cpuid-20250316/0000777001234300001440000000000014765705435011757 5ustar todduserscpuid-20250316/LICENSE0000666001234300001440000004325411437273621012762 0ustar toddusers GNU GENERAL PUBLIC LICENSE Version 2, June 1991 Copyright (C) 1989, 1991 Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA Everyone is permitted to copy and distribute verbatim copies of this license document, but changing it is not allowed. Preamble The licenses for most software are designed to take away your freedom to share and change it. By contrast, the GNU General Public License is intended to guarantee your freedom to share and change free software--to make sure the software is free for all its users. This General Public License applies to most of the Free Software Foundation's software and to any other program whose authors commit to using it. (Some other Free Software Foundation software is covered by the GNU Lesser General Public License instead.) You can apply it to your programs, too. When we speak of free software, we are referring to freedom, not price. Our General Public Licenses are designed to make sure that you have the freedom to distribute copies of free software (and charge for this service if you wish), that you receive source code or can get it if you want it, that you can change the software or use pieces of it in new free programs; and that you know you can do these things. To protect your rights, we need to make restrictions that forbid anyone to deny you these rights or to ask you to surrender the rights. These restrictions translate to certain responsibilities for you if you distribute copies of the software, or if you modify it. For example, if you distribute copies of such a program, whether gratis or for a fee, you must give the recipients all the rights that you have. You must make sure that they, too, receive or can get the source code. And you must show them these terms so they know their rights. We protect your rights with two steps: (1) copyright the software, and (2) offer you this license which gives you legal permission to copy, distribute and/or modify the software. Also, for each author's protection and ours, we want to make certain that everyone understands that there is no warranty for this free software. If the software is modified by someone else and passed on, we want its recipients to know that what they have is not the original, so that any problems introduced by others will not reflect on the original authors' reputations. Finally, any free program is threatened constantly by software patents. We wish to avoid the danger that redistributors of a free program will individually obtain patent licenses, in effect making the program proprietary. To prevent this, we have made it clear that any patent must be licensed for everyone's free use or not licensed at all. The precise terms and conditions for copying, distribution and modification follow. GNU GENERAL PUBLIC LICENSE TERMS AND CONDITIONS FOR COPYING, DISTRIBUTION AND MODIFICATION 0. This License applies to any program or other work which contains a notice placed by the copyright holder saying it may be distributed under the terms of this General Public License. The "Program", below, refers to any such program or work, and a "work based on the Program" means either the Program or any derivative work under copyright law: that is to say, a work containing the Program or a portion of it, either verbatim or with modifications and/or translated into another language. (Hereinafter, translation is included without limitation in the term "modification".) Each licensee is addressed as "you". Activities other than copying, distribution and modification are not covered by this License; they are outside its scope. The act of running the Program is not restricted, and the output from the Program is covered only if its contents constitute a work based on the Program (independent of having been made by running the Program). Whether that is true depends on what the Program does. 1. You may copy and distribute verbatim copies of the Program's source code as you receive it, in any medium, provided that you conspicuously and appropriately publish on each copy an appropriate copyright notice and disclaimer of warranty; keep intact all the notices that refer to this License and to the absence of any warranty; and give any other recipients of the Program a copy of this License along with the Program. You may charge a fee for the physical act of transferring a copy, and you may at your option offer warranty protection in exchange for a fee. 2. You may modify your copy or copies of the Program or any portion of it, thus forming a work based on the Program, and copy and distribute such modifications or work under the terms of Section 1 above, provided that you also meet all of these conditions: a) You must cause the modified files to carry prominent notices stating that you changed the files and the date of any change. b) You must cause any work that you distribute or publish, that in whole or in part contains or is derived from the Program or any part thereof, to be licensed as a whole at no charge to all third parties under the terms of this License. c) If the modified program normally reads commands interactively when run, you must cause it, when started running for such interactive use in the most ordinary way, to print or display an announcement including an appropriate copyright notice and a notice that there is no warranty (or else, saying that you provide a warranty) and that users may redistribute the program under these conditions, and telling the user how to view a copy of this License. (Exception: if the Program itself is interactive but does not normally print such an announcement, your work based on the Program is not required to print an announcement.) These requirements apply to the modified work as a whole. If identifiable sections of that work are not derived from the Program, and can be reasonably considered independent and separate works in themselves, then this License, and its terms, do not apply to those sections when you distribute them as separate works. But when you distribute the same sections as part of a whole which is a work based on the Program, the distribution of the whole must be on the terms of this License, whose permissions for other licensees extend to the entire whole, and thus to each and every part regardless of who wrote it. Thus, it is not the intent of this section to claim rights or contest your rights to work written entirely by you; rather, the intent is to exercise the right to control the distribution of derivative or collective works based on the Program. In addition, mere aggregation of another work not based on the Program with the Program (or with a work based on the Program) on a volume of a storage or distribution medium does not bring the other work under the scope of this License. 3. You may copy and distribute the Program (or a work based on it, under Section 2) in object code or executable form under the terms of Sections 1 and 2 above provided that you also do one of the following: a) Accompany it with the complete corresponding machine-readable source code, which must be distributed under the terms of Sections 1 and 2 above on a medium customarily used for software interchange; or, b) Accompany it with a written offer, valid for at least three years, to give any third party, for a charge no more than your cost of physically performing source distribution, a complete machine-readable copy of the corresponding source code, to be distributed under the terms of Sections 1 and 2 above on a medium customarily used for software interchange; or, c) Accompany it with the information you received as to the offer to distribute corresponding source code. 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These actions are prohibited by law if you do not accept this License. Therefore, by modifying or distributing the Program (or any work based on the Program), you indicate your acceptance of this License to do so, and all its terms and conditions for copying, distributing or modifying the Program or works based on it. 6. Each time you redistribute the Program (or any work based on the Program), the recipient automatically receives a license from the original licensor to copy, distribute or modify the Program subject to these terms and conditions. You may not impose any further restrictions on the recipients' exercise of the rights granted herein. You are not responsible for enforcing compliance by third parties to this License. 7. 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If the distribution and/or use of the Program is restricted in certain countries either by patents or by copyrighted interfaces, the original copyright holder who places the Program under this License may add an explicit geographical distribution limitation excluding those countries, so that distribution is permitted only in or among countries not thus excluded. In such case, this License incorporates the limitation as if written in the body of this License. 9. The Free Software Foundation may publish revised and/or new versions of the General Public License from time to time. Such new versions will be similar in spirit to the present version, but may differ in detail to address new problems or concerns. Each version is given a distinguishing version number. If the Program specifies a version number of this License which applies to it and "any later version", you have the option of following the terms and conditions either of that version or of any later version published by the Free Software Foundation. If the Program does not specify a version number of this License, you may choose any version ever published by the Free Software Foundation. 10. If you wish to incorporate parts of the Program into other free programs whose distribution conditions are different, write to the author to ask for permission. For software which is copyrighted by the Free Software Foundation, write to the Free Software Foundation; we sometimes make exceptions for this. Our decision will be guided by the two goals of preserving the free status of all derivatives of our free software and of promoting the sharing and reuse of software generally. NO WARRANTY 11. BECAUSE THE PROGRAM IS LICENSED FREE OF CHARGE, THERE IS NO WARRANTY FOR THE PROGRAM, TO THE EXTENT PERMITTED BY APPLICABLE LAW. EXCEPT WHEN OTHERWISE STATED IN WRITING THE COPYRIGHT HOLDERS AND/OR OTHER PARTIES PROVIDE THE PROGRAM "AS IS" WITHOUT WARRANTY OF ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. THE ENTIRE RISK AS TO THE QUALITY AND PERFORMANCE OF THE PROGRAM IS WITH YOU. SHOULD THE PROGRAM PROVE DEFECTIVE, YOU ASSUME THE COST OF ALL NECESSARY SERVICING, REPAIR OR CORRECTION. 12. IN NO EVENT UNLESS REQUIRED BY APPLICABLE LAW OR AGREED TO IN WRITING WILL ANY COPYRIGHT HOLDER, OR ANY OTHER PARTY WHO MAY MODIFY AND/OR REDISTRIBUTE THE PROGRAM AS PERMITTED ABOVE, BE LIABLE TO YOU FOR DAMAGES, INCLUDING ANY GENERAL, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES ARISING OUT OF THE USE OR INABILITY TO USE THE PROGRAM (INCLUDING BUT NOT LIMITED TO LOSS OF DATA OR DATA BEING RENDERED INACCURATE OR LOSSES SUSTAINED BY YOU OR THIRD PARTIES OR A FAILURE OF THE PROGRAM TO OPERATE WITH ANY OTHER PROGRAMS), EVEN IF SUCH HOLDER OR OTHER PARTY HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. END OF TERMS AND CONDITIONS How to Apply These Terms to Your New Programs If you develop a new program, and you want it to be of the greatest possible use to the public, the best way to achieve this is to make it free software which everyone can redistribute and change under these terms. To do so, attach the following notices to the program. It is safest to attach them to the start of each source file to most effectively convey the exclusion of warranty; and each file should have at least the "copyright" line and a pointer to where the full notice is found. Copyright (C) This program is free software; you can redistribute it and/or modify it under the terms of the GNU General Public License as published by the Free Software Foundation; either version 2 of the License, or (at your option) any later version. This program is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for more details. You should have received a copy of the GNU General Public License along with this program; if not, write to the Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA. Also add information on how to contact you by electronic and paper mail. If the program is interactive, make it output a short notice like this when it starts in an interactive mode: Gnomovision version 69, Copyright (C) year name of author Gnomovision comes with ABSOLUTELY NO WARRANTY; for details type `show w'. This is free software, and you are welcome to redistribute it under certain conditions; type `show c' for details. The hypothetical commands `show w' and `show c' should show the appropriate parts of the General Public License. Of course, the commands you use may be called something other than `show w' and `show c'; they could even be mouse-clicks or menu items--whatever suits your program. You should also get your employer (if you work as a programmer) or your school, if any, to sign a "copyright disclaimer" for the program, if necessary. Here is a sample; alter the names: Yoyodyne, Inc., hereby disclaims all copyright interest in the program `Gnomovision' (which makes passes at compilers) written by James Hacker. , 1 April 1989 Ty Coon, President of Vice This General Public License does not permit incorporating your program into proprietary programs. If your program is a subroutine library, you may consider it more useful to permit linking proprietary applications with the library. If this is what you want to do, use the GNU Lesser General Public License instead of this License. cpuid-20250316/ChangeLog0000666001234300001440000044556314765705172013550 0ustar toddusersSun Mar 16 2025 Todd Allen * Made new release. Thu Mar 13 2025 Todd Allen * cpuid.c: Updated synth decoding for (0,6),(11,6) to mention Atom P6900, name determined from an Intel SA about DSA. SSG* confirms that Grand Ridge is Crestmont. * cpuid.c: Changed uarch synth for (0,6),(10,15) to Crestmont. The Sierra Forest name appears only under synth decoding, similar to Meteor Lake & Grand Ridge. Sat Mar 1 2025 Todd Allen * cpuid.c: Added synth decoding for (0,6),(11,7) Xeon E-2400 & Xeon 6300. Thu Feb 13 2025 Todd Allen * cpuid.c: Improved synth decoding for (0,6),(10,15),3 Sierra Forest C0, Xeon 6 6700E-Series. Mon Feb 10 2025 Todd Allen * cpuid.c: Changed synth decoding for (8,15),(9,0-7) Van Gogh to Custom APU: Steam Deck. * cpuid.c: Changed synth decoding for (8,15),(9,8-15) Mero to Custom APU: Magic Leap Demophon. Sat Feb 8 2025 Todd Allen * cpuid.c: Changed synth decoding for (11,15),(1,*) to "5th Gen", and uarch decoding for (11,15),(1,*) to "Zen 5c". Mon Jan 13 2025 Todd Allen * cpuid.c: Changed synth decoding for (10,15),(7,0-7) to be Phoenix/Hawk Point. For (10,15),(7,5) specifically, instlatx64 has samples: Ryzen 7 8845HS (Hawk Point) and Ryzen 7 8700G (Phoenix). It may not be possible to differentiate the cases with just cpuid data. Tue Jan 7 2025 Todd Allen * cpuid.c: Added synth decoding for (0,6),(0,9,2) Timna, a canceled precursor to Banias, circa 2000. Tue Jan 7 2025 Todd Allen * cpuid.c: Improved synth decoding for (0,6),(12,5) Arrow Lake-H and its A1 (2) stepping. * cpuid.c: Improved synth decoding for (0,6),(12,6) Arrow Lake-H and its A0/B0 (2) stepping. * cpuid.c: Improved synth decoding for (0,6),(11,5) Arrow Lake-U and its A1 (0) stepping. Mon Oct 28 2024 Todd Allen * cpuid.c: Added AMD PkgType for Ryzen 9000 (11,15),(4,*). * cpuid.man: Added 57896 doc. Wed Oct 23 2024 Todd Allen * Made new release. Wed Oct 23 2024 Todd Allen * cpuid.c: Fixed cut&paste error in print_80000025_ebx, possibly resulting in SIGSEGV: cached segments hard limit is only bit 11. Mon Oct 21 2024 Todd Allen * Made new release. Fri Oct 18 2024 Todd Allen * cpuid.c: Added 7/1/eax MOVRS instructions. * cpuid.c: Added 7/1/ecx RDMSR/WRMSRNS immediates supported. * cpuid.c: Renamed 7/1/edx AVI-COMPLEX to AMX-complex. * cpuid.c: Added leaf 0x1e subleaf walk with hard-coded max_subs of 1. * cpuid.c: Added 0x1e/1 subleaf. * cpuid.c: Changed leaf 0x23 subleaf walk to use a mask of subleaves. * cpuid.c: Added 0x23/4 subleaf. * cpuid.c: Added 0x23/5 subleaf. Fri Oct 18 2024 Todd Allen * cpuid.c: Updated synth decoding for (0,6),(11,5) to Arrow Lake-U. * cpuid.c: Changed uarch decoding for (0,6),(11,5) from Redwood Cove+Crestmont (from 319433-046's Meteor Lake claim) to Lion Cove+Skymont (from 319433-054's Arrow Lake-U claim). * cpuid.c: Added uarch & synth decoding for Intel's (4,15),(0,0) and (4,15),(0,1): Nova Lake (Panther Cove), based on 319433-054's MSR_CPUID_table*. Wed Oct 16 2024 Todd Allen * cpuid.c: #ifdef'ed #define _GNU_SOURCE, in case it already was defined. * cpuid.c: Marked real_get()'s quiet formal as UNUSED, which it will be if !defined(USE_CPUID_MODULE). * cpuid.c: Resized decode_amd_model's proc formal to 34 bytes, which is just a tuned value: it's large enough to accomodate any returned strings, and small enough not to trip an overzealous gcc -Wformat-overflow=2 warning when this is used as an sprintf argument in decode_override_brand. Wed Oct 16 2024 Todd Allen * cpuid.c: Added cpuset_destroy to real_setup USE_SCHED_SETAFFINITY_NP, per Christof Meerwald. Wed Oct 16 2024 Todd Allen * cpuid.c: Corrected print_80000001_ebx_amd PkgType logic to use MaskMm (AMD XM & high-order M bit), similar to previous changes to use FMm, etc. in decode_synth_amd(). * cpuid.c: Added print_80000001_ebx_amd PkgType for (10,15),(1,*) Genoa, (10,15),(10,*) Bergamo/Siena, and (11,15),(0,*) Turin. * cpuid.c: Added 0x8000000a/edx EXITINFO1 non-interceptible shutdown. * cpuid.c: Added 0x8000001a/eax 512-bit SSE executed full-width. * cpuid.c: Added 0x8000001b/eax IBS load latency filtering support. * cpuid.c: Added 0x8000001b/eax simplified DTLB page size & miss report. * cpuid.c: Added 0x8000001f/eax guest intercept control support. * cpuid.c: Added 0x8000001f/eax segmented RMP support. * cpuid.c: Added many new fields to 0x80000021/eax. * cpuid.c: Added 0x80000021/ebx return addr predictor size. * cpuid.c: Widened 0x80000022/ebx number of available UMC PMCs. * cpuid.c: Added leaf 0x80000025 Segmented RMP Table. * cpuid.man: Added new AMD docs. Tue Oct 15 2024 Todd Allen * cpuid.c: Fixed Haiku patch to use pthread_self, per Christof Meerwald. Tue Oct 15 2024 Todd Allen * cpuid.c: Manually reverted Christof Meerwald's first NetBSD patch, and applied his replacement NetBSD & Haiku patch. * cpuid.c: Cleaned up positions of the OS-specific #if/#ifdef blocks. * cpuid.c: In real_get(), #ifdef'ed cpuid module lseek & read with USE_CPUID_MODULE. * cpuid.c: Removed OS-specific lseek & off_t hacks, because they only were needed by the real_get() code, now under #ifdef USE_CPUID_MODULE, and that's Linux-specific. Tue Oct 15 2024 Todd Allen * cpuid.c: Added 7/1/ebx IA32_MISC_ENABLE cannot limit CPUID max. Fri Oct 11 2024 Todd Allen * cpuid.c: Added (synth) decoding for Intel Core Ultra 200S. * cpuid.c: Added (synth) decoding for Intel Core Ultra 200V. * cpuid.c: Changed Skymont & Lion Cove processes to TSMC N3/N3B. * cpuid.man: Added new Intel docs. Tue Sep 24 2024 Christof Meerwald * cpuid.c: Add support for NetBSD. Mon Sep 16 2024 Todd Allen * Made new release. Sun Sep 15 2024 Todd Allen * cpuid.c: Updated AMD Zen 3/4/5 die processes with specific TSMC nodes, where known & consistent. (Earlier generations appear to be a mix of GloFo & TSMC.) * cpuid.c: Updated AMD Instinct MI300 CPUs to MI300A/C. Sun Sep 15 2024 Todd Allen * cpuid.c: Based on LLVM patch from AMD's Ganesh Gopalasubramanian: * cpuid.c: Added numerous early AMD core names for Zen 5. * cpuid.c: Updated AMD 4700S Desktop Kit from Oberon, the GPU name, to Cardinal, the CPU core name. * cpuid.c: Added AMD 4800S Desktop Kit ProjectX core name. Fri Sep 13 2024 Todd Allen * Made new release. Fri Sep 13 2024 Todd Allen * cpuid.c: Fixed a warning about a potential buffer overflow in decode_synth_amd detected by gcc at -O2 (detected via an interprocedural optimaztion, I think). Thu Sep 12 2024 Todd Allen * Made new release. Wed Sep 11 2024 Todd Allen * cpuid.c: For (0,6),(11,14),0 Intel N-Series, add Twin Lake core name. It can only be distinguished with MSR IA32_PLATFORM_ID (17h) -- or by brand name (which would be unreliable if new brandings appear). Tue Aug 27 2024 Todd Allen * cpuid.c: For (synth) decoding of VIA (0,7),(5,11), removed Zhaoxin KaiXian KX-7000 possibility, based on findings that those likely are rebadged Intel CPUs instead. Mon Aug 26 2024 Todd Allen * cpuid.c: In decode_uarch_intel(), for Jintide Gen1, used family field to indicate that they're based on Intel Skylake. * cpuid.c: In decode_uarch_via(), for ZhangJiang CPU's, used family field to to indicate that they're based on VIA C7. Did not provide a family for WuDaoKou or LuJiaZui, because it isn't clear how far they have diverged. Tue Aug 20 2024 Todd Allen * cpuid.c: Changed comments after 743844-012 corrects (0,6),(11,15),5 to be stepping H0. * cpuid.c: In decode_uarch_hygon(), widened Moksha name to include all of Hygon family (9,15). Based on Jinke F. patch to perfmon2, which applies the name to all of fam18h. * cpuid.c: In decode_uarch_hygon(), used family field to indicate that it's based on AMD Zen. Mon Aug 19 2024 Todd Allen * cpuid.c: Added missing AMD Ryzen numbers: Rembrandt=6000/7000, Mendocino=7000, Raphael=7000, Phoenix=7000/8000, Granite Ridge=9000. Sun Aug 11 2024 Todd Allen * cpuid.c: Updated synth decoding for (0,6),(10,15) to detect Intel Xeon 6 (Sierra Forest) CPUs. Thu Jul 18 2024 Todd Allen * cpuid.c: For (0,6),(8,15),8, add Xeon Scalable (5th Gen). Some of these have been rebranded from 4th Gen to 5th Gen: LCC U1. Wed Jul 17 2024 Todd Allen * cpuid.c: Added 0x80000007/edx fast CPPC, mentioned in the PPR for Family 19h Model 61h, Revision B1. Tue Jul 16 2024 Todd Allen * Made new release. Mon Jul 15 2024 Todd Allen * cpuid.c: For AMD Zen CPUs, overhauled uarch & synth decoding to determine the CPU model from only the extended model & high bit of the model field. Also, determine the stepping (revision) mechanically from the low-order 3 bits of the model and the stepping number. This should correctly identify retail Zen 5 Ryzen's. This also corrects some stepping bugs from the Zen 1 era. Tue Jul 9 2024 Todd Allen * Made new release. Sat Jul 6 2024 Todd Allen * cpuid.c: Added 6/eax IA32_HWP_CTL MSR supported. * cpuid.c: Added 7/2/edx MONITOR perf unaffected by tbl overflow. * cpuid.c: Added synth decoding for Hygon Dhyana B1 & C2. Still no information on a uarch name for these, so decode_uarch_hygon() remains silent for them. Tue May 28 2024 Todd Allen * cpuid.c: Added uarch synth decoding for (0,6),(5,5),11 Cooper Lake. The synth decoding was already present. Its absence from decode_uarch_intel was just an oversight. Sun May 12 2024 Todd Allen * cpuid.c: Fixed division-by-zero error in decode_mp_synth Intel leaf 1/4 (zero fallback). This is meant for old, incomplete cpuid -r dumps, but even for hand-crafted dumps, determining 0 cores and then dividing by that 0 is unacceptable. Tue Apr 9 2024 Todd Allen * Made new release. Sun Apr 7 2024 Todd Allen * cpuid.c: Added 0x8000000a/edx PMC virtualization. * cpuid.c: Added 0x8000000a/edx idle HLT intercept. * cpuid.c: Added 0x8000001f/eax PMC virtual support for SEV-ES/SNP. * cpuid.c: Added 0x8000001f/eax mention of SEV-SNP to existing fields. * cpuid.c: Added 0x8000001f/eax RMPREAD instruction. * cpuid.c: Added 0x8000001f/eax secure AVIC support. * cpuid.c: Added 0x8000001f/eax allowed SEV features support. * cpuid.c: Added 0x8000001f/eax write to hypervisor in-used allowed. * cpuid.c: Added 0x8000001f/eax IBPB on entry support. Sun Apr 7 2024 Todd Allen * cpuid.c: Added Siena to (10,15),(10,x) synth decoding, based on 58268 Arch Overview. * cpuid.man: Added 58268: AMD EPYC 8004 Series Architecture Overview. Sat Apr 6 2024 Todd Allen * cpuid.c: Added preliminary (10,15),(7,12) Hawk Point synth decoding. Mon Apr 1 2024 Todd Allen * cpuid.c: Fixed spelling: EPGR->EGPR (extended GPR's). Sat Mar 30 2024 Todd Allen * Made new release. Sat Mar 30 2024 Todd Allen * cpuid.c: Added 5/ecx monitorless MWAIT. * cpuid.c: Added 7/1/edx user-timer events. * cpuid.c: Added 7/1/edx AVX10 instructions. * cpuid.c: Added 7/1/edx APX advanced performance extensions. * cpuid.c: Added 7/1/edx MWAIT instruction (overrides 1/ecx[3]). * cpuid.c: Added Intel-specific print_instr_synth_intel to determine presence of MWAIT from 1/ecx and/or 7/1/edx. * cpuid.c: Updated 12/n/ecx section property values 1 & 3. * cpuid.c: Added 14/0/ebx PTTT processor trace trigger tracing. * cpuid.c: Added 14/1/eax number of IA32_RTIT_TRIGGERx_CFG MSRs, including D4_IMAGES decoding. * cpuid.c: Added 14/1/ecx flags. * cpuid.c: Added MINUS24_IMAGES decoding for 0xf/1/eax QoS monitoring counter size. * cpuid.c: Added 0x23/1 sub-header: Architecture Performance Monitoring Extended Counters Supported Bitmaps (0x23/1), and simplified fields. * cpuid.c: Added 0x23/2 sub-header: Architecture Performance Monitoring Extended Auto Counter Reload (ACR) Bitmaps (0x23/2), expanded on existing field descriptions, and added "can cause reloads" fields. * cpuid.c: Added 0x24 leaf: Converged Vector ISA. * cpuid.c: Added to print_d_n: new XSAVE area: 19 for APX EPGR (extended general purpose registers). * cpuid.man: Added new Intel 355828 (APX) doc. Tue Mar 26 2024 Todd Allen * cpuid.c: Added uarch decoding for (11,15),(1,0), which is mentioned with (11,15),(0,0) in the title of 58088 AMD 1Ah Models 00h-0Fh and Models 10h-1Fh ACPI v6.5 Porting Guide. Mon Mar 25 2024 Todd Allen * cpuid.c: Expanded br.xeon test to include brands with "XEON", and br.scalable to include "BRONZE", "PLATINUM", etc. (all caps), based on Emerald Rapids (engr?) sample. I don't know if this is a change Intel will use moving forward, or a quirk of engr samples, but checking for it is harmless enough. Sun Mar 24 2024 Todd Allen * Made new release. Sun Mar 24 2024 Todd Allen * cpuid.c: Updated synth decoding for (0,6),(12,15),2 Emerald Rapids A1/R1. * cpuid.man: Added new Intel docs. Sat Mar 23 2024 Todd Allen * cpuid.c: In do_real(), for the 0x1b leaf, add a sanity check to avoid infinite recursion if a hypervisor never reports invalid (0) on any subleaf. The sanity check checks for a subleaf identical to its predecessor, which is not reasonable. Sat Mar 23 2024 Todd Allen * cpuid.c: Added synth & uarch decoding for (0,6),(13,13) Clearwater Forest. * cpuid.c: Updated (0,6),(8,12),1 to include stepping B0, from ILPMDF* * cpuid.c: Updated (0,6),(11,15),5 to Raptor Lake stepping H0, based on preponderance of evidence. * cpuid.c: Added synth decoding for (0,6),(10,10) Core Ultra CPUs. * cpuid.c: Updated (0,6),(11,7) to include Core i*-14000. Some CPUs having this branding, and it's not clear what's different from the Core i*-13000 versions. The steppings don't seem to matter. Inspection suggests maybe CET_SSS. * cpuid.c: Corrected synth decoding for (10,15),(1,8) Storm Peak: Ryzen Threadripper 7000. * cpuid.c: Added synth decoding for (10,15),(7,5),2 AMD Ryzen Phoenix F2. * cpuid.c: Added very preliminary uarch decoding for (10,15),(6,0) and (10,15),(7,0), both Zen 5. * cpuid.c: Changed preliminary synth decoding for (0,6),(11,5) to Arrow Lake, based on Intel SDE 9.33.0. * cpuid.c: Added synth decoding for (0,6),(8,13),0 Tiger Lake-H P0 stepping. * cpuid.c: Added synth decoding for (0,6),(11,13),0 Lunar Lake A0 stepping. * cpuid.c: Changed uarch decoding for (0,6),(13,13) to Darkmont, the presumed uarch for Clearwater Forest. Sat Mar 23 2024 Todd Allen * cpuid.c: Added 12/1/eax AEX attribute enabled, as described by Scott Raynor, Intel. * cpuid.c: Added 7/1/eax NMI-source reporting. * cpuid.c: Added 7/1/eax INVD prevention after BIOS done. * cpuid.c: Renamed 7/1/ebx PKNDKB instruction. * cpuid.c: Added 7/1/edx URDMSR, UWRMSR instructions. * cpuid.c: Added 0xa/ebx additional events. * cpuid.c: Added 0xf/1/eax non-CPU agent features. * cpuid.c: For 0xf/0/edx supports L3 cache monitoring, removed redundant "QoS". * cpuid.c: Renamed print_10_n_{eax,ecx} -> print_10_12_{eax,ecx}. * cpuid.c: Added 0x10/0/ebx cache bandwidth allocation supported. * cpuid.c: Replaced 0x10/{1,2}/ecx: non-CPU agent support. * cpuid.c: Renamed 0x10/{1,2}/ecx: non-contiguous bitmask supported. * cpuid.c: Added 0x10/5 Cache Bandwidth Allocation decoding. * cpuid.c: Renamed 0x23/0/ebx IA32_PERFEVTSELx EQ bit supported. * cpuid.c: Added 0x23/2 ACR counters bitmaps. Sat Sep 23 2023 Todd Allen * cpuid.c: Corrected synth decoding for (10,15),(10,x) to EPYC (4th Gen) (server CPUs), instead of Ryzen (desktop CPUs). Wed Sep 13 2023 Todd Allen * cpuid.c: Added (0,6),(12,12) Panther Lake synth decoding from LX*, but left out corresponding uarch decoding which is alls rumors currently: maybe Panther Cove, Cougar Cove, or something else. Tue Sep 5 2023 Todd Allen * cpuid.c: Added hypervisor+0xc ebx isolation type new value: TDX (3) from LX*. Tue Sep 5 2023 Todd Allen * cpuid.c: Added (11,5),(0,0) Zen 5 uarch from LX*. * cpuid.c: To decode_uarch_intel, added (0,6),(11,12) & (0,6),(11,13) Lion Cove & Skymont as uarch underpinning Lunar Lake. Wed Aug 9 2023 Todd Allen * cpuid.c: Added 0x80000021/eax selective branch prediction barrier, PRED_CMD[IBPB] flushes branch type preds. They appear to be only synthetic flags provided for hypervisor guests! * cpuid.c: Added 0x80000021/eax CPU not affected by SRSO flag, from LX*. Sat Aug 5 2023 Todd Allen * cpuid.c: Added (10,15),(8&9,0) uarch & synth decoding for AMD Instinct MI300, from LKML: https://lkml.org/lkml/2023/7/20/668 patches. In the past, Instinct MI* described just the GPU, but they seem to be conflating them into a product name here. Tue Aug 1 2023 Todd Allen * cpuid.: Added prelim uarch decoding for (11,15),(2,0) & (11,15),(4,0), both Zen 5, based on engr samples. No synth decoding yet, because it isn't known yet. * cpuid.c: Added prelim synth decoding for (0,6),(11,12) Lunar Lake from Intel SDE 9.24.0 misc/cpuid/lnl/cpuid.def. No uarch decoding, because Lunar Lake uarch name is not known yet. * cpuid.c: Added prelim synth decoding for (0,6),(9,5) Sapphire Rapids from Intel SDE 9.24.0 misc/cpuid/spr/cpuid.def. Fri Jul 14 2023 Todd Allen * cpuid.c: Added synth decoding for (0,6),(11,7),0 Raptor Lake A0 stepping, from Coreboot*. Mon Jul 3 2023 Todd Allen * cpuid.c: Added 7/1/eax SHA512, SM3 & SM4 instructions. * cpuid.c: Added 7/1/ebx TSE PBNDKB instruction. * cpuid.c: Added 7/1/ebx AVX-VNNI-INT16 instructions. * cpuid.c: Added 7/1/edx UIRET flexibly updates UIF. * cpuid.c: Added 0x1b/2 TSE target. * cpuid.c: Corrected sub-leaf walk of leaf 0x1b to stop immediately if sub-leaf 0 is invalid. Sun Jul 2 2023 Todd Allen * cpuid.c: Added (uarch synth) & (synth) decoding for (0,6),(12,5) Arrow Lake based on Lion Cove & Skymont. Sat Jul 1 2023 Todd Allen * cpuid.c: Added 0x80000008/ebx IBPB_RET. * cpuid.c: Renamed 0x8000000a/edx extended LVT AVIC access changes. * cpuid.c: Renamed 0x8000000a/edx guest VMCB addr check. * cpuid.c: Added 0x8000000a/edx bus lock threshold. * cpuid.c: Renamed several 0x80000020 leaves & fields. * cpuid.c: Added 0x80000020/0/ebx assignable bandwidth monitoring counters. * cpuid.c: Added 0x80000020/0/ebx SDCI allocation enforcement * cpuid.c: Added 0x80000020/5 PQoS Assignable Bandwidth Monitoring Counters. Fri Jun 30 2023 Todd Allen * cpuid.c: Added (synth) decoding for (0,6),(10,10),4 Meteor Lake-M C0 stepping from Coreboot*. Wed Jun 14 2023 Todd Allen * Made new release. Wed Jun 14 2023 Todd Allen * cpuid.c: Improved (synth) identification for (0,6),(5,5),10 Intel Xeon Scalable (3rd Gen) (Cooper Lake A0), based on 634897 doc. * cpuid.c: Changed (synth) identification for (0,6),(6,12) Intel Xeon D-1700/2700 (Ice Lake-D). Intel docs 714071 claim the stepping is U1/U2, which contradicts ILPMDF*. I'm using the actual docs. * cpuid.c: Updated comments with new Intel docs. * cpuid.c: Changed "Intel Scalable" to "Intel Xeon Scalable". * cpuid.man: Added new Intel docs. * cpuid.man: Added 613537, the new pub number for 336065, Intel Xeon Processor Scalable Family Specification Update. Mon Jun 5 2023 Todd Allen * cpuid.c: Added (synth) differentiation for (0,6),(9,10),4 Intel Pentium Gold 8500 series. Sat May 13 2023 Todd Allen * cpuid.c: Made the (simple synth) fields non-default. Too many people were interpreting them as definitive and ignoring the much better (synth) leaf, which uses the entirety of cpuid information. This impacts leaves 1, 0x80000001, and 0x80860001. The (simple synth) fields still are available, but only with the -S/--simple option. * cpuid.c: Organized option flags that need to be passed deeply down in the print_reg* functions into a new print_opts_t, which will make future options easier to add. * cpuid.c: Renamed the old "try" variables to "sub". The word "try" was a remnant of the original leaf 4 subleaf implemntation, before subleaves were commonplace. For leaf 4, one just kept "trying" to read more cache data until it failed. But most subleaves don't work that way. Sat May 13 2023 Todd Allen * cpuid.c: Updated (synth) decoding for (0,6),(8,15),{7,8} to mention steppings {S2,S3} from ILPMDF* 20230512. * cpuid.c: Added (synth) decoding for (0,6),(11,14) pure Atom x7000E, as a variation on other Alder Lake-N CPUs. * cpuid.c: Added (synth) decoding for (0,6),(9,10),4 Atom C1100 Arizona Beach. Thu May 5 2023 Todd Allen * Made new release. Fri May 5 2023 Todd Allen * cpuid.c: Fixed bug in (multi-processing synth) in the recently rewritten decode_mp_synth(). The CPU counts for higher levels were not dividing out counts from lower levels. This is analogous to the way print_apic_synth() subtracts out bit widths from lower levels. Fri May 5 2023 Todd Allen * cpuid.c: Differentiate Core i3-N300 N-Series from ordinary N-Series. (They appear to differ only in branding.) Fri Apr 28 2023 Todd Allen * cpuid.c: Added hypervisor+4/eax bit 21: use hypercalls for MMIO config space I/O, based on LX* (Michael Kelley PCI pass-thru patches). Not documented by Microsoft yet. Tue Apr 25 2023 Todd Allen * cpuid.c: In real_setup(), make inability to switch to CPU 0 no longer a fatal error. It is allowable for CPU 0 to be offlined, just like any other. Tue Apr 18 2023 Todd Allen * cpuid.c: Added (synth) decoding for (0,6),(8,15) Xeon W version of Sapphire Rapids, from instlatx64 sample. * cpuid.c: Corrected (synth) & (uarch synth) for Sapphire Rapids: family is Golden Cove, not Sunny Cove. * cpuid.c: Added (synth) & (uarch synth) Emerald Rapids family: Raptor Cove. * cpuid.c: Added (synth) & (uarch synth) Granite Rapids family: Redwood Cove. * cpuid.c: In decode_uarch_intel, mark Sapphire Rapids, Emerald Rapids & Granite Rapids with core_is_uarch to avoid replicating the name in (synth). Sun Apr 16 2023 Todd Allen * cpuid.c: Added (synth) decoding for (0,6),(10,10),2 Meteor Lake-M B0 from Coreboot*. Thu Apr 6 2023 Todd Allen * Made new release. Thu Apr 6 2023 Todd Allen * cpuid.c: Fixed bug in print_apic_synth() when interpreting leaf 0xb and 0x1f bit widths: In fact, they are bit *offsets*, different from the *widths* of leaf 4! So the (APIC width synth) often has been off by 1, and the (APIC synth) PKG_ID & CORE_ID values often have been shifted incorrectly. * cpuid.c: For 0xb/*/eax & 0x1f/*/eax, rename field to "bit width of level & previous levels" to reflect this definition. * cpuid.c: In print_apic_synth(), decode_mp_synth(), and print_mp_synth(), support APIC bit fields for the newest 4 topology layers: module, tile, die, die group. And for the mp version, also the older cu & pkg levels. * cpuid.c: In print_apic_synth(), use the extended APIC ID's when available in a variety of leaves. * cpuid.c: In print_apic_synth() & decode_mp_synth(), support leaf 0xb method for AMD/Hygon. * cpuid.c: In decode_mp_synth(), for the 1/0x80000008 method, use the same family-specific technique to differentiate CU's from cores, or cores from threads as in print_apic_synth(). Tue Apr 4 2023 Todd Allen * cpuid.c: Added prelim Bergamo A1 stepping from sample from @YuuKi_AnS. Fri Mar 31 2023 Todd Allen * cpuid.c: Added 7/1/edx AMX-COMPLEX instructions. * cpuid.c: Added 7/2/edx UC-lock disable. * cpuid.c: Added 0x10/n/ecx non-contiguous 1s value supported. * cpuid.c: Added 0x1c/ecx event logging supported bitmap. * cpuid.c: Added 0x23/0/ebx decoding. Tue Mar 28 2023 Todd Allen * cpuid.c: Decode 0x80000026/1/ebx core type & native model. Tue Mar 28 2023 Todd Allen * cpuid.c: For 0x80000021/eax, capitalize REP STOSB & REP CMPSB to match Intel versions in 7/1/eax. * cpuid.c: For 0x80000022/ecx, shorten description, show bitmask only in hex. Tue Mar 28 2023 Smita Koralahalli Channabasappa * cpuid.c: Update CPUID utility with new feature bits as documented in the AMD Processor Programming Reference for Family 19h and Model 11h: 0x8000000a/edx extended LVT offset fault change 0x80000021/eax enhanced predictive store forwarding, FSRS, FSRC, FsGsKernelGsBaseNonSerializing 0x80000022/ebx number of available UMC PMCs 0x80000022/ecx bitmask representing active UMCs Tue Mar 28 2023 Todd Allen * cpuid.c: Differentiate preliminary (uarch synth) for (0,6),(10,10); (0,6),(10,11); (0,6),(10,12); and (0,6),(11,5) Crestmont Atom cores from their Redwood Cove counterparts. * cpuid.c: Add preliminary (synth) & (uarch synth) for (0,6),(12,6) Lion Cove & Skymont, from LX*. Sat Mar 25 2023 Todd Allen * cpuid.c: Added 12/0/eax SGX ENCLS EUPDATESVN bit. * cpuid.c: Added 0x1f/*/ecx level type value "die group (6)". Mon Mar 20 2023 Todd Allen * cpuid.c: Added (synth) decoding for (0,6),(8,15) Sapphire Rapids D & E0 steppings from coreboot*. * cpuid.c: Improved (synth) decoding for (0,6),(6,10) Scalable 3rd Gen Xeons to Ice Lake-SP. Also, improved decoding for engr samples where the brand string omits Xeon & Bronze/Silver/Gold/Platinum. Fri Mar 17 2023 Todd Allen * cpuid.c: Improved (synth) decoding for (0,6),(11,14) Intel N-Series. * cpuid.c: Differentiate (synth) & (uarch synth) for (0,6),(11,14) Alder Lake-N based on core type, much like for other Alder Lake models. This corrects the cores to Gracemont. As for Golden Cove, perhaps P-cores never will exist for this model but, if they do, they should now be decoded correctly. * cpuid.man: Added 759603: Intel Processor and Intel Core i3 N-Series Datasheet, Volume 1 of 2. * cpuid.c: Updated (synth) decoding for (0,6),(11,15),5 with Raptor Lake-S/HX/P. * cpuid.c: Updated (synth) decoding for (0,6),(11,10) with Raptor Lake-H/U/P. Mon Mar 6 2023 Todd Allen * Made new release. Sun Mar 5 2023 Todd Allen * Based on Intel-Linux-Processor-Microcode-Data-Files (ILPMDF*), made the following (synth) changes: * cpuid.c: Updated (0,6),(3,7),8 Bay Trail with stepping name C0. * cpuid.c: Added (0,6),(4,5),1 Haswell-ULT C0/D0 stepping. * cpuid.c: Corrected (0,6),(4,6),1 Crystal Well to C0 stepping. * cpuid.c: Updated (0,6),(4,7),1 Broadwell to include E0 stepping. * cpuid.c: Added (0,6),(5,5),3 Skylake B1 (Xeon Scalable). * cpuid.c: Added (0,6),(5,5),5 Skylake A0 (Xeon Scalable). * cpuid.c: Added (0,6),(5,5),11 Cooper Lake A1 (Xeon Scalable). * cpuid.c: Updated (0,6),(5,14),3 Skylake-H/S/E3, adding N0 & S0 steppings. * cpuid.c: Added (0,6),(6,10),5 Ice Lake C0 (Xeon Scalable). * cpuid.c: Added (0,6),(6,12),1 Ice Lake B0. * cpuid.c: Updated (0,6),(8,6),4 Snow Ridge with stepping B0. * cpuid.c: Updated (0,6),(8,6),5 Snow Ridge with stepping B1. * cpuid.c: Added (0,6),(8,6),1 Lakefield B2/B3 stepping. * cpuid.c: Corrected (0,6),(8,12),1 Tiger Lake stepping to B1. * cpuid.c: Added (0,6),(8,12),2 Tiger Lake C0. * cpuid.c: Added (0,6),(8,14),10 Coffee Lake D0. * cpuid.c: Added (0,6),(8,14),13 Whiskey Lake-U V0 stepping. * cpuid.c: Added (0,6),(8,15) Sapphire Rapids numerous steppings. * cpuid.c: Updated (0,6),(9,12) Jasper Lake with stepping A1. Thu Mar 2 2023 Todd Allen * cpuid.c: Differentiate (0,6),(8,10) Lakefield P-cores from Tremont E-cores, much as I previously did for Alder Lake & Raptor Lake. * cpuid.c: In decode_uarch_intel, for known Hybrid chips (Alder Lake, Raptor Lake & Lakefield), only decode the uarch if it's one of the two known hybrid types. However, some (0,6),(9,7) Alder Lake's are non-hybrid (Golden Cove only), so also decode core type == 0x00 there. * cpuid.c: In the Intel Core era, uarch families are identified only by the initial uarch in the family. So the family names in {braces}, which also are uarch names, can be confusing. So, change (synth) and (uarch synth) for those families to explain the relationships between the subsequent uarch and the initial uarch, in the form of "shrink of", "optim of", and the unusual "backport of". * cpuid.c: Added (4th Gen) to the (synth) description of (10,15),(1,*) AMD EPYC Genoa. * cpuid.c: Updated (synth) for (10,15),(7,*) AMD Phoenix & Phoenix 2 CPUs to claim 4nm process. Tue Feb 28 2023 Todd Allen * Made new release. Sun Feb 26 2023 Todd Allen * cpuid.c: Corrected 7/1/eax fast REP instructions, where I'd left the REP prefix out of the description. Wed Feb 22 2023 Todd Allen * cpuid.c: Added 7/1/eax FRED & LKGS bits, from Intel Flexible Return and Event Deliver (FRED). * cpuid.man: Added Intel Flexible Return and Event Deliver (FRED). * cpuid.c: Clarified 7/1/eax ArchPerfmonExt, which indicates that leaf 0x23 is valid. Fri Feb 17 2023 Todd Allen * cpuid.c: Added (uarch synth) decoding for AMD Ryzen (Phoenix E0), based on sample from bakerlab.org, which I missed on Oct 3 2022, when I added the (synth) decoding. * cpuid.c: Added 0x80000001/ebx PkgType decoding for AMD (10,15) Family 19h CPUs: (2,1) Vermeer, (5,1) Cezanne/Barcelo, (6,1) Raphael, and (7,0) Phoenix, based on their respective PPPR's. Sun Feb 12 2023 Todd Allen * cpuid.c: Added very early (synth) decoding for Lunar Lake. There is no corresponding (uarch synth) decoding, because no name is yet known for the uarch. Sat Feb 11 2023 Todd Allen * cpuid.c: Added (0,6),(9,10) Alder Lake Core names: i*-12000. * cpuid.c: Differentiate (0,6),(9,7) & (0,6),(9,10) Alder Lake Gracemont E-cores from Golden Cove P-cores. * cpuid.c: Differentiate (0,6),(11,7); (0,6),(11,10) & (0,6),(11,15) Raptor Lake Gracemont E-cores from Raptor Cove P-cores. * cpuid.c: Added (synth) & (uarch synth) decoding for (10,15),(7,8) Phoenix 2, from Coreboot*. * cpuid.c: Renamed print_hypervisor_3_eax_xen to print_hypervisor_3_0_eax_xen. * cpuid.c: Added print_hypervisor_3_0_ebx_xen and decode Xen tsc mode. * cpuid.c: Added (synth) decoding for (10,15),(6,1,1) Raphael B1. Fri Jan 20 2023 Todd Allen * Made new release. Fri Jan 20 2023 Todd Allen * Eliminate reliance on "old" build system. Instead, for the cpuid.i386 and cpuid.x86_64, meant to be executable anywhere, including on old hardware & distros, use static builds. They're much bigger, but utterly immune to library changes. Wed Jan 18 2023 Todd Allen * Intel's 13th Generation Core datasheet provides stepping names as well as numbers! So: * cpuid.c: Added synth decoding for (0,6),(11,7) Raptor Lake B0 stepping. * cpuid.c: Added synth decoding for (0,6),(11,15) Raptor Lake C0 steppings, and clarified case for unknown stepping. * cpuid.man: Added 743844: 13th Generation Core datasheet. * cpuid.c: Fixed (0,6)(12,15) synth typo: Emearld Rapids. Tue Jan 17 2023 Todd Allen * cpuid.c: Added 6/eax IA32_HW_FEEDBACK_THREAD_CONFIG bit 25. * cpuid.c: Added 7/0/edx SGX-KEYS: SGX attestation services. * cpuid.c: Clarified 7/0/edx IA32_MCU_OPT_CTRL SRBDS mitigation MSR. * cpuid.c: Clarified 7/0/edx IA32_TSX_FORCE_ABORT MSR. * cpuid.c: Added 7/1/edx CET_SSS: shadow stacks w/o page faults. * cpuid.c: Added several 7/2/edx bits. * cpuid.c: In 0xd/0/eax, corrected CET_U & CET_S, which were IA32_XSS. * cpuid.c: In 0xd/0/eax, removed the IA32_XSS bits, which aren't relevant for XCR0. * cpuid.c: For 0xd/1/ecx, enumerate the IA32_XSS bits instead of a hex bitmask. * cpuid.c: For 0xd, added IA32_XSS PASID state (couple places). * cpuid.c: Renamed 0x1a: Native Model ID. * cpuid.c: Added synth & uarch decoding for (0,6),(11,15) Raptor Lake from MSR_CPUID_table*. * cpuid.c: Added synth decoding for (0,6),(9,7),5 Pentium Gold G7400, based on instlatx64 sample. * cpuid.c: Added rudimentary synth decoding for future (0,6),(12,15) Emerald Rapids CPUs. * cpuid.c: Added 7/1/eax LASS: linear address space separation. * cpuid.c: Corrected 0x18/n/edx maximum number of addressible IDs, which should use minus-one notation. Tue Jan 17 2023 Todd Allen * cpuid.c: Certain leaves cannot be displayed correctly in isolation, i.e. without information about other leaves saved in the stash. For example, the display for leaf 3 uses bits saved from leaf 1. If the -l/--leaf option is used to restrict cpuid to reading only a single leaf, such leaves now are displayed as raw hex, rather than with incorrect information. This is handled by passing a NULL stash to print_reg() and below, and by many new checks for a NULL stash. Thanks to Bill Zissimopoulos for the bug report. Mon Jan 9 2023 Todd Allen * cpuid.c: Updated cache associativity strings used in 0x80000006 and 0x80000019 leaves to use value ranges, as in AMD docs. * cpuid.c: Fixed mistake in AMD L3 range reservation support: it's in 0x80000020/0 register EBX, not ECX. * cpuid.c: Added 0x80000026/0/edx extended APIC ID. Tue Dec 13 2022 Todd Allen * cpuid.c: Added synth & uarch decoding for (10,15),(1,1) Genoa, from AMD 57095 revision guide. * cpuid.man: Added AMD 57095 revision guides, and some older guides that I'd forgotten. Thu Dec 1 2022 Todd Allen * Made new release. Wed Nov 30 2022 Todd Allen * Clarified synth decoding for Intel Xeon D-1700. Wed Nov 30 2022 Todd Allen * Added uarch & synth decoding for AMD 4800S Desktop Kit, based on instlatx64 sample. The generation is known to be Zen 2 (7nm), but the core is unknown. I heard speculation for each of Ariel (rejected PlayStation 5 CPU), or Lockhart/Scarlett (rejected Xbox CPU). * Added uarch decoding for AMD Genoa A1, based on instlatx64 sample from @IanCutress. Mon Nov 28 2022 Todd Allen * Added uarch decoding for (0,6),(12,15) Emerald Rapids, from LX*. Mon Nov 28 2022 Todd Allen * Added synth & uarch decoding for (10,15),(10,1) Bergamo. Mon Nov 28 2022 Todd Allen * Added 0x8000000a/edx bits: ROGPT, VNMI, IBS virtualization. * Added 0x8000001b/eax bit: IBS L3 miss filtering support. * Added 0x8000001f/eax bits: RMPQUERY instruction support, VMPL supervisor shadow stack support, VMGEXIT parameter support, virtual TOM MSR support, IBS virtual support for SEV-ES guests, SMT protection support, SVSM communication page MSR support, VIRT_RMPUPDATE & VIRT_PSMASH MSR support. * Added 0x80000020/0/ecx bit: L3 range reservation support. * Added 0x80000021/eax bits: automatic IBRS, CPUID disable for non-privileged. * Added 0x80000022/eax bit: AMD LBR & PMC freezing. * Added 0x80000022/ebx field: number of LBR stack entries. * Added 0x80000023 leaf: Multi-Key Encrypted Memory Capabilities. * Added 0x80000026 leaf: AMD Extended CPU Topology. Fri Nov 11 2022 Mateusz Guzik * cpuid.c: FreeBSD patch to use lseek64 and cpuset_setaffinity. Tue Oct 11 2022 Todd Allen * cpuid.c: Added 0x80000022/eax AMD LBR V2 flag, from LX*. * cpuid.c: Note that (8,15),(10,0) Mendocino now is documented. Mon Oct 3 2022 Todd Allen * Made new release. Mon Oct 3 2022 Todd Allen * cpuid.c: Added synth decoding for AMD Ryzen (Phoenix E0), based on sample from bakerlab.org. * cpuid.c: Added synth decoding for AMD Ryzen (Storm Peak A1), based on sample from einstein11.aei.uni-hannover.de. * cpuid.c: Added synth & uarch synth decoding for (0,6),(11,5) Intel Meteor Lake, based on MSR_CPUID_table*. * cpuid.c: Added synth & uarch synth decoding for (0,6),(11,6) Intel Grand Ridge (Crestmont), based on MSR_CPUID_table*. * cpuid.c: Added synth & uarch synth decoding for (0,6),(11,14) Intel Granite Rapids, based on MSR_CPUID_table*. * cpuid.c: Confirmed several other existing synth & uarch decodings based on MSR_CPUID_table*, and updated comments (no functional changes). * cpuid.c: Renamed 7/0/eax enh hardware feedback to simply Thread Director. Evidently, Intel just calls it that now too. * cpuid.c: Added 7/1/eax RAO-INT instructions, CMPccXADD instructions, ArchPerfmonExt is valid, WRMSRNS instructions, AMX-FP16, AVX-IFMA, RDMSRLIST & WRMSRLIST. * cpuid.c: Added 7/1/edx AVX-VNNI-INT8, AVX-NE-CONVERT, PREFETCHIT* instructions. * cpuid.c: Added 0x12/0/eax SGX ENCLU EDECCSA flag. * cpuid.c: Added 0x23 Architecture Performance Monitoring Extended leaf decoding. * cpuid.c: Corrected AVX512IFMA description: integer FMA, not just FMA. Tue Sep 27 2022 Todd Allen * Made new release. Tue Sep 27 2022 Todd Allen * cpuid.c: Added synth decoding for (10,15),(6,1) Raphael, based on instlatx64 samples. Wed Aug 17 2022 Todd Allen * cpuid.c: Fixed missing return statement in get_nr_cpu_ids()'s default case, used by Cygwin. Thanks to Brian Inglis for reporting this. Tue Aug 16 2022 Umio-Yasuno * cpuid.c: Fixed title for AMD 0x8000001a leaf: Performance Optimization Identifiers. Fri Aug 12 2022 Todd Allen * Made new release. Fri Aug 12 2022 Todd Allen * cpuid.c: Corrected (synth) decoding for (0,6),(8,6) Intel Snow Ridge/Parker Ridge. It had been lumped in with Elkhart Lake, but only because that had been the only known core name for the Tremont uarch. These appear to be different cores. Also added steppings from SSG*. Fri Aug 5 2022 Todd Allen * cpuid.c: Added 8000000a/edx X2AVIC flag, from Linux kernel patches It appears to be undocumented, so far. Thu Aug 4 2022 Todd Allen * cpuid.c: Improved (synth) decoding for (0,6),(9,7),2, adding Added Alder Lake-HX. Wed Jul 27 2022 Todd Allen * cpuid.c: Reverted May 27 2022 split of 7/0/ebx hack to report bit 22 as RDPID on AMD architectures. The AMD documentation is inconsistent on the location of this flag. In E.3.6, it claims 7/0/ebx. But in section 3, the RDPID instruction itself claims 7/0/ecx, as does the mention in Table 3-1. This also is consistent with Intel architectures. Thanks to Stefan Kanthak for pointing this out. Mon Jul 25 2022 Todd Allen * cpuid.c: Generalized (0,6),(8,14),9,YP stepping case to include Pentium 4425Y, from instlatx64 sample. Thu Jul 14 2022 Todd Allen * cpuid.c: Updated 7/0/edx comments to reflect original info source for SRBDS mitigation MSR available, previously just marked LX*. * cpuid.c: Updated 7/0/edx comments to reflect original info source for RTM transaction always aborts, previously just marked LX*. * cpuid.c: Added (vuln to branch type confusion synth) synthetic leaf to correct for the one known inaccuracy. * cpuid.man: Added those two original source web pages from Intel: Intel Transactional Synchronization Extensions (Intel TSX) Memory and Performance Monitoring Update for Intel Processors (Article ID 000059422), Special Register Buffer Data Sampling. Wed Jul 13 2022 Todd Allen * cpuid.c: Added 0x80000008/ebx not vulnerable to branch type confusion flag from "Technical Guidance For Mitigating Branch Type Confusion (White Paper)". Also added a synthetic flag to correct the special case for Family 0x19, where the raw flag is documented to be wrong. * cpuid.c: Added 7/2/edx indirect branch prediction related flags from Intel's "Branch History Injection and Intra-mode Branch Target Injection / CVE-2022-0001, CVE-2022-0002 / INTEL-SA-00598". * cpuid.c: Added (uarch synth) decoding for (0,6),(6,14) Cougar Mountain, mentioned as Airmont by Intel's "Retpoline: A Branch Target Injection Mitigation". * cpuid.man: Added "Branch History Injection and Intra-mode Branch Target Injection / CVE-2022-0001, CVE-2022-0002 / INTEL-SA-00598" and "Retpoline: A Branch Target Injection Mitigation". Tue Jul 12 2022 Todd Allen * cpuid.c: Clarified (synth) for (0,6),(8,13) Tiger Lake-H from SSG*. Tue Jul 12 2022 Todd Allen * cpuid.c: Added support for hypervisor+3/ecx (Microsoft) flags. * cpuid.c: Added support for hypervisor+0xa/eax (Microsoft) VMCS GuestIa32DebugCtl support flag. * cpuid.c: Added support for hypervisor+0xa/ebx (Microsoft) VMCS HvFlushGuestPhysicalAddress* flag. Wed Jun 29 2022 Todd Allen * cpuid.c: Added (synth) for (0,6),(11,10),3 Raptor Lake-P Q0, from Coreboot*. Sat Jun 25 2022 Todd Allen * cpuid.c: Lionel Debroux's patch used MAX_CPUS all the time. But it really was meaningful only for the USE_KERNEL_SCHED_SETAFFINITY case (although, by happenstance, it may have been correct for all three cases). Replace this with an nr_cpu_ids global, determined by get_nr_cpu_ids(). The simplest version just returns sysconf(_SC_NPROCESSORS_CONF), although that could be problematic on systems with non-contiguous CPU numbers. * cpuid.c: For USE_KERNEL_SCHED_SETAFFINITY, improve this, and also support systems with > 1024 CPUs, by estimating nr_cpu_ids using a power-of-2 walk through successively larger cpu_set_t sizes until sched_getaffinity succeeds. * cpuid.c: For systems using cpu_set_t (only Cygwin?), cap the nr_cpu_ids to CPU_SETSIZE. * cpuid.c: The _SC_NPROCESSORS_CONF check in real_setup() is removed because it's redundant now. Wed Jun 22 2022 Lionel Debroux * cpuid.c: In do_real() and do_real_one(), avoid breaking out of loop because of downed CPUs. Mon Jun 20 2022 Todd Allen * Made new release. Sat Jun 18 2022 Todd Allen * cpuid.c: Added (synth) for (0,6),(9,7),1 Alder Lake-S B0 from Coreboot*. * cpuid.c: Added (synth) stepping name for (0,6),(9,7),4 Alder Lake-U G0 from Coreboot* (although this dubiously mixes partly contradictory info from two sources). * cpuid.c: Added (synth) stepping name for (0,6),(9,7),5 Alder Lake-S H0 from Coreboot*. * cpuid.c: Added hypervisor+4/eax (Xen) upcalls with physical IRQ vectors from Xen*. * cpuid.c: Added hypervisor+{0x80,0x81,0x82} (Microsoft) synthetic debugging leaves. * cpuid.c: Eliminated print_header(), and distributed those headers throughout print_reg(), frequently using the try (subleaf) number to ensure they are printed only once. Many headers already were like this, and it makes them more consistent. Sun Jun 12 2022 Todd Allen * cpuid.c: Changed (synth) for Alder Lake-S to remove K/KF suffixes, because other suffixes (or no suffix) are available too. * cpuid.c: Added (synth) for (0,6),(9,7),5 Alder Lake-S. * cpuid.c: Added (synth) for (0,6),(9,7),3 Alder Lake-P/H. * cpuid.c: Added (synth) for (0,6),(9,7),4 Alder Lake-U. Sat Jun 11 2022 Todd Allen * cpuid.c: Added 0xf/1/eax QoS monitoring counter size, both in raw form (-24 notation) and as a synthetic leaf the determines the value from the raw form and family/model information. * cpuid.c: Added stash information to print_header() to avoid printing Xen-only headers for hypervisor+3 leaves of other hypervisors. * cpuid.c: Rewrote the handling of subleaves (tries) for legacy raw input files. Originally, I thought I only needed this support for those leaves which existed during that legacy period. But the testbeds lean on that support for samples from instlatx64. So now it's more general. * cpuid.c: For leaf 0x80000020, rewrote the rules for subleaf processing based on the description in AMD64 Technology Platform Quality of Service Extensions (pub 56375 1.03): walk the bits in the mask. * cpuid.c: Added 0x80000020/0/ebx bits 2 & 3, and renamed bit 1. * cpuid.c: Added 0x80000020/1 subleaf header. * cpuid.c: Added 0x80000020/2 subleaf. * cpuid.c: Added 0x80000020/3 subleaf. * cpuid.man: Added 56375: AMD64 Technology Platform Quality of Service Extensions Fri May 27 2022 Todd Allen * cpuid.c: Added 0x8000001f/eax virtual TSC_AUX supported, from Linux kernel. * cpuid.c: Split 7/0/ebx decoding into Intel-specific & AMD-specific versions (using ugly macro to avoid code duplication), differing by bit 22: PCOMMIT (intel) vs. RDPID/TSC_AUX (amd). Wed May 25 2022 Todd Allen * cpuid.c: Added 0x80000022/eax AMD perfmon V2, from Linux kernel. Tue May 24 2022 Todd Allen * cpuid.c: Added 0x21 TDX guest leaf, as ASCII text (e.g. "IntelTDX "). Sat May 21 2022 Todd Allen * cpuid.c: Changed (synth) for AMD (10,15),(5,*) Cezanne to also mention Barcelo, because instlatx64 samples show that they seem to be indistinguishable from cpuid information. Tue May 17 2022 Todd Allen * cpuid.c: Added synth decoding for stepping (0,6),(11,10),2 Raptor Lake-P J0 from Coreboot*. Tue May 3 2022 Todd Allen * cpuid.man: Added 344425, "Architecture Specification: Intel Trust Domain Extensions (Intel TDX) Module". * cpuid.c: Removed 7/0/ecx bus lock detection LX*, Qemu* comment, because it now is documented in the above. * cpuid.man: Added 343754, "Intel Trust Domain CPU Architectural Extensions". * cpuid.c: Added 0x12/0/eax bit 7: EVERIFYREPORT2 support, from the above. Tue May 3 2022 Stefan Kanthak * cpuid.c: Corrected spelling of 7/0/ecx "RDPID: read processor ID supported". Mon May 2 2022 Todd Allen * cpuid.c: Clarified (synth) decoding for (10,15),(11,14) Alder Lake-N, based on LX*. Also added A0 stepping. * cpuid.c: Added defined() checks around uses of __GNUC__, __GNUC_MINOR__, and __GNUC_PATCHLEVEL__, as suggested by Stefan Kanthak. * Makefile: Added -Wundef to compilation options to check the above, although they always are defined with gcc. * cpuid.c: To simplify the new #if's for __builtin_clzl, added new USE_BUILTIN_CLZL macro. Sat Apr 30 2022 Todd Allen * cpuid.c: Added (synth) decoding for (10,15),(0,1),2 Milan B2 stepping. Tue Apr 5 2022 Todd Allen * cpuid.c: Changed (0,6),(9,10) Alder Lake synth decoding stepping names, based on Coreboot*, evidently from Intel doc 626774. I cannot find that document. Perhaps it is under NDA. * cpuid.c: Added (0,6),(1,9) ZhangJiang synth & uarch decoding from Google_cpu_features*. * cpuid.c: Added (0,7),(1,11) WuDaoKou synth & uarch decoding from Google_cpu_features*. Also corrected (0,7),(0,11) uarch decoding. * cpuid.c: Added (0,7),(3,11) LuJiaZui uarch decoding from Google_cpu_features*. Also simplified its synth decoding. * cpuid.c: Added (0,7),(5,11) YongFeng synth & uarch decoding from Google_cpu_features*. Still somewhat speculative. Fri Mar 25 2022 Todd Allen * cpuid.c: Added hypervisor+4/eax (Microsoft) bits 15, 17, 18. * cpuid.c: Added hypervisor+4/ecx (Microsoft) leaf. * cpuid.c: Added many hypervisor+6/eax (Microsoft) fields. * cpuid.c: Added hypervisor+0xa/eax (Microsoft) bit 22. * cpuid.c: Added hypervisor+3/ebx (Microsoft) Isolation flag, from Linux kernel (arch/x86/include/asm/hyperv-tlfs.h). * cpuid.c: Added hypervisor+0xc/{eax,ebx} (Microsoft) leaves, from Linux kernel (arch/x86/include/asm/hyperv-tlfs.h). Fri Mar 18 2022 Todd Allen * cpuid.c: Corrected (synth) for (0,6),(9,10) Alder Lake to report Core where appropriate, instead of Atom always. In fact, I've seen zero instances of Atoms with this core, so perhaps this was an early misunderstanding. The (0,6),(9,7) Alder Lake-S core was added at the same time, also as an Atom, but was corrected much earlier. So I've made the same correction here. Sat Mar 12 2022 Todd Allen * cpuid.c: Added (synth) decoding for (8,15),(9,0),2 Van Gogh A2 from instlatx64 sample. Thu Mar 10 2022 Todd Allen * cpuid.c: Added (synth) decoding for (0,6),(10,10),{0-1} A0 steppings, based on info from Coreboot*. Thu Feb 24 2022 Todd Allen * Made new release. Wed Feb 23 2022 Todd Allen * cpuid.c: Added (synth) and (uarch synth) decoding for AMD Rembrandt E1. Sat Feb 19 2022 Todd Allen * cpuid.c: Added hypervisor+4/eax (Xen) expanded destination id bit. Mon Jan 17 2022 Todd Allen * cpuid.c: Removed bogus 7/1/eax bit 24 "AMX tile support". The only claim for that was an inaccurate comment in the linux kernel, added 2-Nov-2021, but the actual bit is in 7/0/edx, which already was present in cpuid. Sun Jan 9 2022 Todd Allen * cpuid.c: Renamed 6/eax bit to 23 to mention Thread Director. * cpuid.c: Widened 6/ecx number of enh hardware feedback classes from bits 8-11 to bits 8-15. * cpuid.c: Renamed 7/1/eax bit to 10 to include "fast". * cpuid.c: Added 7/1/ebx decoding. * cpuid.c: Added 0x14/0/ebx decoding for support for IA32_RTIT_CTL EventEn & DisTNT bits. * cpuid.c: Added synth decoding for (0,6),(11,15) Alder Lake, based on MSR_CPUID_table*. * cpuid.c: Confirmed synth decoding for (0,6),(10,8) Rocket Lake. Tue Jan 4 2022 Todd Allen * cpuid.c: Added (synth) steppings based on instlatx64 samples: 1,(0,5),(0,3),2 P24T C0, (0,6),(0,2),2 K75/Pluto/Orion A2, (0,6),(4,6),1 Crystal Well C1, (0,6),(7,14),5 Ice Lake-U/Y D1, (0,6),(9,7),2 Alder Lake-S C0, (0,6),(10,7),1 Rocket Lake B0. * cpuid.c: Corrected missing Core name for (0,6),(9,7) Alder Lake-S A0 stepping. Mon Dec 13 2021 Todd Allen * cpuid.c: In 0x18 leaves, line up values better. Fri Dec 10 2021 Todd Allen * Made new release. Fri Dec 10 2021 Todd Allen * cpuid.c: Reorganized loop over 0x12 subleaves in do_real(). The old code assumed validity was at least partially determined by a bitmask in subleaf 0 (like for leaf 0x10), but that was wrong. Thanks to Scott Raynor for pointing this out. * cpuid.c: Added code for 0x12/(n>=2) subleaves to show invalid cases as such, instead of resorting to a raw dump. * cpuid.c: Fixed missing loop over 0x1b subleaves in do_real(). This might become necessary if more target identifiers are added. * cpuid.c: Added print_1b_n_target() to decode the MKTME target identifier. * cpuid.c: Modified leaf 4 subleaf loop to include the terminating "no more caches" subleaf. Modified print_reg() to abbreviate "no more caches" subleaves. * cpuid.c: Cleaned up loops for leaves 7, 0x14, 0x17, 0x18, 0x1d, 0x20 subleaves: max_tries (from subleaf 0) is available before the loop starts. * cpuid.c: Modified leaf 0xb subleaf loop to exit for the right reason, level type == 0. Also, it includes the terminating "invalid" subleaf. The similiar 0x1f leaf already did this. Mon Nov 29 2021 Todd Allen * Made new release. Fri Nov 26 2021 Todd Allen * From AMD Programmer's Manual, Vol 3, Rev 3.33, Appendix E: * cpuid.c: Added 0x80000008/ebx CPU prefers: IBRS always on. * cpuid.c: Renamed 0x80000008/ebx CPU prefers: STIBP always on. * cpuid.c: Renamed 0x80000008/ebx INVLPGB supports TLB flush guest nested. * cpuid.c: Added 0x8000001f/eax Secure TSC supported. * cpuid.c: Added 0x8000001f/eax VMSA register protection. * cpuid.c: Added 0x80000021/eax upper address ignore support. * cpuid.c: Added 0x80000021/eax SMM_CTL MSR not supported * cpuid.c: Added 0x80000021/ebx. * cpuid.c: Added 0x80000022/ebx. Mon Nov 22 2021 Todd Allen * cpuid.c: Correct (uarch synth) phys for Cascade Lake to 14nm++. * cpuid.c: Correct (uarch synth) phys for Cooper Lake to 14nm++. Sun Nov 21 2021 Todd Allen * Made new release. Sun Nov 21 2021 Todd Allen * cpuid.c: Removed __LARGE64_FILES from __CYGWIN__, per Brian Inglis' request. * cpuid.c: Renamed macros with names starting with underscores, which are resered names in C: __THING -> MaskTHING, _THING -> ShftTHING. Brian Inglis says this was an actual practical problem in Cygwin. This change makes the code less dense, but a bit easier to understand. Sat Nov 20 2021 Todd Allen * cpuid.c: Distinguish (synth) decoding: AMD (8,15),(2,0) Dali CPUs: Ryzen vs. other. * cpuid.c: Added to (synth) decoding: AMD Ryzen 1000/2000/3000/4000/5000 series numbers. * cpuid.c: Added to (synth) decoding: AMD Epyc Gen numbers. * cpuid.c: Distinguish (synth) decodings for Threadripper CPUs. For Zen & Zen+, only the brand distinguishes; for Zen 2 (and rumored for Zen 3), there are distinct models. * cpuid.c: Distinguish (synth) decoding between Great Horned Owl & Banded Kestrel. * cpuid.c: Distinguish (synth) decoding for Grey Hawk from Renoir. Thu Nov 18 2021 Todd Allen * cpuid.c: Added (synth) & (uarch synth) decoding for (0,6),(11,14) Golden Cove (Alder Lake) from Coreboot*. * cpuid.c: Added (synth) & (uarch synth) decoding for (0,6),(6,7) Palm Cove (Cannon Lake) from DPTF*. * cpuid.c: Added (synth) & (uarch synth) decoding for (0,6),(10,11) Redwood Cove (Meteor Lake-N) from DPTF*. * cpuid.c: Added (synth) & (uarch synth) decoding for (0,6),(11,10) Raptor Cove (Raptor Lake-P) from DPTF*. Mon Nov 15 2021 Todd Allen * cpuid.c: Added (synth) decoding for (0,6),(11,7) Raptor Lake, from LX*. * cpuid.c: Updated (uarch synth) phys strings for Intel 14nm and 10nm process nodes using 14nm+, 14nm++, 14nm+++, 10nm+, 10nm++. Sun Nov 14 2021 Todd Allen * Made new release. Mon Nov 8 2021 Todd Allen * cpuid.c: Updated (uarch synth) for Bergamo to say "Zen 4c". Fri Nov 5 2021 Todd Allen * cpuid.c: Added (synth) decoding for Pentium Gold G5420 (0,6),(9,14),10, based on a sample from Andrey Rahmatullin. Previously, I knew only of variants with stepping 11. * cpuid.c: Renamed Golden Cove & derivatives phys (physical properties) to use new Intel 7 branding. Likewise for the preliminary Redwood Cove & Granite Rapids and Intel 4. Thu Nov 4 2021 Todd Allen * cpuid.c: Added (synth) decoding for AMD Storm Peak (preliminary). * cpuid.c: Added (synth) decoding for Intel (0,6),(10,8) (preliminary). * cpuid.c: Added (synth) decoding for Intel (0,6),(10,10) (preliminary). * cpuid.c: Added (synth) decoding for Intel (0,6),(10,12) (preliminary). * cpuid.c: Added (synth) decoding for Intel (0,6),(10,13) (preliminary). * cpuid.c: Added (synth) decoding for Intel (0,6),(9,15) (preliminary). * cpuid.c: Added Cougar Mountain name to Intel Puma 7, from MRG 2018-Mar-6. Wed Nov 3 2021 Todd Allen * cpuid.c: Added (synth) decoding for AMD Lucienne A1 stepping. * cpuid.c: Added (synth) decoding for AMD Van Gogh (preliminary). * cpuid.c: Added (synth) decoding for AMD Mero (preliminary). * cpuid.c: Added (synth) decoding for AMD Mendocino (preliminary). * cpuid.c: Added (synth) decoding for AMD Chagall (preliminary). * cpuid.c: Added (synth) decoding for AMD Badami (preliminary). * cpuid.c: Added (synth) decoding for AMD Rembrandt (preliminary). * cpuid.c: Added (synth) decoding for AMD Genoa (preliminary). * cpuid.c: Added (synth) decoding for AMD Raphael (preliminary). * cpuid.c: Added (synth) decoding for AMD Phoenix (preliminary). * cpuid.c: Added (synth) decoding for AMD Bergamo (preliminary). Wed Nov 3 2021 Todd Allen * cpuid.c: Added hypervisor+3/edx (Microsoft) new fields. * cpuid.c: Added hypervisor+7/eax (Microsoft) new field. * cpuid.c: Added hypervisor+7/ecx (Microsoft) new field. * cpuid.c: Added hypervisor+0xa/eax (Microsoft) new field. Wed Nov 3 2021 Todd Allen * cpuid.c: Updated (synth) decoding for Alder Lake-S to include Core variants. * cpuid.c: Added (synth) and (uarch) decoding for VIA/Centaur CHA (CNS). Tue Nov 2 2021 Todd Allen * cpuid.c: Added 7/1/eax AMX tile support, from Linux kernel. Sun Oct 31 2021 Todd Allen * Made new release. Sun Oct 31 2021 Todd Allen * cpuid.c: Support hypervisors which can move their range of leaves to other base addresses, to support hypervisors under other hypervisors: IS_HYPERVISOR_LEAF(), print_hypervisor_*(). * cpuid.c: Separated out get_hypervisor(). This ended up being unnecessary, but I prefer it anyway. * cpuid.c: Added print_esc_substring() to print hypervisor_id values that contain non-graphic characters. Fri Oct 29 2021 Todd Allen * cpuid.c: Improved (synth) decoding for Intel Xeon (3rd Gen) D2/M1 steppings. Wed Oct 27 2021 Todd Allen * cpuid.c: Added 0x40000001/eax support for ACRN hypervisor. Untested. * cpuid.c: Added better decoding of 0x12/1 SECS.ATTRIBUTES fields. Tue Oct 26 2021 Todd Allen * cpuid.c: Added 5,3 model for Cyrix M1 6x86, based on Cyrix 6x86 Processor, Instruction Set document (M1-6). * cpuid.c: Corrected wrong register passed to print_40000009_edx_microsoft(). Mon Oct 25 2021 Todd Allen * cpuid.c: Adapted patch from Brian Inglis for easier Cygwin cygport, but made an effort to reduce duplicate header file references, and use of for the right reasons (i.e. a more general change). * cpuid.c: For 12/n/ebx & 12/n/edx (n >= 2), mask the high 12 bits. * cpuid.c: Added 0x40000001/eax(KVM) map gpa range hypercall & MSR_KVM_MIGRATION_CONTROL. Sun Oct 24 2021 Todd Allen * cpuid.c: Add (synth) decoding for additional Alder Lake steppings. * cpuid.c: Generalize (synth) decoding for Elkhart Lake B0. * cpuid.c: Added 0x8000000a/edx guest SVME addr check. * cpuid.c: Added 7/0/ecx bus lock detection. * cpuid.c: Added 7/0/edx RTM transaction always aborts, TSX_FORCE_ABORT. * cpuid.c: Added 0x40000001/eax (KVM) extended destination ID. * cpuid.c: Added (synth) decoding for Vortex86EX2 & Vortex86DX2. Info on these is almost nonexistent, so it's possible that these rules are too specific or too vague. * cpuid.c: Improved (synth) decoding for Tiger Lake: Pentium & Celeron. * cpuid.c: Improved (synth) decoding for Elkhart Lake: Pentium & Celeron. * cpuid.c: Improved (synth) decoding for Jasper Lake: Pentium & Celeron. * cpuid.c: Improved (synth) decoding for (0,6)(10,5) Comet Lake: Pentium, Celeron & Xeon. * cpuid.c: Improved (synth) decoding for (0,6),(6,10) Ice Lake: Xeon Scalable. * cpuid.c: Improved (synth) decoding for AMD (8,15),(1,1) Raven Ridge: Athlon Pro 200. * cpuid.c: Improved (synth) decoding for AMD (8,15),(1,8) Picasso: Athlon Pro 300. * cpuid.c: Added (synth) decoding for AMD 4700S Desktop Kit. * cpuid.c: Added (synth) decoding for AMD (8,15),(4,7) Lucienne. Sun Oct 24 2021 Todd Allen * cpuid.c: Added 0x80000008/ecx tscSize. * cpuid.c: Added 0x8000001c/{eax,edx} continuous mode sampling. * cpuid.c: Added 0x8000001c/{eax,edx] tsc in event record. * cpuid.c: Added (synth) decoding for AMD Milan B1. * cpuid.c: Added (synth) decoding for AMD Vermeer. * cpuid.c: Added (synth) decoding for AMD Cezanne. Sat Oct 23 2021 Todd Allen * cpuid.c: Renamed 7/0/ecx 5-level paging to include LA57 & 57-bit addrs. * cpuid.c: Improved 0xa/ebx presentation, and automatically mask bits marked as invalid by 0xa/eax vector length. * cpuid.c: Added 0x12/n/ecx new section property encoding. * cpuid.c: Renamed Rocket Lake uarch to Cypress Cove. * cpuid.c: Improved (synth) decoding for Tiger Lake. * cpuid.c: Improved (synth) decoding for Rocket Lake. Fri Jul 16 2021 Ani Sinha * cpuid.c: Add support for 0x40000003/eax reenlightenment control MSR & 0x40000003/eax TscInvariant control MSR [on Microsoft Hyper-V]. Fri Jul 16 2021 Smita Koralahalli Channabasappa * cpuid.c: restoring the deleted "AMD (unknown model)" entry. Mon Jul 12 2021 Smita Koralahalli Channabasappa * cpuid.c: updates the existing leaf and subleaf in the CPUID with features related to INVLPGB, CPPC, PSFD, SEV [affects 0x80000008/edx, 0x80000008/edx, and 0x8000001f/eax]. * cpuid.c: defines new leaf 80000021/eax. * cpuid.c: replaces the naming "Unknown Model" -> "AMD EPYC Milan" for Family 19h and Model 01h [affects (synth) decoding]. Tue Feb 2 2021 Jonathan Teh * From http://datasheets.chipdb.org/Cyrix/112ap.pdf (page 7, table 1): * cpuid.c: Cyrix family 4 model 4 should be MediaGX or GXi * cpuid.c: GXm is family 5, model 4 * cpuid.c: Cyrix MediaGX is derived from the 5x86 and unrelated to the WinChip C6. Based on Wikipedia, the MediaGXm was renamed the Geode GXm after it was sold to National Semi but the CPUs appear to have continued to be sold under the Cyrix vendor up to and including the Geode GX1. Hence, I've simply duplicated the names from NSC model 4 into Cyrix. * cpuid.c: Model 9 for the WinChip 3 is moved to the Centaur section [decode_synth_via()], from the datasheet page 3-11: http://datasheets.chipdb.org/IDT/x86/WinChip3/winchip_3_datasheet.pdf * cpuid.c: The Cyrix CPU detection guide [112ap] also offers some possible codenames from page 20, table 17 Cx486SLC/DLC/SRx/DRx (M0.5) up to table 26 for the GXm. Mon Jan 4 2021 Todd Allen * cpuid.c: Corrected decode_amd_model()'s (0,15),(4,0) decodings for bti values 0x29, 0x2a, and 0x2b. * cpuid.c: Corrected wrong register passed to print_40000001_edx_kvm(). Mon Nov 2 2020 Brian Inglis * Makefile: Set BUILDROOT=$(DESTDIR) for easier Cygwin cygport support. Mon Oct 12 2020 Todd Allen * cpuid.c: Added (synth) decoding for (6,15),(3,0) AMD R-Series Bald Eagle based on instlatx64 sample. * cpuid.c: Added rudimentary synth & uarch decoding for Montage Jintide Gen1, a CPU based on Intel Skylake (0,6),(5,5), and detectable by brand string. * cpuid.c: Fixed append_uarch() to pass stash, which improves uarch [suffix] for Montage, Zhaoxin, and ZhangJiang CPUs. Tue Oct 6 2020 Todd Allen * Made new release. Tue Oct 6 2020 Todd Allen * cpuid.c: Added 6/eax enhanced hardware feedback interface. * cpuid.c: Added 6/ecx number of enh hardware feedback classes. * cpuid.c: Added 7/0/ecx KL: key locker. * cpuid.c: Added 7/0/edx UINTR: user interrupts. * cpuid.c: Added 7/0/edx AVX512_FP16: fp16 support. * cpuid.c: Added 7/1/eax AVX-VNNI: AVX VNNI neural network instrs. * cpuid.c: Added 7/1/eax zero-length MOVSB. * cpuid.c: Added 7/1/eax fast short STOSB. * cpuid.c: Added 7/1/eax fast short CMPSB, SCASB. * cpuid.c: Added 7/1/eax HRESET: history reset support. * cpuid.c: Added 0xa/ecx fixed counter support enumeration. * cpuid.c: Added 0xd/0/eax IA32_XSS UINTR state. * cpuid.c: Added 0xd/n UINTR feature. * cpuid.c: Added 0x19 key locker features. * cpuid.c: Added 0x20 HRESET features. Mon Oct 5 2020 Todd Allen * cpuid.c: Added (7,5),(2,6) AMD Cato (synth) decoding based on instlatx64 example (possibly an engr sample). Sun Oct 4 2020 Todd Allen * cpuid.c: Corrected 6/edx size field to use minus-one notation. * cpuid.c: Added 7/0/edx AMX flags. * cpuid.c: Added 0xd XTILECFG & XTILEDATA features. * cpuid.c: Added 0xd/1/eax XFD: extended feature disable supported flag. * cpuid.c: Added 0xd/n/ecx XFD: faulting supported flag. * cpuid.c: Added 0x18/0/edx: load-only TLB & store-only TLB encodings. * cpuid.c: Added 0x1d leaf (Tile info) decoding. * cpuid.c: Added 0x1e leaf (TMUL) decoding. * cpuid.c: Added 0x1c leaf (architectural LBR) decoding. * cpuid.c: Added 0xd LBR features. Sun Oct 4 2020 Todd Allen * cpuid.c: Added (synth) steppings for Comet Lake (0,6),(10,6) CPUs. For the first time in a long time, Intel actually provided this in the revision guide (615213)! * cpuid.c: Corrected (synth) decoding for AMD (8,15),(2,0) Dali CPUs. * cpuid.c: Added (synth) decoding for AMD Dali A1 stepping. * cpuid.c: Added (synth) decoding for AMD Picasso A1 stepping. * cpuid.c: Added (synth) decoding for AMD Renoir A1 stepping. Sat Oct 3 2020 Todd Allen * cpuid.c: Added 7/0/ecx PKS flag. * cpuid.c: Added 7/0/edx SRBDS flag, from Linux kernel. * cpuid.c: Added 7/0/edx LBR flag. * cpuid.c: Added 0xd/0/eax IA322_XSS HWP state flag. * cpuid.c: Added synth decoding for Rocket Lake. * cpuid.c: Added synth decoding for Elkhart Lake B0. * cpuid.c: Added synth decoding for Alder Lake [Golden Cove]. * cpuid.c: Clarified synth decoding for (0,6),(8,10) Lakefield. * cpuid.c: Added KVM interrupt-based page-ready APF event flag. Sat Aug 8 2020 Todd Allen * cpuid.c: Corrected 0x20000001/edx header. * cpuid.c: Detect bogus 0x20000000 leaf values and cap the maximum valid register for the 0x2xxxxxxx range to avoid absurdly long dumps on old CPUs. Mon Aug 3 2020 Todd Allen * cpuid.c: Added bzero before cpuid instruction, in case the cpuid instruction quietly fails. This mostly is paranoia, but I don't see how this ever could cause harm. Mon Jun 8 2020 Todd Allen * cpuid.c: Added Tiger Lake-U B0 stepping, from coreboot. * cpuid.c: Added AMD (8,15),(2,0) Picasso model synth & uarch decoding. Sun May 24 2020 Todd Allen * cpuid.c: Added Zhaoxin KX-6000 decoding that still claims the vendor CentaurHauls. Later Zhaoxin CPUs were supposed to use their own vendor, but instlat64x showed an example that still used the old one. Sat May 16 2020 Todd Allen * cpuid.c: Added better (synth) decoding for Intel Comet Lake-H/S Core i*-10000 CPUs, based on instlatx64 example and listings in ark.intel.com. Tue Apr 28 2020 Todd Allen * cpuid.c: Added 0x8000000a/edx INVLPGB/TLBSYNC hypervisor intercept enable flag. Mon Apr 27 2020 Todd Allen * Made new release. Wed Apr 22 2020 Todd Allen * cpuid.c: Added synth decoding for AMD Steppe Eagle/Crowned Eagle (Puma 2014 G-Series), based on instlatx64 sample. Thu Apr 16 2020 Todd Allen * cpuid.c: Added 7/0/edx SERIALIZE & TSXLDTRK bit descriptions. * cpuid.c: Added 0xf/1/eax Counter width & overflow flag. * cpuid.c: Added 0x10/3/ecx per-thread MBA controls flag. * cpuid.c: Added 0x8000001f fields. * cpuid.man: Added AMD 24594 & 40332 docs. Tue Mar 3 2020 Todd Allen * cpuid.c: Corrected field lengths in 14/0 and 14/1 subleafs so that columns line up. Thu Feb 27 2020 Todd Allen * cpuid.c: Added CC150 (Coffee Lake R0) synth decoding, based on instlatx64 example. Wed Feb 26 2020 Todd Allen * cpuid.c: Added Jasper Lake A0 stepping (from Coreboot*). * cpuid.c: Updated 1/ebx "cpu count" to modern terminology: "maximum addressible IDs for CPUs in pkg" to avoid user confusion. It was a reliable count of the number of CPUs for only a split second some time around 2002. Maybe. * cpuid.c: Updated 4/eax CPU & core count terminology in the same way. Tue Feb 11 2020 Todd Allen * Made new release. Mon Feb 10 2020 Todd Allen * cpuid.c: Clarified Intel NNP-I (Spring Hill). * cpuid.c: In decode_vendor(), report "Zhaoxin" even with VENDOR_VIA, if the brand string indicates so. * cpuid.c: In 0xc0000004/ebx, make current voltage use the shift-4 + 700 encoding used for other VIA voltages. Fri Feb 7 2020 Todd Allen * cpuid.man: Use both Intel doc numbers for 329671/600827. * cpuid.man: Added missing 329901/600834 Intel doc. Thu Feb 6 2020 Todd Allen * cpuid.c: Added VIA 0xc0000004 leaf decoding. * cpuid.c: Added X2_IMAGES special flag to pretty-print values in the 2X encoding. * cpuid.c: Added MINUS1_IMAGES special flag to pretty-print values with the "- 1" encoding. (I finally got turned around about this being better than the older "raw" values.) Wed Feb 5 2020 Todd Allen * cpuid.c: Add VIA C7-D and Eden brands to (0,6),(0,10) (synth). * cpuid.c: Differentiate VIA (0,6),(0,13) (synth) based on brand strings. * cpuid.c: Overhaul of VIA 0xc0000002 leaf decoding. * cpuid.c: Updated VIA Nano steppings (synth). * cpuid.c: Removed extraneous WinChip & core words from C3 and later VIA CPUs (synth). Wed Feb 5 2020 Todd Allen * cpuid.c: Changed mp_synth fields to use '=' separator instead of ':', like every other value. * cpuid.c: Changed processor serial number to use '=' separator instead of ':', like every other value. Tue Feb 4 2020 Todd Allen * cpuid.man: Added 336907 doc with 7/0/ecx/TME bit description. * cpuid.c: Removed LX* comment from 7/0/ecx/TME bit description. It's documented after all. Tue Feb 4 2020 Todd Allen * cpuid.c: Clarified (0,6),(10,6) Comet Lake-U (synth). Mon Feb 3 2020 Todd Allen * Made new release. Mon Feb 3 2020 Todd Allen * cpuid.c: Removed comments about (0,6),(8,14),10 contradiction. Coreboot* removed the incorrect code claiming it was Coffee Lake D0. The actual code already reflected this resolution. * cpuid.c: Removed now-redundant lines from decode_uarch_intel() for the individual (0,6),(8,14) steppings. They all say Kaby Lake now, so they aren't necessary. * cpuid.c: Added (0,6),(4,14),8 Kaby Lake G0 and (0,6),(5,14),8 Kaby Lake-H A0 steppings to both (synth) and (uarch synth) that I found in Coreboot*. I realized I was worrying too much about them. They are at least wholly distinct steppings, so they don't constitute the intra-stepping blurring that I saw with {Kaby,Amber,Whiskey,Comet} Lake. They are more akin to the already-existing Cascade Lake & Cooper Lake steppings. Perhaps those two new entries were just early engineering samples for Kaby Lake. * cpuid.c: Added (0,6),(9,14),13 stepping to decode_uarch_intel. The fallback without a stepping is weak, and it should be avoided for any actual known stepping. (Added a comment too.) * Makefile: Changed my own Todd's Development rules to build on very old systems, so that the executables will run at all on very old systems. * Makefile: Changed -Wextra to -W. That isn't recommended on modern gcc versions, but still works. And it is necessary on really old gcc versions, because -Wextra produces a hard error. Sun Feb 2 2020 Todd Allen * Made new release. Sun Feb 2 2020 Todd Allen * Makefile, cpuid.proto.spec: Added FAMILY.NOTES to the list of files to be included in tarball & rpm doc directory. That file still is messy, but I reference it a lot, so maybe it will be useful to others too. Sun Feb 2 2020 Todd Allen * cpuid.c: Added old (synth) models from sandpile.org: AMD Elan SC400, NSC Geode LX. * cpuid.c: Added some old (synth) and (uarch synth) die process numbers from sandpile.org. * cpuid.c: Added stepping values from sandpile.org. * cpuid.c: sandpile.org calls (0,6),(4,6) "Crystalwell". Arguably, that is just the name of the L4 cache. But even Intel's ARK calls these CPUs "Crystal Well". So I'm changing the name to "Crystal Well". The uarch still is Haswell, so that should clarify any confusion. * cpuid.c: sandpile.org calls (0,6),(4,7) "Brystalwell". The situation is similar, but Intel does not use that name at all. I'm not renaming these cores. Sun Feb 2 2020 Todd Allen * cpuid.c: Added leaf walking of the 0x20000000 (Intel Phi) range and decoding of a single bit in 0x20000001, based on information in sandpile.org. I found only a vague hint about this in the Intel Xeon Phi Coprocessor System Developers Guide, but no details. * cpuid.c: For the (0,11) family of Phi processors, placing them within a K1OM family. The (0,6) Phi cores are just Airmont-derived, so left them alone. Sat Feb 1 2020 Todd Allen * cpuid.c: Reverted Cedar Trail back to Cedarview. (Atom uArch name vs. Core name vs. Platform name vs. SoC name is very confusing.) Sat Feb 1 2020 Todd Allen * cpuid.c: Added Broadwell (0,6),(3,13) steppings based on Coreboot*. * cpuid.c: Added Haswell (0,6),(3,12) steppings based on Coreboot*. * cpuid.c: Added Haswell-ULT (0,6),(4,5),0 stepping based on Coreboot*. * cpuid.c: Added some Skylake (0,6),(4,14) steppings based on Coreboot*. * cpuid.c: Added some Skylake (0,6),(5,14) steppings based on Coreboot*. * cpuid.c: Added Kaby Lake-H (0,6),(9,14),9 stepping based on Coreboot*. * cpuid.c: Added Cannon Lake (0,6),(6,6) steppings based on Coreboot*. * cpuid.c: Added Apollo Lake (0,6),(5,12) A0 stepping based on Coreboot*. * cpuid.c: Added Gemini Lake (0,6),(7,10) A0 stepping, and corrected R0 stepping, based on Coreboot*. * cpuid.c: Added Ice Lake-U/Y (0,6),(7,14) A0 stepping based on Coreboot*, and disregarding inconsistent info from spec update. * cpuid.c: Added Tiger Lake (0,6),(8,12) A0 stepping based on Coreboot*. * cpuid.c: Added Elkhart Lake (0,6),(9,6) A0 stepping based on Coreboot*. * cpuid.c: Added Comet Lake (0,6),(10,6) steppings based on Coreboot*. * cpuid.c: Added Comet Lake-H/S (0,6),(10,5) steppings based on Coreboot*. Sat Feb 1 2020 Todd Allen * cpuid.c: Added (uarch synth) decoding for (6,15),(0,0) Bulldozer, based on engineering sample. * cpuid.c: Added (uarch synth) & (synth) (6,15),(6,0) Excavator Carrizo and Toronto, based on instlatx64 samples. * cpuid.c: Added (uarch synth) decoding for (8,15),(0,0) Zen, based on engineering sample. * cpuid.c: Added Zhaoxin (0,7),(1,15) based on example. * cpuid.c: Differentiate Zhaoxin ZhangJiang from VIA Isaiah [C7] in (synth) and (uarch synth). Sadly, this implies a need to use brand information for (uarch synth). * cpuid.c: Addedd (synth) for VIA version of Zhaoxin ZhangJaing at (0,7),(0,11). * cpuid.c: Added Westmere-EP A0 & B0 stepping (synth) based on instlatx64 sample & wikipedia article. * cpuid.c: Fixed bogus stepping in Centerton fallback (synth). * cpuid.c: Added (0,6),(5,5),10 Cooper Lake (synth) & (uarch synth), based on Qemu. * cpuid.c: Added "AMD PRO A" as a 2nd string to detect AMD A-Series. * cpuid.c: Differentiate Raven Ridge from Great Horned Owl/ Banded Kestrel (synth), based on "Embedded" string in brand. * cpuid.c: Added Merlin Falcon as R-Series alternative everywhere G-Series Brown Falcon appears. * cpuid.c: Added rules for EPYC Embedded to differentiate (synth) for Snowy Owl and Naples, based on EPYC 3000 series. Untested, because I have no examples. Fri Jan 31 2020 Todd Allen * cpuid.man: Added instlatx64.atw.hu. * cpuid.man: Added -l and -s options. Fri Jan 31 2020 Todd Allen * cpuid.c: Added rudimentary (10,15) (synth) for AMD Zen 3. Fri Jan 31 2020 Todd Allen * cpuid.man: Added linux kernel note about intel-family.h. * cpuid.c: Added rudimentary Tremont (synth) & (uarch synth). * cpuid.c: Added tentative Ice Lake NNPI (synth) & (uarch synth). * cpuid.c: Added rudimentary (0,6),(10,6) Comet Lake [Coffee Lake] (synth) & (uarch synth). Fri Jan 31 2020 Todd Allen * cpuid.man: Added Intel Microcode Update Guidance document. * cpuid.c: Removed br.generic check from dc (Core) query. It was useful in the Yonah era, but has been problematic since. Instead, add a dG (Generic) query and use that where needed for the Yonah CPUs. And a few other users of dc now use dG. * cpuid.c: Added (synth) for Apollo Lake D0 (collision with B0/B1?) & E0. * cpuid.c: Generalized P4500 & U4500 (Arrandale/Clarkdale) (synth) names. * cpuid.c: Added Broadwell-DE V3 (synth) alternate stepping. * cpuid.c: Added Broadwell H 43e (synth). * cpuid.c: Added Pentium 3700U / 3800U (synth). * cpuid.c: Added Apollo Lake (Broxton) (synth). * cpuid.c: Added Atom x5-E8000 (synth). * cpuid.c: Added Pentium G6900 (Clarkdale K0) (synth). * cpuid.c: Added Core i*-900 (Clarksfield) (query dc) (synth). * cpuid.c: Added E5-4600 (Ivy Bridge) (synth) names. * cpuid.c: Prefixed E to Jasper Forest Xeon (synth) names. * cpuid.c: Added Xeon E3-1200 (Kaby Lake) (synth) specific line. * cpuid.c: Added Xeon 6500 names to Beckon (synth). * cpuid.c: Generalized Pentium 900 (Sandy Bridge) (synth) names. * cpuid.c: Added Celeron T3000 / 900 / SU2300 (Wolfdale) (synth) names. * cpuid.c: Added Pentium T4000 (Wolfdale) (synth) names. * cpuid.c: Added Celeron M ULV 700 (Penryn) (synth). * cpuid.c: Correct query to dc for Sandy Bridge-E Core (synth). * cpuid.c: Added Pentium 1405 (Sandy Bridge-E) (synth). * cpuid.c: Added Xeon D-2100 (Skylake stepping 4) (synth) names. * cpuid.c: Added Core i9-7000X (Skylake-X) (synth). * cpuid.c: Changed case of x for SoFIA (synth). * cpuid.c: Simplified Westmere-EP Xeon (synth) names. * cpuid.c: Added Atom x*-A3900 (Apollo Lake) (synth) names. * cpuid.c: Added Rangeley core name to Atom C2000 (synth) names. * cpuid.c: Clarified that all (0,6),(4,15) CPUs are Broadwell-{E,EX} in (synth) lines. * cpuid.c: Clarified that (0,6),(3,13) is Broadwell-U. * cpuid.c: For (0,6),(4,6) (synth), MRG* 2018-08-31 shows stepping 1, so that must be the only known stepping: G0. * cpuid.c: Corrected Broadwell-Y Core M (synth). * cpuid.c: Added (0,6),(9,14),11 Coffee Lake Pentium & Celeron (synth). * cpuid.c: Corrected (0,6),(9,14),11 fallback (synth). * cpuid.c: Clarified transition from i*-8000 to i*-9000 at (0,6),(9,14),12 stepping in (synth) lines. * cpuid.c: Added Puma 7 (synth). * cpuid.c: Generalized Pentium B900C (Ivy Bridge) (synth). * cpuid.c: Added Celeron G2000 (Haswell) (synth). * cpuid.c: Clarified Haswell-E (synth). * cpuid.c: Aded -4000 series to (0,6),(4,6) Core (synth) names. * cpuid.c: Added (0,6),(3,14) Ivy Bridge Celeron (synth). * cpuid.c: Corrected (0,6),(3,14) Cores as Ivy Bridge-E (synth). * cpuid.c: Differentiate i*-8700 and i*-7700 Kaby Lake (synth). * cpuid.c: Added (0,6),(8,14),9 Kaby Lake Pentium & Celeron (synth). * cpuid.c: Differentiate (0,6),(8,14),9 Kaby Lake-Y and Amber Lake-Y (synth) with test for -8000 Series in brand name, because there seems to be no other way to tell. * cpuid.c: Added XMM 7272 (SoFIA) (synth). * cpuid.c: Added Coffee Lake R0 Xeon (synth). * cpuid.c: Added Whiskey Lake W0 Pentium & Celeron (synth). * cpuid.c: Correct (8,14) (uarch synth) to just Kaby Lake once all instances of Coffee lake had been eliminated from that family. The (9,14) family continues to include both Kaby Lake & Coffee Lake. Fri Jan 31 2020 Todd Allen * cpuid.man: Added Intel 600827 spec update. * cpuid.c: Generalized Bay Trail-M/D (synth) names and expanded them. * cpuid.c: Added Bay Trail-M/D D0/D1 (synth). Thu Jan 30 2020 Todd Allen * cpuid.c: Added VIA die processes for as many uarchs/cores as I could find. Wed Jan 29 2020 Todd Allen * cpuid.c: Added comments about various Intel spec updates. * cpuid.man: Removed extra "315593" garbage line. * cpuid.c: Added (synth) for Broadwell-E R0 stepping. * cpuid.c: Added stepping number for Apollo Lake B0/B1. * cpuid.c: Differentiate (synth) between Core & Xeon (0,6),(3,15) Haswell. * cpuid.c: Differentiate (synth) between Core & Xeon (0,6),(2,12) Westmere/Gulftown. * cpuid.c: Simplified more (synth) i*-*000 combinations. * cpuid.c: Removed duplicate slash in one Haswell (synth) line. * cpuid.c: Correct Itanium Merced model/stepping confusion. * cpuid.c: Added KX-5000 & KH-20000 to Zhaoxin WuDaoKou (synth). * cpuid.c: Added die proess to Zhaoxin WuDaoKou (uarch synth). * cpuid.c: Added Zhaoxin LuJiaZiu (0,7),(3,11) model (synth) & (uarch synth). Tue Jan 28 2020 Todd Allen * cpuid.c: Differentiate (synth) between Bay Trail Pentiums, Celerons & Atoms. * cpuid.c: Differentiate (synth) between Braswell Pentiums & Celerons. * cpuid.c: Corrected (synth) steppings for Braswell. * cpuid.c: Add J3000 series to (synth) for Braswell. * cpuid.c: Remove Pentium & Celeron items from {Kaby,Coffee,Comet} Lake Core (synth). I'd already created separate items for those, but missed removing the names from the Core-specific line. Mon Jan 27 2020 Todd Allen * Made new release. Mon Jan 27 2020 Todd Allen * cpuid.c: Changed 0x8000001e/ecx to display nodes per processor in N-1 notation, after receiving confirmation from AMD that this is correct. Sat Jan 25 2020 Todd Allen * cpuid.c: Fixed spelling of (size synth). I meant to always have "synth" at the end of synthesized fields, and had that one flipped around. * cpuid.c: Clarified AVX512_VNNI: neural network instructions. * cpuid.c: Clarified AVX512_VBMI2: byte VPCOMPRESS, VPEXPAND. * cpuid.c: Clarified AVX512_BF16: bfloat16 is a data format, not an instruction. * cpuid.c: Added 7/0/edx md-clear feature, found from Xen & Qemu hypervisors. * cpuid.c: Added 0x80000008/ebx ppin feature, found from Xen hypervisor. * cpuid.c: Added 0x40000001/eax (KVM) flags. * cpuid.c: Got rid of the Transmeta 0x80860001/eax family description, which I missed when I got rid of all 1/eax families. It wasn't so egregious, but it wasn't very valuable either. The Transmeta Crusoe name already was in the (synth) leaf. * cpuid.c: Wrote a version of bits_needed() that uses __builtin_clz with gcc 3.4 and later. * cpuid.c: Fixed bug with old asm-based bits_needed() function when the input value was 0. Sat Jan 25 2020 Todd Allen * cpuid.c: Further clarified descriptions in 0x8000001f leaf, based on text in AMD64 Architecture Programmer's Manual, Vol 3, 3.28. I had missed these new fields in my earlier pass through the manual. * cpuid.c: Added comments for more undocumented fields, noting where the information came from, particularly SKC*, LX*, and sandpile.org. * cpuid.c: Changed case of new descriptions. * cpuid.c: Created Synth_Family() & Synth_Model() macros based on print_1_eax & SKC's AMD_Family() macro. * cpuid.c: Added (family synth) and (model synth) to 0x80000001/eax, (AMD and Hygon variants), just like for 1/eax. * cpuid.c: Added Castle Peak B0 stepping (synth), now that I know the stepping name. * cpuid.c: Changed 0x80000008/ebx "RDPRU instruction" field. * cpuid.c: Clarified 0x80000020 leaf descriptions based on AMD 55803 PPR. * cpuid.c: Modified print_apic_synth's bit width computations to reflect change in terminology (core => thread, CU => core) in AMD Family 17h. * cpuid.man: Updated 54945 PPR name, using newer doc from developer.amd.com. * cpuid.man: Added 55803 PPR, found by URL provided by AMD. * cpuid.man: Updated sandpile.org URL. Sat Jan 25 2020 Todd Allen * cpuid.c: Selectively applied changes from Smita Koralahalli Channabasappa's patch: "Add PQoS feature to CPUID utility and display subleaf 1 for leaf 0x80000020 in the raw CPUID data." * cpuid.c: Renamed fields which no longer are Intel-specific: RDT-CMT/PQoS cache monitoring and RDT-CAT/PQE cache allocation. Fri Jan 24 2020 Todd Allen * cpuid.c: Shortened 0x8000001f leaf descriptions to <= 40 chars. Fri Jan 24 2020 Smita Koralahalli Channabasappa * cpuid.c: Add AMD Secure Encryption feature bits to CPUID utility. * cpuid.c: Update CPUID utility with additional AMD specific features. * cpuid.c: Handle naming issues of cores->threads at register 80000008_ecx and compute unit->core at register 8000001e_ebx for families greater than 16h. Retains previously assigned names if families are lesser than or equal to 16h. Family values are determined by adding family number and extended family number(80000001_eax[8:11] + 80000001_eax[20:27]) as described in PPR under CPUID_Fn00000001_eax. Wed Jan 22 2020 Todd Allen * Made new release. Wed Jan 22 2020 Todd Allen * cpuid.c: In print_80000001_ebx_amd, removed two checks for __M(val_1_eax) >= _XM(0) + _M(0). Yes, gcc, I know that "comparison of unsigned expression >= 0 is always true", and I also know even a half-assed optimizer will get rid of it, so I preferred clarity. But people freak out if the compiler emits any warnings, no matter what crazy -W options the've chosen. So I'm removing them. * cpuid.c: Changed a bunch of ccstring return types to cstring. The extra const in ccstring was meaningless for return types, but it caused a ton of additional -Wignored-qualifiers warnings. No grousing about those warnings; they seem legit. * Makefile: Added -Wextra, so I'll see these before people complain about them in the future. Tue Jan 21 2020 Todd Allen * cpuid.c: Changed Cannon Lake to Palm Cove when talking about uarch. * cpuid.c: Added extra (0,6),(8,14),12 (unknown type) fallback. * cpuid.c: Fixed (0,6),(8,14) Whiskey Lake typo. * cpuid.c: Added i*-9000 names to (0,6),(9,14) Coffee Lake CPUs. Mon Jan 20 2020 Todd Allen * Made new release. Sun Jan 19 2020 Todd Allen * cpuid.c: Fixed (synth) decoding of Kaby Lake vs. Coffee Lake (and their myriad "optimizations"). * cpuid.c: Correctly (synth) decoding of Comet Lake, which was wildly wrong. * cpuid.c: Treating Whiskey Lake, Amber Lake, and Comet Lake as distinct uarchs just causes absurd "Coffee Lake / Whiskey Lake / Amber Lake / Comet Lake" uarch strings. Instead, call all of them Coffee Lake, but turn off the core_is_uarch flag. This ends up treating the other 3 as core names within the Coffee Lake uarch, which seems clearer. * cpuid.c: Renamed Ice Lake to Sunny Cove when talking about uarch. * cpuid.c: Renamed Tiger Lake to Willow Cove when talking about uarch. * cpuid.c: Added (synth) differentiation between Whiskey Lake (U line) & and Amber Lake (Y line). * cpuid.c: Added (synth) differentiation between Whiskey Lake (8000 Series) and Comet Lake (10000 Series). * cpuid.c: Separated (synth) for Goldmont Plus into Pentium & Celeron. * cpuid.c: Fixed Moorefield (synth) to say Z3500 instead of Z3400. * cpuid.c: Fixed (0,6),(5,5),7 to Cascade Lake-X. Core names should be as specific as possible (in contrast to uarch names). * cpuid.c: added (0,6),(2,7) Atom Z2000 Medfield (synth) based on example found on instlatx64. * cpuid.c: Renamed Cedarview (SoC name) to Cedar Trail (core name). * cpuid.c: Added (0,6),(1,15) Havendale/Auburndale (synth). * cpuid.c: Added VIA (0,6),(0,15) Esther C5J (synth). * cpuid.c: Added VIA Nano steppings to (synth). * cpuid.c: Added AMD Ryzen vs. EPYC (synth) differentiation to Castle Peak / Rome. * cpuid.c: Separated Mullins into Mullins (tablets) and Beema (desktop). * cpuid.c: Separated Kabini into Kabini (desktop) and Kyoto (servers). Also added Temash for A-Series, although they're all mixed up with Kabini. * cpuid.c: Added AMD (6,15),(3,8) Godavari (synth) decoding. * cpuid.c: Added AMD (2,15),(0,3) Griffin (synth) decodings. * cpuid.c: Removed duplicate junk code for AMD (1,15),(0,2) which prevented the 3 and 10 steppings from being used. * cpuid.c: Corrected some AMD (0,6),(0,8) Duron Applebred (synth) names. * cpuid.c: Added AMD DG02SRTBP4MFA based on example found on instlatx64. Fri Jan 17 2020 Todd Allen * cpuid.c: Merged 0xb and 0x1f leaf code, much like what Len Brown of Intel suggested a year ago. I don't know why I didn't just do that in the first place. Merged field names look more like the 0x1f names, because I thought they were clearer. * cpuid.c: Removed type descriptions from "--- level ---" sub-headers. Intel docs clarify the levels and types are not related. * cpuid.c: Got rid of the ridiculously overloaded 1/eax family descriptions. That information is nearly useless in isolation and described much better in the new (uarch synth) field. * cpuid.c: Also got rid of 0x80000001/eax family descriptions. It wasn't nearly as bad, but still better to use the (uarch synth) field. * cpuid.c: Because I removed that family information, also updated the decode_uarch* functions with information about older CPU makers' information. * cpuid.c: Added vendor name to (uarch synth). * cpuid.c: Fixed 4 and 0x8000001d leaf descriptions to say that the values are in "minus 1" notation. Steven Noonan hinted that there was something to check here, and there was. * cpuid.c: Added (synth size) field to the 4 and 0x8000001d leaves to compute the cache size, also based on a hint from Steven Noonan. * cpuid.c: Added preliminary Zhaoxin decoding based on limited information I could find. * cpuid.c: Added missing uarch names to decode_uarch_intel(). * cpuid.c: Added note about P5 Tillamook CPUs. * cpuid.c: Added some more die process values. Thu Jan 16 2020 Todd Allen * Made new release. Thu Jan 16 2020 Todd Allen * cpuid.c: Added decode_uarch*() and moved the uarch suffixes there from print_synth*(). print_synth_intel() and print_synth_amd() now call that function to get the suffixes. * cpuid.c: Added print_uarch_synth() to display just those suffixes. * cpuid.c: Added (synth) decoding for Itanium Poulson & Kittson. * cpuid.c: Correct (synth) decoding for Itanium Montecito, Millington, Montvale, Tukwila. * cpuid.c: Cleaned up AMD [Excavator] core names. * cpuid.man: Added some missing Intel spec updates. Wed Jan 15 2020 Todd Allen * cpuid.c: Added "(family synth)" and "(model synth)" to do the combined values used by the linux kernel and AMD. That is: Family = XF + F Model = (XM << 4) + M * cpuid.c: Hunt down the fallback (synth) decodings that just list tons of different possible meanings, all copied from the more specific lines above them. They almost always are wrong; if they were right, the more specific tests would've detected them. So, they're pure guesswork. Replace them with "(unknown type)", which is more honest. * cpuid.c: Simplified Intel Xeon Scalable descriptions. * cpuid.c: Eliminated reiteration of i3-XXXX, i5-XXXX, i7-XXXX CPUs, using i*-XXXX instead. * cpuid.c: Added (synth) decoding for Core i*-4000U seen in the wild. * cpuid.c: Correct missing = symbol in 0x80000001/eax transmeta leaf. * cpuid.c: Added [K6], [K7], [K8] (synth) clarifications for AMD K8 CPUs. * cpuid.c: Added (6,15),(6,5) (synth) based on sample from Alexandros Couloumbis. * cpuid.c: Added AMD "*-Series" queries for the various latters and (synth) rules to use them. Added more rules for AMD architectures that used this nomenclature. * cpuid.c: Changed dO query to sO. Wed Jan 15 2020 Todd Allen * cpuid.c: Clarified (synth) for each microarchitecture to include process-neutral microarchitecture names too: {P6} = (Pentium Pro, Klamath, Deschutes, Katmai, Coppermine, Tualatin, Mendocino, Cascades) {Netburst} = [Willamette, Northwood, Prescott, Cedar Mill] {P6 Pentium M} = (Banias), [Dothan, Yonah] {Core} = [Merom, Penryn] {Nehalem} = [Nehalem, Westmere] {Sandy Bridge} = (Sandy Bridge, Ivy Bridge) {Haswell} = (Haswell, Broadwell) {Skylake} = (Skylake, Kaby Lake, Coffee Lake, Whiskey Lake, Amber Lake, Cascade Lake, Comet Lake, Cooper Lake, Cannon Lake) {Sunny Cove} = (Ice Lake, Tiger Lake) The similarities are hazy in places. But this seems useful to help people who, for example, don't know "Cedar Mill", but do know "Netburst". Also the number of Skylake-related architecture names exploded, and not all "Lake" names belong to Skylake, so this helps to clarify. * cpuid.c: Corrected (synth) for Tolapai to 90nm process. Tue Jan 14 2020 Todd Allen * cpuid.c: Clarified Arrandale & Clarkdale as [Westmere]. * cpuid.c: Clarified Bloomfield, Gainestown & Beckton as [Nehalem]. * cpuid.c: Added [Merom] clarification to a couple CPUs that missed it. * cpuid.c: Added [Cedar Mill] clarification to a couple CPUs that missed it. * cpuid.c: Clarified Dothan, Stealey, Crofton & Tolopai as [Dothan]. * cpuid.c: Clarified Yonah, Sossaman as [Yonah]. * cpuid.c: Did not clarify Banias as [Banias] because it appears there are no non-Banias chips based on it. * cpuid.man: Added handy wiki pages about microarchitectures. Mon Jan 13 2020 Todd Allen * cpuid.c: Added 6/eax HW_FEEDBACK flag. * cpuid.c: Added 7/0/ecx ENQCMD flag. * cpuid.c: Added 7/0/edx AVX512_VP2INTERSECT flag. * cpuid.c: Added 7/1/eax AVX512_BF16 flag. * cpuid.c: Added 0xd/0/eax flags for CET_U & CET_S state. * cpuid.c: Added 0x80000008/ebx WBNOINVD flag. * cpuid.c: Added 0x80000008/ebx SSBD flags from AMD white paper. * cpuid.c: In 7/0/edx leaf, clarified PCONFIG as an instruction. * cpuid.c: Added synth detection for Cyrix MediaGX (circa 1997 SoC). * cpuid.c: Added 7/0/ecx TME flag, discovered in the linux-5.5-rc6 kernel source. * cpuid.c: Added 0x80000008/ebx additional STIBP always on flag, discovered in the linux-5.5-rc6 kernel source. * cpuid.man: Added AMD SSBD white paper. * cpuid.man: Added linux kernel note and clue on what to look for. Sun Jan 12 2020 Todd Allen * cpuid.c: Added Matisse B0 stepping based on sample from Steven Noonan. * cpuid.c: Removed redundant dR lines from Pinnacle Ridge. (They could come back if I see an EPYC based on Pinnacle Ridge, but they're redundant now.) Sun Jan 12 2020 Todd Allen * Made new release. Sun Jan 12 2020 Todd Allen * Makefile, cpuid.proto.spec: Added INSTALL_STRIP to allow disabling the install -s option. This makes rpmbuild & find-debuginfo.sh happy, because they can find the cpuid debug information and create the cpuid-debuginfo rpm. * Makefile: Updated release target to move debugsource rpms too. Sun Jan 12 2020 Todd Allen * cpuid.c: Added 0x40000004 leaf for Xen hypervisor. * cpuid.c: Added 0x40000005 leaf for Xen hypervisor. * cpuid.c: Fixed errors with static ccstring arrays that were not large enough to hold NULLs for all reserved bit field values. * cpuid.c: Added AMD's CMT "compute unit" concept to print_apic_synth by adding that architectural level above the "cores" level, which relects AMD's portrayal. This level is displayed only if it is present. * cpuid.c: Added some undocumented synth decodings found on https://en.wikichip.org/wiki/amd/cpuid. Not everything there makes sense, so I didn't take everything. Marked with comments. * cpuid.c: Added architecture tags to Intel synth decodings: [Willamette], [Northwood], [Prescott], [Merom], [Penryn], [Nehalem], [Westmere]. After that, Intel dropped the hyper-specific code names in favor of suffix letters. * cpuid.c: Added architecture tags to Intel synth decodings: [Bonnell], [Saltwell], [Silvermont], [Airmont], [Goldmont], [Goldmont Plus]. Intel continues to use hyper-specific names for Atom CPUs. Sat Jan 11 2020 Todd Allen * Makefile: Added -Wimplicit-fallthrough -Wunused-parameter options. * cpuid.c: Clarified 4/edx WBINV/INVD flag. * cpuid.c: Added new 7/edx flags, especially including new features to mitigate speculative execution exploits. * cpuid.c: Cleaned up output of 0x10 subleaves. * cpuid.c: Added 0x12/0/ebx CPINFO for #CP exceptions in enclave. * cpuid.c: Properly display 0x18 sub-leaf number. * cpuid.c: Added leaf 0x1f V2 Topology logic to decode_mp_synth() and print_apic_synth(). I have no physical examples, so I only could test with artificial input files. * cpuid.c: Added 3-way and 6-way associativity to 0x80000006 and 0x80000019 leaves. * cpuid.c: Fixed incorrect fallthrough in switch for "41322 3.74: table 16". * cpuid.c: Fixed incorrect fallthrough's in switch for Family 12h tables. * cpuid.c: Added UNUSED macro to make newer gcc's shut up about unused formals. (They have one complaint if the name is omitted, and another complaint if it's specified but unused. There's just no pleasing gcc.) * cpuid.c: Added break after usage() to make gcc shut up about a nonexistent fallthrough (even though it was marked with NOTREACHED). * cpuid.c: Added missing newlines to all the print_2_byte Cyrix/VIA special cases. * cpuid.c: Fixed print_f_0_edx: QoS monitoring was in 0xf/0 bit 1, not bit 0. * cpuid.c: Added print_40000001_edx_kvm and appropriate call. * cpuid.c: For 0x80000001/ebx amd, display PkgType for all family 16h or higher systems, even if no specific BrandId breakdown is known. Added encodings from AMD BKDG and PPR documents. Sat Jan 11 2020 Todd Allen * cpuid.c: Added proper synth decoding for Atom C3000 (Denverton). * cpuid.c: Clarified Goldmont into eithe Apollo Lake or Denverton. * cpuid.c: Corrected (0,6),(9,14) synth decoding to be Coffee Lake. * cpuid.c: Added (0,6),(9,14) Coffee Lake synth decoding steppings. * cpuid.c: Added (0,6),(9,14) Coffee Lake synth decoding for Xeon E-2100 & E-2200. * cpuid.c: Added (0,6),(5,5),7 synth decoding for Xeon 2nd Gen Scalable. * cpuid.c: Added (0,6),(5,5),7 synth decoding for Xeon D-2100. * cpuid.c: Added synth decoding for Gemini Lake R0 stepping (same as B0). * cpuid.c: Added vague synth decoding for (0,6),(6,6) Cannon Lake. * cpuid.c: Added vague synth decoding for (0,6),(6,10) Ice Lake. * cpuid.c: Added vague synth decoding for (0,6),(6,12) Ice Lake. * cpuid.c: Added vague synth decoding for (0,6),(7,13) Ice Lake. * cpuid.c: Added additional synth decodings for AMD Ryzen, including Pinnacle Ridge. * cpuid.c: Differentiate Ryzen from EPYC using brand string and new query functions. * cpuid.man: Added new spec updates, revision guides, etc. Sat Jan 11 2020 Todd Allen * Prettification of Masanori Misono's 0x40000001/eax KVM fields. * Formatting changes & URL removal from Jeffrey Walton's SunOS patch. * Prettification of Thomas Friebel's 0x40000003 leaf fix: while loop. * Reverted print_header() to use !raw (personal preference of mine). * Format changes to & rearrangement of fanjinke's Hygon patch. * Changed Ani Sinha's 0x80000008/ebx indirect branch prediction barrier description to include IBPB acronym. Fri Jan 3 2020 Thomas Friebel * Fixed bug that skipped half the subleaves in the 0x40000003 hypervisor leaf. * Fixed contradictory try logic in print_header() for leaf 0x40000003. * Fixed to use 0x40000003/ebx for high 32 bits of vtsc_offset, instead of using eax for both high & low 32 bits. Fri Nov 8 2019 Ani Sinha * cpuid.c: Added 0x80000001/ecx NB performance counter extensions & 0x80000008/ebx indirect branch prediction barrier. Mon May 13 2019 fanjinke * Added Hygon support. Wed May 8 2019 Jeffrey Walton * cpuid.c: Added support for SunOS build. Sat Mar 2 2019 Masanori Misonoc * cpuid.c: Added 0x40000001/eax KVM bit fields. Fri Jun 1 2018 Tony Luck * cpuid.c: Added decoding of 0x10/3 subleaf. Sat May 26 2018 Todd Allen * cpuid.c: Fixed 7/ecx spelling error: intruction. * cpuid.c: Fixed main spelling error: unrecogized. Sat May 19 2018 Todd Allen * Made new release. Sat May 19 2018 Todd Allen * cpuid.c: Added some more fields reported by Stefan Kanthak, after tracking down some documentation that explains them: * cpuid.c: Added 7/ecx bit 7: CET_SS and 7/edx bit 20: CET_IBT fields. So far, the only documentation for these is Control-flow Enforcement Technology Preview (334525), section 8.2 Feature Enumeration. * cpuid.c: Added 7/ecx bit 16: 5-level paging. So far, the only documentation for this is 5-Level Paging and 5-Level EPT White Paper (335252). * cpuid.c: Improved 14/0/ecx descriptions. * cpuid.c: Added hypervisor leaf descriptions from Microsoft's Hypervisor Top Level Functional Specification (Released Version 5.0b). * cpuid.man: Added the above mentioned docs. Thu May 17 2018 Todd Allen * cpuid.c: Added CPUID features documented in PPR for AMD Family 17h Model 01h B1 (54945 Rev 1.14): * cpuid.c: Added PCOMMIT to 7/ebx: PCOMMIT instruction (a deprecated instruction). * cpuid.c: Added bits to 80000001/ecx (amd). * cpuid.c: Added 80000007/ebx. * cpuid.c: Added 80000007/ecx. * cpuid.c: Added bits to 80000007/edx. * cpuid.c: Added 80000008/ebx. * cpuid.c: Added bits to 8000000a/edx. * cpuid.c: Added bits to 8000001a/eax. * cpuid.c: Added bits to 8000001b/eax. * cpuid.c: Added tentative 8000001f descriptions. Information obtained from Linux kernel 4.17-rc5 arch/x86/kernel/cpu/scattered.c (as patched by Tom Lendacky of AMD on 18-Apr-2017 via LKML), and from Secure Encrypted Virtualization API Version 0.16 Technical Preview (55766 Rev 3.06). * cpuid.man: Added 54945 & 55766 docs. Thu Apr 19 2018 Todd Allen * Made new release. Wed Apr 19 2018 Todd Allen * cpuid.c: Fixed various bugs reported by Stefan Kanthak: * cpuid.c: Fixed bug in print_2_meaning: 0x49 normal & special cases. * cpuid.c: Fixed bug in print_2_meaning: 0x63 additional 2M/4M, 4-way, 32 entries item. * cpuid.c: Collapsed print_2_meaning into print_2_byte so that the prefix and CONT are known in one place. * cpuid.c: Fixed bug in print_2_byte: 0x7d is not sectored. * cpuid.c: Fixed bug in print_2_byte: 0xc2 is 4K, not 4M. * cpuid.c: Changed 6/ecx bit 0 to "hardware coordination feedback". * cpuid.c; Changed 7/ebx bit 3 to "BMI1 instructions". * cpuid.c: Change 7/ebx bit 12 to RDT-M. * cpuid.c: Change 7/ebx bit 15 to RDT-A. * cpuid.c: Corrected "0x40000003/ecx" label. * cpuid.c; print_40000003_edx_microsoft: corrected "idle" spelling. Wed Apr 19 2018 Todd Allen * cpuid.c: Added mnemonic letters for some 1/ecx, 1/edx, and 7/ebx leaf fields. * cpuid.c: Fixed bug with 4/ecx: field name should be "number of sets". * cpuid.c: Fixed bug with 4/ecx leaf: pass ECX to it! * cpuid.c; Fixed bug with 0x10/ecx: pass ECX to it! * cpuid.c: Fixed bug with 0x10/edx: pass EDX to it! Sun Apr 8 2018 Todd Allen * cpuid.c: Added 2 leaf 0xfe encoding: TLB data in leaf 0x18. * cpuid.c: Added new Intel 6/eax bit fields. * cpuid.c: Added new Intel a/edx bit field: anythread deprecation. * cpuid.c: Added new Intel d/0/eax bit field: IA32_XSS HDC state. * cpuid.c: Added new Intel 10/0/ebx bit field: memory bandwidth alloc. * cpuid.c: Added new Intel 12/0/eax bit fields * cpuid.c: Added new Intel 18 leaf: deterministic address translation. * cpuid.c: Added new Intel 7/ecx bit fields from Intel Architecture Instruction Set Extensions and Future Features Programming Reference. * cpuid.c: Added new Intel 1b leaf from Intel Architecture Instruction Set Extensions and Future Features Programming Reference. * cpuid.c: Added synth decoding for Avoton C0 stepping (same as B0). * cpuid.c: Corrected synth decoding for Bay Trail-M C0 steppings. * cpuid.c: Added synth decoding for Bay Trail-I (E3800). * cpuid.c: Added synth decoding for Xeon D-1500N (Broadwell-DE A1). * cpuid.c: Added synth decoding for Xeon E7-4800/8800 (Broadwell-EX B0). * cpuid.c: Correct synth decoding for Bay Trail A0. * cpuid.c: Added synth decoding for Bay Trail D0. * cpuid.c: Added synth decoding for Core X-Series (Skylake-X). * cpuid.c: Added synth decoding for Xeon Scalable (Bronze, Silver, Gold, Platinium) (Skylake). * cpuid.c: Added synth decoding for Pentium Silver (Gemini Lake). * cpuid.c: Added synth decoding for AMD Zen. * cpuid.man: Added new spec updates & PPR. Fri Nov 3 2017 Todd Allen * cpuid.c, cpuid.man: Attribute whitepaper to Shih Kuo. Wed Jun 22 2017 Lars Wendler * cpuid.c: recent glibc versions no longer automagically include sysmacros.h headers. This needs to be done by the source files itself now. Fri Mar 3 2017 Todd Allen * cpuid.c: Added missing SDBG bit to 1/ecx leaf. Sun Jan 22 2017 Todd Allen * Made new release. * cpuid.c: Use __cpuid_count macro for "cpuid" instruction if possible. This macro is present in gcc 4.3.0 and later, and works around the fact that the cpuid instruction writes on the PIC register. This is only important when compiling PIC/PIE. * cpuid.c: Added synth decoding for Intel Knights Landing B0. The Intel docs still don't specify the stepping numbers, but all examples seen so far have stepping number 1, and so far B0 is the only stepping. * cpuid.c: Added new synth decodings for Intel Kaby Lake. * cpuid.c: Fixed synth decodings for AMD Steamroller. * cpuid.c: Fixed synth decodings for AMD Jaguar. * cpuid.c: Added synth decodings for AMD Puma. * cpuid.c: Added synth decodings for AMD Excavator. * cpuid.c: For (6,15),(0,2) Piledriver processors, detect FX series and report it as Vishera instead of Abu Dhabi/Seoul/Delhi. * cpuid.c: Added general microarchitecure names for AMD (e.g. Piledriver) in addition to specific core names (e.g. Trinity) for later generation processors. If I have trouble remembering these, it seems likely other people do too. * cpuid.c: Added synth decoding for Quark X1000. * cpuid.c: Added Intel Atom Z2760 (Clover Trail). * cpuid.c: Added extra synth decodings for some Sandy Bridge processors. * cpuid.c: Added extra synth decodings for some Ivy Bridge processors. * cpuid.man: Added new & missing spec updates & revision guides. * FUTURE: Cleaned this up somewhat. Mon Dec 5 2016 Todd Allen * cpuid.c: Removed stale len variable from do_file(). Thu Dec 1 2016 Todd Allen * Made new release. Wed Nov 30 2016 Todd Allen * cpuid.c: Fixed bugs in the subleaf walks for 0x8000001d (AMD cache information) and 0x40000003 (Xen hypervisor information) because the code for them was under wholly the wrong loops. Thanks to Brice Goglin for detecting this and working out the cause of the bug. Wed Nov 16 2016 Todd Allen * cpuid.c: Updated comments referencing 325462 Table 35-1 to also specify Volume 3. * cpuinfo2cpuid: Added grep commands to EXAMPLES. Mon Nov 14 2016 Todd Allen * Made new release. * cpuid.man: Added 334663 & 334820 spec updates. Sun Nov 13 2016 Todd Allen * cpuid.c: Fixed bug reported by Andrew Cooper where, in do_real, for the 0xd leaf, the lower half of the valid bit set for XSS should've used 0xd/1/ecx instead of 0xd/1/eax. Sadly, this bug affects raw dumps too. * cpuid.c: Added -l/--leaf and -s/--subleaf options to cause cpuid to dump just the specified leaf and subleaf. If -s/--subleaf is not specified, it is assumed to be 0. The intended purpose for this is to display raw dumps of not-yet-supported leaves, or to workaround bugs like the above. Sat Nov 12 2016 Todd Allen * cpuid.c: In bits_needed, add a further check for !defined(__ILP32__), which should help with building a 32-bit version of cpuid on a 64-bit system. Sat Nov 12 2016 Todd Allen * cpuid.c: Made editorial changes to Piotr Luc's patches (spelling, capitalization, register order, comments, etc.). * cpuid.c: Added AVX512DQ, AVX512IFMA, AVX512BW, AVX512VL, and CLWB decoding to 7/ebx. * cpuid.c: Added AVX512VBMI to 7/ecx. * cpuid.c: Added print_f_0_edx to show L3 cache QoS monitoring support. * cpuid.c: Added total & local bandwidth monitoring to 0xf/1/edx. * cpuid.c: Added 0x15/ecx nominal core crystal clock decoding. * cpuid.c: In print_17_0_ebx, corrected reversed scheme encodings. * cpuid.c: Added synth decoding for Xeon D-1500 (Broadwell-DE) Y0 stepping. * cpuid.c: Added synth decoding comment about Braswell D1 stepping, but its stepping number isn't documented. * cpuid.c: Added synth decoding for (0,6),(8,14) Kaby Lake processors. * cpuid.c: Added synth decoding for Apollo Lake processors. * cpuid.c: Added vague synth decoding for (0,6),(9,14) Kaby Lake processors. * cpuid.c: Re-sorted (0,6),(5,7) Knights Landing to correct position. * cpuid.c: Re-sorted (0,6),(5,15) Goldmont to correct position. Sat Oct 27 2016 Piotr Luc * cpuid.c: Add AVX512_4VNNIW & AVX512_4FMAPS flags. * cpuid.c: Add Knights Mill (KNM) CPUID. Sun Aug 14 2016 Todd Allen * Made new release. * Makefile: Added clean rules to remove tarballs & rpm's with other version numbers. Sun Aug 14 2016 Todd Allen * cpuinfo2cpuid: Added a script that takes input from a /proc/cpuinfo file and converts it into suitable input to cpuid. The information that cpuid is capable of producing based on this very limited input information is slight, but apparently there is interest in getting the synthesized (synth) leaf from this. There isn't much value in using it with an actual /proc/cpuinfo file on the local system, because just allowing cpuid to read the local cpuid info will provide better output. But it could be useful for interpreted saved /proc/cpuinfo files from another system. I slapped together the basic logic, and Jirka Hladky turned it into a proper perl script, with actual options, a help screen, and even documentation. I then made some changes to give it some more uniform indentation, whitespace, and such. And to give Jirka Hladky more credit, since his contribution to the script is larger than my own. * Makefile: Added rules to generate cpuinfo2cpuid.man from the =pod data in the script. * Makefile: Added cpuinfo2cpuid & cpuinfo2cpuid.man to the released materials. * cpuid.proto.spec: Added cpuinfo2cpuid & cpuinfo2cpuid.1.gz to released materials. Sun Aug 14 2016 Todd Allen * cpuid.c: Changed instances of Kb to KB. In print_2_meaning, changed an instance of 4k to 4K. Sat Aug 13 2016 Todd Allen * cpuid.c: Added 7/ebx SGX & FDP_EXCPTN_ONLY flags. * cpuid.c: Added 7/ecx BNDLDX/BNDSTX MAWAU value field, RDPID & SGX_LC. * cpuid.c: Added d/0/eax MPX state field. * cpuid.c: In print_d_0_eax, split MPX and AVX-512 all_or_none fields into their component parts. Also added IA32_XSS PT state. * cpuid.c: In print_d_n_ecx, clarify XCR0 as user state and IA32_CXX as supervisor state. * cpuid.c: In print_d_n, add MPX and PT features. * cpuid.c: Renamed leaf 0x10 to Intel's new name. Corrected totally bogus interpretation of subleaf 0. * cpuid.c: Generalize subleaf 0x10/1 to also include 0x10/2, and provide new Intel correct names for each. * cpuid.c: Added 0x14/0 PTWRITE & power event trace. * cpuid.c: Added description for leaf 0x12 (SGX Capability) and all its subleaves. * cpuid.c: Added descriptionf or leaf 0x17 (SoC vendor) and its subleaves. * cpuid.c: Decode new leaf 2 cache descriptors: 0x64 & 0xc4. * cpuid.c: Updated Atom C2000 (Avoton) with A0/A1 steppings. * cpuid.c: Added Atom Z3n00 (Bay Trail-T B2/B3) specific stepping 1. * cpuid.c: Added Xeon D-1500 (Broadwell-DE) V2 stepping. * cpuid.c: Corrected Atom Z8000 (Cherry Trail) with correct model, per changes in its spec update. * cpuid.c: Change the (0,6),(5,14) Skylake descriptions to be more vague to reflect the larger set of existing processors now. * cpuid.c: Add actual information for the (0,6),(4,14) Skylake processors. * cpuid.c: Add actual information for the (0,6),(5,14) Broadwell-E processors. * cpuid.c: Add actual information for the (0,6),(4,15) Broadwell and Broadwell-EX processors. * cpuid.c: Added vague mentions of Goldmont (0,6),(5,12) and (0,6),(5,15) based on 325462 Table 35-1. * cpuid.c: Add Atom S1200 (Centerton) under (0,6),(3,6) thanks to an example provided by Jirka Hladky. * cpuid.c: Added Eden to the list of possible meanings of VIA (0,6),(6,13). An example provided by Daniel Wyatt shows that they sometimes use the simple Eden brand for this architecture. * cpuid.man: Added various new Intel documents used while making the above changes. * cpuid.c: Made -f - operate on stdin. Wed Jun 22 2016 Alan Cox * cpuid.c: Added out-of-memory checks to strregexp. Mon Oct 19 2015 Todd Allen * Updated cpuid.man's list of information sources with new sources used in the 20151017 release (and one renamed source). Sat Oct 17 2015 Todd Allen * Made new release. * cpuid.c: Updated synth decoding for Broadwell processors. * cpuid.c: Added 0xd leaf field. * cpuid.c: Updated and expanded 0x14 leaf fields. * cpuid.c: Added synth decoding for Intel Xeon E7 v2 (Ivy Bridge-EX). * cpuid.c: Added synth decoding for Intel Core i5/i7 (Skylake). * cpuid.c: Added vague synth decodings for a few more future processor models from Intel 64 and IA-32 Architectures Software Developer's Manual (325462), Table 35-1. Thu Oct 15 2015 Hubert Chrzaniuk * cpuid.c: Decode new leaf 2 cache descriptors: 6a, 6b, 6c, 6d. * cpuid.c: added synth decoding for Knights Landing. [NOTE FROM Todd Allen: There is no datasheet or spec update for Knights Landing yet, but Intel 64 and IA-32 Architectures Software Developer's Manual (325462), Table 35-1 mentions that it will have the family & model (0,6),(5,7). Sat Jun 6 2015 Todd Allen * Made new release. * cpuid.man: Added 325462 manual. * cpuid.c: Added new & missing decodings for: 4/ecx, 6/eax, 7/ebx, 7/ecx. * cpuid.c: Overhauled handling of 0xd leaf, based on new and more extensive information in the Intel CPUID documentation, particularly on how to decide which leaves are valid. The approach functions correctly for the subset described in the AMD documentation, too. This overhaul includes information on the XSAVEC, XGETBV, and XSAVES/XRSTORS instructions. * cpuid.c: Renamed 0xf leaves to include "Monitoring". * cpuid.c: Added 0x10 leaves for QoS Enforcement. * cpuid.c: Added new leaf 2 cache meanings: 0x1d, 0x24, 0xa0, 0xc3. * cpuid.c: Added missing i7 synth decoding for (0,6),(3,14). * cpuid.c: Corrected Atom Z3000 model & stepping which were bafflingly wrong: (0,6)(3,5),1 -> (0,6)(3,7),8. * cpuid.c: Corrected other Bay Trail stepping names for Celeron/Pentium N and J series. * cpuid.man: Added references to a bunch of new Intel manuals. * cpuid.c: Added synth decoding for Intel Xeon Phi (Knights Corner). * cpuid.c: Added synth decoding for Intel Atom C2000 (Avoton). * cpuid.c: Added synth decoding for Intel Xeon E5-x600 (Haswell-EP). * cpuid.c: Added synth decoding for Intel Xeon E5-[48]800 (Haswell-EP). * cpuid.c: Added synth decoding for Intel Core M (Broadwell-Y). * cpuid.c: Added synth decoding for Intel Xeon D-1500 (Broadwell-DE). * cpuid.c: Added synth decoding for Intel i7-5000 Extreme (Haswell R2). * cpuid.c: Added synth decoding for Intel Atom Z8000 (Cherry Trail). * cpuid.c: Added synth decoding for Intel Pentium/Celeron N3000 (Braswell). * cpuid.c: Added synth decoding for Intel i7 5th gen (Broadwell). * cpuid.c: Added synth decoding for Intel E3-1200 v4 (Broadwell). * cpuid.c: Added Xeon E5-4600 to synth decoding for other Sandy Bridge E5 processors (it was omitted accidentally). * cpuid.c: Added Pentium D 9xx Processor to synth decoding for Presler D0 (it was omitted accidentally). Fri Mar 21 2014 Todd Allen * cpuid.c: Deal with 0-width PKG_width fields in print_apic_synth(), for CPUs where the SMT_width + CORE_width >= 8. This happens on Xeon Phi chips. Wed Feb 12 2014 Todd Allen * cpuid.c: Added CLFLUSHOPT instruction field to leaf 7, ebx. * cpuid.c: Added Processor Frequency Information leaf (0x16). Tue Feb 11 2014 Todd Allen * Makefile: Added src_tar rule. Tue Feb 11 2014 Todd Allen * cpuid.c: Made changes to allow building and running on kFreeBSD. This started out as a patch from Andrey Rahmatullin, but I refactored it. The changes to disable the cpuid kernel support are protected by a USE_CPUID_MODULE definition. And there's an additional sanity check to reject -k in that case. The changes to use the library versions of sched_setaffinity are protected by USE_KERNEL_SCHED_SETAFFINITY. I continue to go straight to the kernel on linux, though. Tue Feb 11 2014 Todd Allen * Makefile: Reorganized Andrey Rahmatullin's changes a bit and used them in my development build rules (make todd) too. Tue Feb 11 2014 Andrey Rahmatullin * Makefile: Honor CPPFLAGS, CFLAGS and LDFLAGS from the environment. Mon Jan 27 2014 Todd Allen * Makefile: Change to my development build rules (make todd) to use ld's --hash-style=both to avoid a SIGFPE when running on very old 32-bit systems. It has no effect on the tool for anyone else. Thu Jan 23 2014 Todd Allen * Made new release. Thu Jan 23 2014 Todd Allen * cpuid.c: Stop displaying raw hex for 0xc and 0xe leaves, because they are reserved and just contain zeroes. * cpuid.c: Fixed missing leaf 0xf subleaf 1 in do_real(). * cpuid.man: Added reference to Intel Architecture Instruction Set Extensions Programming Reference (319433). * cpuid.c: Added new feature flags from that document. Sun Jan 12 2014 Todd Allen * Made new release. Sun Jan 12 2014 Todd Allen * cpuid.c: Added Celeron B800 synth decoding. * cpuid.c: Added Pentium G3000 & Celeron G1800 synth decoding. * cpuid.c: Added 4th Gen Core family mobile processors synth decoding. * cpuid.c: Added information about E5 v2 processors (no longer just engineering samples) and related Ivy Bridge-EP processors. * cpuid.c: Added Bay Trail (Atom Z3000, etc.) processors synth decoding. Sun Jan 12 2014 Todd Allen * cpuid.man: Added reference to Intel decoding from Intel 64 and IA-32 Architectures Software Developer's Manual Volume 2A: Instruction Set Reference, A-M (253666). * cpuid.c: Added new Intel decodings from that document. Sun Jan 12 2014 Todd Allen * cpuid.c: Added new (instruction supported synth) field to report on instruction support when knowledge of that is scattered across multiple CPUID leaves. PREFETCH/PREFETCHW is the weirdest example. * cpuid.c: Clarified the raw PREFETCH/PREFETCHW field in 80000001 edx leaf with the 3DNow! prefix, similar to the description in the AMD CPUID docs. Thanks to Chris Orgill for reporting these two issues. Fri Sep 27 2013 Todd Allen * cpuid.c: Added missing break to decode_amd_model(), family (0,15), model (4,0), case 0x18. Thanks to David Binderman for reporting this. Mon Jun 10 2013 Todd Allen * Made new release. Mon Jun 10 2013 Todd Allen * cpuid.c: Added mention of Opteron 3200 (Zurich) chips, accidentally omitted from yesterday's updates. Sun Jun 9 2013 Todd Allen * Made new release. Sun Jun 9 2013 Todd Allen * cpuid.c: Updated 14h Model 00h-0Fh AMD model tables. * cpuid.c: Added synth decoding for Opteron x300 (Piledriver) chips. * cpuid.c: Added synth decoding for family 16h processors, tentatively identified as Steamroller. * cpuid.man: Added new AMD 15h Model 10h-1Fh, and AMD 16h Model 00h-0Fh manuals. Sat Jun 8 2013 Todd Allen * cpuid.c: Added sanity check to 0xCxxxxxxx leaves to check for an unreasonably large indicated maximum leaf number. If found, further walk of them is halted. * cpuid.c: Skip 0x4xxxxxxx leaves if cpuid does not indicate that the environment is a guest. This was suggested by Steven Levine, although I implemented it differently. Sat Jun 8 2013 Todd Allen * cpuid.c: Clarified some KVM hypervisor leaf feature flags that Eduardo Habkost pointed out. Added a couple new flags. Sat Jun 8 2013 Todd Allen * cpuid.c: Extended Eduardo Habkost's stash separation to include the 0x80000008 leaf, and the leaves that inform transmeta_info. Sat Jun 8 2013 Eduardo Habkost * cpuid.c: This patch separates the code that changes fields in the 'stash' struct from the code that prints that information. This way, the stash struct will get updated even when in raw mode, so other parts of the code can use that information. [NOTE FROM Todd Allen: It used to be that the stash was only set and used in cooked mode, but some uses dealing with the hypervisor snuck out and were used all the time. This new separation is only really necessary for the hypervisor fields, but it's good practice to do all the fields this way, so I'm accepting the patch as is.] Sat Jun 8 2013 Todd Allen * cpuid.c: Added synth decoding for Celeron G400/G500. * cpuid.c: Added synth decoding for Cedarview B3. * cpuid.c: Added synth decoding for Ivy Bridge i3 processors. * cpuid.c: Added synth decoding for Ivy Bridge Pentium G1600/G2000/G2100. * cpuid.c: Added synth decoding for Ivy Bridge Pentium 900/1000/2000/2100. * cpuid.c: Clarified that Ivy Bridge Xeon E3-1200 is actually E3-1200 v2. * cpuid.c: Added vague synth decoding for Haswell, but spec updates show no specific chips or steppings yet. * cpuid.c: Expanded A100/A110 synth decoding to include semi-official Pentium M (Crofton) processors in Apple TV boxes. * cpuid.c: Added Xeon E5-2600 v2 engineering sample. Perhaps this will be the final synth decoding for them, but for now it's just marked as an engineering sample. * cpuid.man: Added new Intel manuals. Fri Aug 24 2012 Todd Allen * cpuid.c: Added sanity check to 0x4xxxxxxx leaves to check for an unrecognized hypervisor and an unreasonably large indicated maximum leaf number. If found, further walk of them is halted. Tue Aug 21 2012 Todd Allen * cpuid.c: Cleaned up printf(name) statements that were admonished by clang. Fri Jun 1 2012 Todd Allen * Made new release. Thu May 31 2012 Todd Allen * cpuid.c: Updated CPUID feature flags. * cpuid.c: Updated CPUID function 7 to support sub-leaves (mostly for future functionality that might be added to them). * cpuid.c: Updated synth decoding for Intel Dothan C0 because some use 65nm process now. * cpuid.c: Updated Intel EP80579 synth to mention 65nm process. * cpuid.c: Added synth decoding for Intel Atom E600 series. * cpuid.c: Updated synth decoding for Intel Sandy Bridge D2 to include J1 and Q0, which have the same CPUID. * cpuid.c: Added synth decoding for Intel Atom D2000/N2000 (Cedarview). * cpuid.c: Added synth decoding for Intel Sandy Bridge-E. * cpuid.c: Added synth decoding for AMD Llano. * cpuid.c: Improved distinction between AMD Interlagos & Zambezi. * cpuid.c: Added synth decoding for RDC IAD 100. * cpuid.c: Fixed some formatting bugs for Transmeta-specific leaves. * cpuid.c: Added synth decoding for some of VIA's versions of WinChips. * cpuid.man: Added mentions of spec updates for several Atoms, i7 for LGA-2011, and Xeon E5; and AMD 12h family. Wed May 30 2012 Todd Allen * cpuid.c: Fixed ancient bug in distinguishing Irwindale from Nocona (they differ only by L2 cache size). * cpuid.c: Added synth decoding for desktop and mobile Ivy Bridge. Sat Feb 25 2012 Todd Allen * Made new release. * cpuid.c: Cleaned up hypervisor-specific leaves for KVM. * cpuid.man: Added mention of KVM cpuid documentation. Fri Feb 24 2012 Todd Allen * cpuid.c: Added synth decoding for Intel Westmere-EX processors. * cpuid.c: Added synth decoding for AMD family 15h chips: AMD FX (Zambezi), Opteron 6200 (Interlagos), and Opteron 4200 (Valencia). * cpuid.c: Added synth decoding for AMD Z-Series and other Fusion chip ON-C0 steppings. * cpuid.c: Added synth decoding for Atom Z600 (Lincroft). * cpuid.c: Updated AMD model decoding for family 10h processors. * cpuid.man: Added mention of AMD family 14h and 15h documents, and Intel Westmere-EX & Lincroft documents. * cpuid.man: Removed obsolete limitation about 0x8000001b. * cpuid.c: Added support for hypervisor leaves (0x4000000 and after). Interpreted known generic leaves. Interpreted hypervisor-specific leaves for Xen (deduced from source, as no documentation on them exists). Interpreted hypervisor-specific leaves for KVM. Interpreted hypervisor-specific leaves for Microsoft. Tue Jan 3 2012 Todd Allen * cpuid.c: Added synth decoding for Athlon 64 (Venice DH-E6) chips. Wed Nov 2 2011 Todd Allen * cpuid.c: Added saw_4 and saw_b stash flags to deal with chips that report 0xc codes but still omit 0xb codes. This way, a maximum code of 0xc no longer implies the presence of 0xb codes for things like APIC decoding. Mon Mar 28 2011 Todd Allen * cpuid.c: Added APIC synth decoding for AMD, deduced by analogy to Intel code and the multiprocessor synth logic. Mon Mar 7 2011 Todd Allen * cpuid.c: Added some decoding for VIA 0xc0000002 codes, based on information from Juerg Haefliger. Very incomplete because VIA doesn't document their functions well. * cpuid.c: Fixed output of 0xc0000001 raw dump to conform to new style. Sat Mar 5 2011 Todd Allen * Made new release. Fri Mar 4 2011 Todd Allen * cpuid.c,cpuid.man: Added Celeron T1000 series, previously missing. * cpuid.c,cpuid.man: Added Celeron Mobile P4000, U3000 series. * cpuid.c,cpuid.man: Added current Sandy Bridge processors. Thu Mar 3 2011 Todd Allen * cpuid.c: Added detection of PCIDs & TSC-DEADLINE. * cpuid.c: Verified Mike Stroyan CPUID 2 cache meanings from Intel CPUID document (241618-037). Added 0x76 meaning. * cpuid.c: Added various new flags from Intel 241618-037. * cpuid.c,cpuid.man: Added AMD family 14h processors. * cpuid.c,cpuid.man: Updated Intel process id table, mostly as just generalizations. Tue Nov 9 2010 Todd Allen * cpuid.c: Update the usage() screen, since some of its -i and -1 comments are incorrect now. Mon Oct 4 2010 Todd Allen * cpuid.c, cpuid.man: Added AMD Geode LX. * cpuid.c: Added NSC Geode GX2 and AMD Geode GX. * cpuid.c, cpuid.man: Added AMD Geode NX. Sat Oct 2 2010 Todd Allen * Made new release. * cpuid.c,cpuid.man: Added Intel Atom N500. Thu Sep 30 2010 Todd Allen * cpuid.c,cpuid.man: Added support for Intel Tolapai (SoC). * cpuid.c,cpuid.man: Added support for Intel Clarkdale chips from specification update 323179. * cpuid.c: Generalized decode_amd_model by adding full brand tables for AMD chips. If a BIOS doesn't recognize a chip it writes "model unknown" into its brand string via MSR's. decode_override_brand detects that and uses the decode_amd_model brand to differentiate CPUs. * cpuid.c: Corrected 80000001/ebx PkgType, BrandId, and str1 bit fields. * cpuid.c: Corrected problems with brand field decoding because its bit field with differs from architecture to architecture. * cpuid.c: decode_amd_model: the partialmodel decrement special case applies only to XF=1,F=15; and not to XF=2,F=15. Mon Sep 27 2010 Todd Allen * cpuid.c: Added support for NSC/AMD Geode GX1. Wed Sep 8 2010 Todd Allen * cpuid.c: Corrected the Transmeta processor revisions, which should've been in hex instead of octal. Thu Sep 2 2010 Todd Allen * cpuid.c: Added a couple vague steppings for Transmeta Efficeon TM8000 processors. Updated some transmeta bitfields. This is all done blind, as I have no examples of these chips, little documentation, and the company is long defunct. Thu Sep 2 2010 Todd Allen * Made new release. * cpuid.c: Fixed a few header strings that had incorrect function hex codes or registers. Wed Sep 1 2010 Todd Allen * Made new release. * cpuid.c: Fixed buffer size in do_file() to be able to read new raw dumps with ecx information. It needed a couple more characters. * cpuid.c: Added Celeron M (Yonah D0) & Celeron M (Merom-L1 A1) synth entries. * cpuid.c: added Xeon Processor LV (Sossaman D0). * cpuid.c: Update Itanium chips in the synth tables. Sadly, this all still is being done blind, as I have no access to any Itanium chips. * cpuid.c: Wrote an x86_64 counterpart to the assembly code for bits_needed(). * Makefile, cpuid.proto.spec: Changed to support building for both i386 and x86_64. Tue Aug 31 2010 Todd Allen * Made new release. * cpuid.c: Rearranged synth rules and substantially simplified query macros into something like the form I was hoping for when I started this redesign. * cpuid.c: Added changes from the new AMD CPUID document that claims to have been released in September 2010! * cpuid.c: Changed raw dump to include %ecx values to accomodate CPUID functions with gaps in the useful %ecx range (e.g. 0xd). The file parser accepts either the old or new forms. * Makefile, cpuid.proto.spec: Updated build scheme for my current systems. * LICENSE: Changed to a GPL license. Mon Aug 30 2010 Todd Allen * cpuid.c: Semi-mechanically eliminated the codes used to disambiguate in the synth string and replaced them with queries, which I think will be more general-purpose and will allow me to eliminate a lot of the problem with codes appropriate for one model being a problem for subsequent models (e.g. the Core Solo vs. Core Duo distinction). There still are general-purpose queries like there were general-purpose codes, but the special-case queries will only matter for those families that care about them. This does mean that it's possible for multiple queries to register as true, so I have to be more careful with the order of chips in the synth tables. Fri Aug 27 2010 Todd Allen * Tested on a variety of CPUs. * cpuid.c: Corrected Mobile Turion checking in decode_brand. * cpuid.c: Added synth entries for 6/15/4 pre-production Conroe B0/Woodcrest B0. * cpuid.c: Added synth entries for Santa Rosa F3 stepping (undocumented). * cpuid.c: Fixed synth entries for Brisbane, Toledo, and Windsor to expect code DA (for dual-core Athlons). * cpuid.c: Generalized the check for Intel Extreme Edition chips. * cpuid.c: Added synth entries Core 2 Quad (Conroe) chips. * cpuid.c: Added synth entry for VIA 6/13/0 chip. Unfortunately, there is no documentation and very little anecdotal evidence of this chip, so the description is vague. * cpuid.c: Added addition CPUID function 2 cache codes from Mike Stroyan. * cpuid.c: Fixed some cut&paste errors that had EAX where it should have been EBX, as reported by Mike Stroyan * cpuid.c: Added very short synth table for SiS chips. I found no documentation on these, so I just have the one case. * cpuid.c: Fixed the (synth) strings for oddball chips, which suffered from a cut&paste error. * cpuid.c: Simplified some of the fallback strings that had grown ridiculously long. Thu Aug 26 2010 Todd Allen * Tested on a variety of CPUs. * cpuid.c: Added more logic for Woodcrest pre-production chips. * cpuid.c: Corrected synth logic for VIA Antaur chips. * cpuid.c: Added synth for plain vanilla Thoroughbred Athlon. Wed Aug 25 2010 Todd Allen * Tested on a variety of CPUs. * cpuid.c: Fixed a couple bugs with decoding processor numbers in print_synth_amd_model. Tue Aug 24 2010 Todd Allen * cpuid.c: Further changes to mp_synth decoding, including tracking of the decoding method used (there are around 4 major approaches, depending on how you count). * cpuid.c: Added apic_synth decoding to find the appropriate field widths and decode the process local APIC physical ID. This is useful in its own right, but also helps convince me that many Intel chips really do claim to have hyperthreads even though they don't. * cpuid.c: Added support for direct instruction (-i) functionality to report on all CPUs by calling sched_setaffinity to reschedule the process on each CPU. This is now the default behavior for -i, but it can be overridden with the -1 option. * cpuid.c: added Barcelona B1 (undocumented chip) synth decoding. Mon Aug 23 2010 Todd Allen * cpuid.c: Made real_get pass the requested ecx values even when using -k. Modern linux kernel expect the ecx values in the upper 32 bits of the file offset (i.e. lseek64). * cpuid.c: Worked out a fallback for determining mp_synth information for Intel chips which lack CPUID function 4. * cpuid.c: Added mechanism for determining mp_synth information from CPUID function 11 information if it's available (because if it's present on Intel chips, it's the only reliable way; the older mechanisms return gibberish). Fri Aug 20 2010 Todd Allen * cpuid.c, cpuid.man: Added to synth even more Nehalem chips. * cpuid.c: Added 6/15 model for VIA Nano, but there's very little detailed information on this chip, so that's it. * cpuid.c: Corrected some AMD codename confusion from 2006: Dublin->ClawHammer/Odessa, Sonora->Dublin, Palermo(mobile)->Georgetown/Sonora, Lancaster->Lancaster/Richmond, Richmond->Taylor/Trinidad. * cpuid.c: Overhauled the AMD model dumping code to understand new families. * cpuid.c: Tweaked decode_mp_synth to use ApicIdCoreIdSize, per AMD's CPUID recommendations. Thu Aug 19 2010 Todd Allen * cpuid.c, cpuid.man: Updated synth tables for Intel Xeons. * cpuid.c: Removed all the "How to distinguish" comments, since it seems to be very common for Intel to have indistinguishable processors nowadays (the old cache-checking tricks are unreliable now). * cpuid.c, cpuid.man: Added to synth additional Nehalem chips as I'm able to hunt them down. Wed Aug 18 2010 Todd Allen * cpuid.c, cpuid.man: Updated synth tables for Intel Core 2, Atom, Celeron, and Pentium chips based on the same cores. Tue Aug 17 2010 Todd Allen * cpuid.c, cpuid.man: Updated synth tables for AMD family 10h (K10) and family 11h processors. * cpuid.c: simplified print_x_synth_amd by pruning its table down to just the three families that differ from normal 1/eax simple synth, and falling back on 1/eax simple synth otherwise. Mon Aug 16 2010 Todd Allen * cpuid.c: Added new steppings to synth tables using latest spec updates for all AMD processor families already in them. * cpuid.c, cpuid.man: Updated synth tables for AMD family 0Fh (K8) processors. Fri Aug 13 2010 Todd Allen * cpuid.c: Updated raw data dump based on latest CPUID documentation from Intel & AMD. * cpuid.c: Fixed dump of function 4 to iterate over all caches. Thu Aug 12 2010 Todd Allen * cpuid.c: Reorganized synth tables to always use extended family and extended model numbers since they are so prevalent on modern chips. * cpuid.c: Added new steppings to synth tables using latest spec updates for all Intel processor families already in them. Sun Nov 26 2006 Todd Allen * cpuid.c: Recognize Intel Core 2 Extreme Edition from brand string. Thanks to Tony Freitas for explaining that Ennnn means desktop while Xnnnn means Extreme Edition for those processors. Wed Nov 22 2006 Todd Allen * cpuid.c: Recognize Itanium2 Montecito C2. * cpuid.c: Recognize Intel Core 2 Duo Mobile (Conroe B2). * cpuid.c: Recognize Intel Quad-Core Xeon Processor 5300 (Woodcrest B3) and Intel Core 2 Extreme Quad-Core Processor QX6700 (Woodcrest B3). * cpuid.c: Recognize Intel Celeron D Processor 36x (Cedar Mill D0). * cpuid.c: Distinguish Core 2 Duo from Core 2 Extreme Edition based on presence or absence of hyperthreading. Thanks to Tony Seacow for providing output for numerous processors and the advice about hyperthreading. Thu Nov 2 2006 Todd Allen * cpuid.c: Changed "number of logical CPU cores - 1" to "number of CPU cores - 1". Sun Sep 17 2006 Todd Allen * Made new release. * cpuid.c: Made the cpuid instruction (-i, --inst options) the default. * cpuid.c: Added -k, --kernel option to cause the kernel module to be used. * cpuid.c: Removed confusing CPU number from output when using the cpuid instruction. * cpuid.man: Updated with new options. * cpuid.c, Makefile: Changed i386 _llseek kludge to workaround offsets >= 0x80000000. Now using -D_FILE_OFFSET_BITS=64 in the Makefile instead. This should allow the i386 cpuid to work on an x86_64 system. * cpuid.c: Added knowledge of CPU modules to synthesized field: Tulsa, Woodcrest B1 (pre-production) * cpuid.c: In synthesized model field, properly distinguish between Intel Pentium D Processor 8x0 and Intel Pentium Extreme Edition Processor 840 (both Smithfields). * cpuid.man: Added mention of new 7100 series spec updates. * cpuid.spec: Changed Copyright to License. Thu Aug 23 2006 Todd Allen * cpuid.c: Removed unnecessary one_cpu argument from do_file. * cpuid.c: Added -v option to display version number. Wed Aug 23 2006 Todd Allen * Made new release. Tue Aug 22 2006 Todd Allen * cpuid.c, cpuid.man: Added -i option to use the CPUID instruction directly instead of the CPUID kernel module. * cpuid.c: Change Pentium Processor 9x0 to 9xx because of 9x5 processors. * cpuid.man: Updated information about determining synthesized model information, and added information about determining synthesized multiprocessor information. Mon Aug 7 2006 Todd Allen * cpuid.proto.spec: Change URL to cpuid-specific page. Sun Aug 6 2006 Todd Allen * Made new release. Sat Aug 5 2006 Todd Allen * cpuid.c: Added support for differentiating Core 2 Duo CPUs from Xeon 5100 CPUs based on the brand string. * cpuid.c: Clarified that CPUID 4 ECX contains one less than the number of sets. * cpuid.c: Added support for CPUID 5 ecx & edx. * cpuid.c: Added support for CPUID 6 ecx. * cpuid.c: Added support for CPUID 0xa eax & ebx. * cpuid.c: Made CPUID functions 7, 8, and 9 reserved (i.e. say nothing until and unless they are defined). * cpuid.c: Corrected CPUID 1 ecx xTPR disabnle. Wed Aug 2 2006 Todd Allen * cpuid.c: Corrected bug with Core 2 Duo recognition. * cpuid.c: Distinguish between Allendale and Conroe cores based on L2 cache size. * cpuid.c: Added VIA C7 & C7-M names to Esther WinChip C5J core CPUs. * cpuid.man: Mention wikipedia pages for CPUs. Tue Aug 1 2006 Todd Allen * cpuid.c: On help screen, clarified that -f option reads output from -r option. * cpuid.proto.spec: Used %{} macros for external command invocations. Mon Jul 31 2006 Todd Allen * Makefile: Removed install -o 0 -g 0 options. For installations from the tarball, the user will have to be root anyway. And for rpm, the %defattr() attribute in the spec is handling this more cleanly. Finally, those options are causing some non-root installations to have to be done by the root user, which is undesirable. * cpuid.c: Improved identification for VIA C3 (Samuel WinChip C5A core). * cpuid.c: Loosened up check for "Mobile AMD Athlon(tm) XP" by removing "-M" suffix. * cpuid.c: Recognize mobile Athlon XP (Thoroughbred). Sun Jul 30 2006 Todd Allen * Made new release. * cpuid.c: Fixed "deterministic cache parameters (4)", so that its children aren't staggered. * cpuid.c: Corrected Venice and Palermo processors with DH-E3 and DH-E6 steppings that had been reported as Toledo processors incorrectly. * cpuid.c: Corrected codename for the Athlon Thoroughbred's Duron counterpart: Applebred. * cpuid.c: Added code to distinguish Athlon XP Thortons from Bartons, based on L2 cache size. * cpuid.c: Added code to distinguish Athlon 64 X2 Manchester E6 from Athlon 64 X2 Toledo. * cpuid.c: Added Celeron Yonah C0. * cpuid.c: Added Core Yonah D0. * cpuid.c: Added Xeon Nocona R0 / Irwindale R0 stepping. * cpuid.c: Added Pentium 4 Cedar Mill C1, Pentium D Presler C1, and Xeon Dempsey C1. * cpuid.c: Added Xeon Woodcrest B2. * cpuid.c: Added Core 2 Conroe B1 & B2 & Core 2 Extreme Processor B1 & B2. * cpuid.c: Updated Itanium2 processors. * cpuid.man: Added Intel specification updates for new CPUs. Wed Jul 26 2006 Todd Allen * cpuid.c: In decode_brand, added check for "Athlon(TM) XP", equivalent to "Athlon(tm) XP". * cpuid.c: Fixed "80000002" typo in print_80860002_eax(). Mon Jul 24 2006 Todd Allen * cpuid.c: Distinguish properly between Core Solo, Core Duo, and Xeon Processor LV. Reorganized multi-processor decoding to support that. Sun Jul 23 2006 Todd Allen * cpuid.c: Fixed emission of raw values for cpuid code 2. * cpuid.c: Added -f file option to read raw hexadecimal input from a file and parse it instead of executing the cpuid instruction, and code reorganization to support this. Mon May 22 2006 Todd Allen * cpuid.c: Fixed "unrecogninzed" typo in error. Fri Apr 7 2006 Todd Allen * cpuid.proto.spec: Added %defattr so that the files in the rpm's are owned by "root" and not "todd". (Why did no one scream bloody murder about this before?) Mon Apr 3 2006 Todd Allen * Made new release. * cpuid.c: Added code to distinguish between the two different Dual-Core Xeon (Paxville A0) and Dual-Core Xeon Processor 7000 (Paxville A0). Empirically, the significant differences are the VMX flag and the "execution disable" flag. The VMX flag is in an Intel-defined CPUID function, so it's used. Thanks to Jason Nicholls for providing the Dual-Core Xeon (Paxville A0) output that made this possible. * cpuid.c: Added detection for Xeon Processor LV (Sossaman C0). Mon Mar 13 2006 Todd Allen * Made new release. * cpuid.c: Fixed code that distinguished processors based on presence or absence of L3 cache. Some of the cache codes weren't being recognized as L3 cache. Sun Feb 26 2006 Todd Allen * Made new release. Wed Feb 22 2006 Todd Allen * cpuid.c: Added VMX: virtual machine extensions to CPUID function 1, register ecx. * cpuid.c: Added SVM LBR virtualization to CPUID function 8000000a, register edx. * cpuid.c: Fixed cut & paste header error in print_8000000a_eax. Tue Feb 21 2006 Todd Allen * cpuid.c: Renamed "hyper-threading technology" field to "hyper-threading / multi-core supported" to eliminate some confusing situations, such as Northwood chips which nominally support hyper- threading, but where it is disabled in the chip; or where hyper- threading is disabled in the BIOS; or AMD multi-core chips, which indicate TRUE here, but all of which lack hyper-threading at present. * cpuid.c: Updated family 15 description, which had grown very stale. * cpuid.c: Generalized Intel Pentium D Processor 900 to 9x0. * cpuid.c: Added Processor Number info to Smithfield processors. Wed Feb 8 2006 Todd Allen * Made new release. * cpuid.c: Use defined(i386) instead of __LONG_MAX__ to determine whether or not it's necessary to use _llseek(). Fixes handling of functions >= 2**31 on some build systems, like the one I used to build the binary rpm. (D'oh!) And also indirectly affects the (synth) field. * cpuid.c: Fix a busted error check in read_reg() that caused it to return success if the read() failed and quiet was true. * LICENSE: Created LICENSE file (using content straight out of the man page). Tue Feb 7 2006 Todd Allen * Made new release. * cpuid.c: Correctly distinguish Egypt/Italy processors. * cpuid.c: Fixed minor problems in error checking in open_file(). * cpuid.spec: Fixed bad Packager field. * cpuid.spec: Include ChangeLog. * cpuid.man: Added -r/--raw description. * cpuid.man: Clarified info used for (synth) field. * cpuid.man: Fixed version number & date. * Makefile: Reworked to make it easy for people other than me to build and install. * cpuid.spec: Used new Makefile organization * Makefile: Fixed production of spec file so that it's possible to rebuild with the srpm without having to specify %version and %release. Mon Feb 6 2006 Todd Allen * Initial public release. cpuid-20250316/cpuid.man0000666001234300001440000006504714765705273013574 0ustar toddusers.\" .\" $Id: cpuid.man,v 20250316 2025/03/16 20:35:23 todd $ .\" .TH CPUID 1 "16 Mar 2025" "20250316" .SH NAME cpuid \- Dump CPUID information for each CPU .SH SYNOPSIS .B cpuid \fI[options...]\fP .SH DESCRIPTION .I cpuid dumps detailed information about the CPU(s) gathered from the CPUID instruction, and also determines the exact model of CPU(s) from that information. It dumps all information available from the CPUID instruction. The exact collection of information available varies between manufacturers and processors. The following information is available consistently on all modern CPUs: .nf vendor_id version information (1/eax) miscellaneous (1/ebx) feature information (1/ecx) .fi It also produces synthetic fields based on information from multiple CPUID functions. Currently, the synthetic fields are the exact model of each CPU (but see LIMITATIONS below) as (synth); the multiprocessing characteristics including the number of cores per chip (c) and the number of hyperthreads per core (t) as (multi-processing synth); and a decoding of the APIC physical ID as (APIC synth). The determination of the model is based on the following information: .nf version information (1/eax), processor type version information (1/eax), family version information (1/eax), model version information (1/eax), stepping id version information (1/eax), extended family version information (1/eax), extended model feature information (1/ecx), virtual machine extensions brand id (1/ebx) brand (0x80000004) cache and TLB information (2) deterministic cache parameters (4/eax), extra processor cores AMD extended brand id (0x80000001/ebx) AMD extended processor signature (0x80000001/eax) Transmeta processor revision ID (0x80860001/ebx & ecx) .fi The determination of the multiprocessing characteristics and decoding of APIC physical ID is based on the following information: .nf feature information (1/edx), hyper-threading / multi-core supported miscellaneous (1/ebx), cpu count deterministic cache parameters (4/eax), extra processor cores on this die x2APIC features / processor topology (0xb) AMD feature flags (0x80000001/ecx) AMD Logical CPU cores (0x80000008/ecx), number of logical CPU cores - 1 .fi In addition, a simpler and coarser determination of the CPU is performed using only the information listed above under version information (1/eax). It is provided as (simple synth) under version information (1/eax). However, it tends to be unable to distinguish between various modern CPUs. .SH OPTIONS .PP .I cpuid accepts the following command line arguments: .TP 8 .I -1, --one-cpu Display information only for the first CPU. This cuts down on the output on a multiprocessor system, and is useful when certain that all CPUs are identical. .TP 8 .I -f \fIFILE\fR, --file=\fIFILE\fR Read raw hex information from FILE instead of from executions of the cpuid instruction. If the filename is '-', instead read from standard input. .TP 8 .I -l \fILEAF\fR, --leaf=\fILEAF\fR Display information only for the specified LEAF. .TP 8 .I -s \fISUBLEAF\fR, --subleaf=\fISUBLEAF\fR Display information only for the specified SUBLEAF. It requires the -l or --leaf option to specify the LEAF. .TP 8 .I -h, -H, --help Display help information. .TP 8 .I -i, --inst Use the CPUID instruction. The information it provides is reliable. It is not necessary to be root to use this option. (This option is the default.) .TP 8 .I -k, --kernel Use the CPUID kernel module. The information does not seem to be reliable on all combinations of CPU type and kernel version. Typically, it is necessary to be root to use this option. .TP 8 .I -r, --raw Display only raw hex information with no decoding. .TP 8 .I -v, --version Display cpuid version. .SH LIMITATIONS There are numerous cases where there is no way to distinguish between various CPUs in the (synth) information. In some cases, the sizes of caches, number of cores, brand strings, etc., can be used to distinguish multiple CPUs with the same family and model. But there are cases where that information is insufficient. Whenever .I cpuid is unable to distinguish between multiple CPUs, it will list all known possibilities. If you believe that a certain processor should be distinguishable from another and it isn't, please inform the author of this tool. The (multi-processing synth) information is unreliable on many processors. It faithfully reports the information provided by the CPUID instruction and decodes it as recommended by the processor manufacturers, but often that information is incorrect. The information seems to indicate the architecture's capabilities, rather than what the particular chip actually does. In particular, it seems commonplace to claim the presence of multiple hyperthreads when there is only one. .SH INFORMATION SOURCES Information on the CPUID instruction and on specific CPUs is available from the following documents from Intel Corporation , with the specified Document Numbers: .RS .br 241618: Intel Processor Identification and the CPUID Instruction, Application Note 485 .br 242480: Pentium Processor Specification Update .br 242689: Pentium Pro Processor Specification Update .br 243326: 60- and 66-MHz Pentium Processor Specification Update .br 243337: Intel Pentium II Processor Specification Update .br 243748: Intel Celeron Processor Specification Update .br 243776: Intel Pentium II Xeon Processor Specification Update .br 243887: Mobile Intel Pentium II Processor Specification Update .br 244444: Mobile Intel Celeron Processor at 466 MHz, 433 MHz, 400 MHz, 366 MHz, 333 MHz, 300 MHz, and 266 MHz Specification Update .br 244453: Intel Pentium III Processor Specification Update .br 244460: Intel Pentium III Xeon Processor Specification Update .br 245306: Mobile Intel Pentium III Processor and Mobile Intel Pentium III Processor-M Specification Update .br 245421: Mobile Intel Celeron Processor (0.18u and 0.13u) Specification Update .br 249199: Intel Pentium 4 Processor Specification Update .br 249678: Intel Xeon Processor Specification Update .br 250721: Mobile Intel Pentium 4 Processor-M Specification Update .br 251309: Mobile Intel Celeron Processor on .13 Micron Process in Micro-FCPGA Package Specification Update .br 252665: Intel Pentium M Processor Specification Update .br 253176: Mobile Intel Pentium 4 Processor with 533 MHz System Bus Specification Update .br 253666: 64 and IA-32 Architectures Software Developer's Manual Volume 2A: Instruction Set Reference, A-M. .br 276613: Detecting Multi-Core Processor Topology in an IA-32 Platform by Khang Nguyen and Shihjong Kuo .br 290741: Intel Xeon Processor MP Specification Update .br 290749: Intel Celeron Processor in the 478-Pin Package Specification Update .br 300303: Intel Celeron M Processor Specification Update .br 302209: Intel Pentium M Processor on 90nm Process with 2-MB L2 Cache Specification Update .br 302352: Intel Pentium 4 Processor on 90 nm Process Specification Update .br 302354: Intel Celeron D Processor 3xx Sequence Specification Update .br 302402: Intel Xeon Processor with 800 MHz System Bus .br 302441: Mobile Intel Pentium 4 Processor supporting Hyper-Threading Technology on 90-nm process technology Specification Update .br 306752: 64-bit Intel Xeon Processor MP with 1 MB L2 Cache Specification Update .br 306757: 64-bit Intel Xeon Processor MP with up to 8 MB L3 Cache Specification Update .br 306832: Intel Pentium Processor Extreme Edition and Intel Pentium D Processor Specification Update .br 309159: Dual-Core Intel Xeon Processor 2.80 GHz Specification Update .br 309222: Intel Core Duo Processor and Intel Core Solo Processor on 65 nm Process Specification Update .br 309627: Dual-Core Intel Xeon Processor 7000 Sequence Specification Update .br 310307: Intel Pentium D Processor 900 Sequence and Intel Pentium Processor Extreme Edition 955, 965 Specification Update .br 310309: Intel Pentium 4 Processor 6x1 Sequence Specification Update .br 311392: Dual-Core Intel Xeon Processor LV and ULV Specification Update 311827: Intel Celeron D Processor 300 Sequence Specification Update .br 313065: Dual-Core Intel Xeon Processor 5000 Series Specification Update .br 313279: Intel Core 2 Extreme Processor X6800 and Intel Core 2 Duo Desktop Processor E6000 Sequence Specification Update .br 313356: Dual-Core Intel Xeon Processor 5100 Series Specification Update .br 313515: Intel Pentium Dual-Core Processor Specification Update .br .br 314079: Intel Core 2 Duo and Intel Core 2 Solo Processor for Intel Centrino Duo Processor Technology Intel Celeron Processor 500 Series Specification Update 314554: Dual-Core Intel Xeon Processor 7100 Series Specification Update .br 314916: Dual-Core Intel Xeon Processor 3000 Series Specification Update .br 315593: Intel Core 2 Extreme Quad-Core Processor QX6000 Sequence and Intel Core 2 Quad Processor Q6000 Sequence Specification Update .br 316134: Quad-Core Intel Xeon Processor 3200 Series Specification Update .br 316515: Intel Pentium Dual-Core Processor Specification Update .br 316964: Intel Celeron Processor 400 Series Specification Update .br 316982: Intel Pentium Dual-Core Desktop Processor E2000 Series Specification Update .br 317667: Intel Celeron Processor 500 Series Specification Update .br 318081: Intel Xeon Processor 7200 and 7300 Series Specification Update .br 318547: Intel Celeron Processor 200 Sequence Specification Update .br 318585: Intel Xeon Processor 5400 Series Specification Update .br 318586: Intel Xeon Processor 5200 Series Specification Update .br 318727: Intel Core 2 Extreme Processor QX9000 Series and Intel Core 2 Quad Processor Q9000, Q9000S, Q8000, Q8000S Series Specification Update .br 318733: Intel Core 2 Duo Processor E8000 and E7000 Series Specification Update .br 318915: Intel Core 2 Duo Processor and Intel Core 2 Extreme Processor on 45-nm Process Specification Update .br 318925: Intel Celeron Dual-Core Processor E1000 Series Specification Update .br 319006: Dual-Core Intel Xeon Processor 3100 Series Specification Update .br 319007: Quad-Core Intel Xeon Processor 3300 Series Specification Update .br 319129: Intel Core 2 Extreme Processor QX9775 Specification Update .br 319433: Intel Architecture Instruction Set Extensions Programming Reference .br 319536: Intel Atom Processor Z5xx Series Specification Update .br 319735: Intel Celeron Dual-Core Processor T1x00 Series Specification Update .br 319978: Intel Atom Processor 200 Series Specification Update .br 320047: Intel Atom Processor N270 Series Specification Update .br 320121: Intel Core 2 Extreme Quad-Core Mobile Processor, Intel Core 2 Quad Mobile Processor, Intel Core 2 Extreme Mobile Processor, Intel Core 2 Duo Mobile Processor, Intel Core 2 Solo Mobile Processor and Intel Celeron Processor on 45-nm Process Specification Update .br 320257: Intel EP80579 Integrated Processor Product Line Specification Update .br 320336: Intel Xeon Processor 7400 Series Specification Update .br 320468: Intel Pentium Dual-Core E6000 and E5000 Series Specification Update .br 320529: Intel Atom Processor 300 Series Specification Update .br 320767: Intel Core i7-900 Mobile Processor Extreme Edition Series, Intel Core i7-800 and i7-700 Mobile Processor Series Specification Update .br 320836: Intel Core i7-900 Desktop Processor Extreme Edition Series and Intel Core i7-900 Desktop Processor Series Specification Update .br 321324: Intel Xeon Processor 5500 Series Specification Update .br 321333: Intel Xeon Processor 3500 Series Specification Update .br 322166: Intel Core i7-800 and i5-700 Desktop Processor Series Specification Update .br 322373: Intel Xeon Processor 3400 Series Specification Update .br 322568: Intel Celeron Processor E3x00 Series Specification Update .br 322849: Intel Atom Processor N400 Series Specification Update .br 322861: Intel Atom Processor D400 Series (Single Core) Specification Update .br 322862: Intel Atom Processor D500 Series (Dual Core) Specification Update .br 322814: Intel Core i7-600, i5-500, i5-400 and i3-300 Mobile Processor Series Specification Update .br 322911: Intel Core i5-600, i3-500 Desktop Processor Series and Intel Pentium Processor G6950 Specification Update .br 323056: Intel Xeon Processor L3406 Specification Update .br 323179: Intel Core i7-660UE, i7-620LE/UE, i7-610E, i5-520E, i3-330E and Intel Celeron Processor P4505, U3405 Series Datasheet Addendum Specification Update .br 323105: Intel Xeon Processor C5500/C3500 Series Specification Update .br 323254: Intel Core i7-900 Desktop Processor Extreme Edition Series and Intel Core i7-900 Desktop Processor Series on 32-nm Process Specification Update .br 323338: Intel Xeon Processor 3600 Series Specification Update .br 323344: Intel Xeon Processor 7500 Series Specification Update .br 323372: Intel Xeon Processor 5600 Series Specification Update .br 323874: Intel Pentium P6000 and U5000 Mobile Processor Series Specification Update .br 324209: Intel Atom Processor E6xx Series Specification Update .br 324341: Intel Atom Processor N500 Series Specification Update .br Intel 64 Architecture Processor Topology Enumeration (Whitepaper) by Shih Kuo .br 324456: Intel Celeron Mobile Processor P4000 and U3000 Series Specification Update .br 324643: 2nd Generation Intel Core Processor Family Desktop Specification Update .br 324827: 2nd Generation Intel Core Processor Family Mobile Specification Update .br 324972: Intel Xeon Processor E3-1200 Product Family Specification Update .br 325122: Intel Xeon Processor E7-8800 / 4800 / 2800 Product Families Specification Update .br 325307: Intel Atom Processor Z600 Series Specification Update .br 325309: Intel Atom Processor Z6000 Series Specification Update .br 325462: Intel 64 and IA-32 Architectures Software Developer's Manual Combined Volumes: 1, 2A, 2B, 2C, 2D, 3A, 3B, 3C, 3D, and 4 .br 325630: Intel Atom Processor Z6xx Series Specification Update .br 326140: Intel Atom Processor N2000 and D2000 Series Specification Update .br 326198: Intel Core i7 Processor Family for the LGA-2011 Socket Specification Update .br 326510: Intel Xeon Processor E5 Family Specification Update .br 326766: Desktop 3rd Generation Intel Core Processor Family Specification Update .br 326770: Mobile 3rd Generation Intel Core Processor Family Specification Update .br 326774: Intel Xeon Processor E3-1200 v2 Product Family Specification Update .br 327335: Intel Xeon and Intel Core Processors For Communications Infrastructure Specification Update .br 328105: Intel Atom Processor Z2760 Specification Update .br 328198: Intel Atom Processor S1200 Product Family for Microserver Specification Update .br 328205: Intel Xeon Phi Coprocessor x100 Product Family Specification Update .br 328899: Desktop 4th Generation Intel Core Processor Family Specification Update .br 328903: Mobile 4th Generation Intel Core Processor Family Specification Update .br 328908: Intel Xeon Processor E3-1200 v3 Product Family Specification Update .br 329189: Intel Xeon Processor E5 v2 Product Family Specification Update .br 329376: Intel Xeon E3-1125C v2, E3-1105C v2, Intel Core 3115C and Intel Pentium Processor B925C Specification Update .br 329460: Intel Atom Processor C2000 Product Family Specification Update .br 329475: Intel Atom Processor Z3600 and Z3700 Series Specification Update .br 329597: Intel Xeon Processor E7 v2 Product Family Specification Update .br 329671/600827: Intel Pentium Processor N3500-series, J2850, J2900 and Intel Celeron Processor N2900-series, N2800-series, J1800-series, J1900, J1750 Specification Update .br 329676: Intel Quark SoC X1000 Datasheet .br 329901/600834: Intel Atom Processor E3800 Specification Update .br 330785: Intel Xeon Processor E5 v3 Product Family Specification Update .br 330836: 5th Generation Intel Core Processor Family, Intel Core M Processor Family, Mobile Intel Pentium Processor Family, and Mobile Intel Celeron Processor Family Specification Update .br 330841: Intel Core i7 Processor Family for LGA2011-v3 Socket Specification Update .br 332054: Intel Xeon Processor D-1500 Product Family Specification Update .br 332067: Intel Atom Z8000 Processor Series Specification Update .br 332095: Intel N-Series Intel Pentium Processors and Intel Celeron Processors Specification Update .br 332317: Intel Xeon Processor E7 v3 Product Family Specification Update .br 332381: Mobile/Desktop 5th Generation Intel Core Processor Family Specification Update .br 332689: 6th Generation Intel Core Processor Family Specification Update .br 333133: Intel Xeon Processor E3-1200 v5 Product Family Specification Update .br 333811: Intel Xeon Processor E5-2600 v4 Product Family Specification Update .br 334165: Intel Xeon Processor E7-8800/4800 v4 Product Family Specification Update .br 334208: Intel Core i7 Processor Family for LGA2011-v3 Socket Specification Update .br 334525: Control-flow Enforcement Technology Preview .br 334646: Intel Xeon Phi Processor x200 Product Family Preliminary Specification Update .br 334663: 7th Generation Intel Processor Family Specification Update Supporting 7th Generation Intel Core Processor Families based on U/Y-Processor Line .br 334820: Intel Pentium and Celeron Processor N- and J- Series Specification Update .br 335252: 5-Level Paging and 5-Level EPT White Paper .br 335718/730694: Intel Xeon Processor E3-1200 v6 Product Family Specification Update .br 335864: Intel Celeron Processor J1800, J1900, N2807, and N2930 for Internet of Things Specification Update Addendum .br 335901: Intel Core X-Series Processor Family Specification Update .br 336065/613537: Intel Xeon Processor Scalable Family Specification Update .br 336345: Intel Atom Processor C3000 Product Family Specification Update .br 336466: 8th Generation Intel Processor Family for S-Processor Platforms Specification Update .br 336505: Intel Xeon Processor Scalable Family Specification Update .br 336562: Intel Pentium Silver and Intel Celeron Processors Specification Update .br 337346: 8th and 9th Generation Intel Core Processor Family Specification Update .br 336907: Intel Architecture Memory Encryption Technologies Specification .br 338014: Intel Xeon E-2100 and E-2200 Processor Family Specification Update .br 338025: 8th Generation Intel Core Processor Families Specification Update .br 338848: Second Generation Intel Xeon Scalable Processors Specification Update .br 338854: Intel Xeon D-2100 Processor Product Family Specification Update .br 341079: 10th Generation Intel Core Processor Families Specification Update .br 343754: Intel Trust Domain CPU Architectural Extensions .br 344425: Architecture Specification: Intel Trust Domain Extensions (Intel TDX) Module .br 346466: Intel Flexible Return and Event Delivery (FRED) Specification .br 355828: Intel Advanced Performance Extensions (Intel APX) Architecture Specification. .br 615213: 10th Generation Intel Core Processor Specification Update .br 631123: 11th Generation Intel Core Processor Family Specification Update .br 634808: 11th Generation Intel Core Processor Specification Update Supporting 11th Generation Intel Core Processor Families for S Platform, formerly known as Rocket Lake .br 634542: Intel Pentium Silver and Intel Celeron Processor Specification Update .br 634897: 3rd Generation Intel Xeon Scalable Processors, Codename Cooper Lake Specification Update .br 636674: Intel Atom x6000E Series, and Intel Pentium and Celeron N and J Series Processors for Internet of Things (IoT) Applications Specification Update - Public .br 637780: 3rd Gen Intel Xeon Scalable Processors, Codename Ice Lake Specification Update .br 682436: 12th Generation Intel Core Processor Specification Update Supporting 12th Generation Intel Core Processor for S Processor Line Platforms, formerly known as Alder Lake .br 709192: Intel Xeon E-2300 Processor Family Specification Update .br 714071: Intel Xeon D-2700 Processor Family Specification Update .br 743844: 13th Generation Intel Core Processors Datasheet, Volume 1 of 2 Supporting 13th Generation Intel Core Processor for S/P/PX/H/HX/U Processor Line Platforms, formerly known as Raptor Lake .br 759603: Intel Processor and Intel Core i3 N-Series Datasheet, Volume 1 of 2 .br 764616: Intel Processor and Intel Core i3 N-series Specification Update .br 772415: 4th Gen Intel Xeon Scalable Processors Codename Sapphire Rapids Specification Update .br 792254: Intel Core Ultra Processor Specification Update .br 793902: 5th Gen Intel Xeon Processor Scalable Family, Codename Emerald Rapids Specification Update .br 827538: Intel Core Ultra 200V Series Processors Specification Update .br 834774: Intel Core Ultra 200S Series Processors Specification Update .br Intel Microcode Update Guidance .br Branch History Injection and Intra-mode Branch Target Injection / CVE-2022-0001, CVE-2022-0002 / INTEL-SA-00598 .br Intel Transactional Synchronization Extensions (Intel TSX) Memory and Performance Monitoring Update for Intel Processors (Article ID 000059422) .br Retpoline: A Branch Target Injection Mitigation .br Special Register Buffer Data Sampling .RE Information on the CPUID instruction and on specific CPUs is available from the following documents from Advanced Micro Devices, Inc. , with the specified Publication Numbers: .RS .br 20734: AMD Processor Recognition Application Note .br 21266: AMD-K6 Processor Revision Guide Model 6 .br 21641: AMD-K6-2 Processor Revision Guide Model 8 .br 21846: AMD-K6 Processor Revision Guide Model 7 .br 22473: AMD-K6-III Processor Revision Guide Model 9 .br 23614: AMD Athlon Processor Model 4 Revision Guide .br 23865: AMD Duron Processor Model 3 Revision Guide .br 24332: AMD Athlon Processor Model 6 Revision Guide .br 24594: AMD64 Architecture Programmer's Manual Volume 3: General-Purpose and System Instructions .br 24806: AMD Duron Processor Model 7 Revision Guide .br 25481: CPUID Specification .br 25703: AMD Athlon Processor Model 8 Revision Guide .br 25759: Revision Guide for AMD Athlon 64 and AMD Opteron Processors .br 26094: BIOS and Kernel Developer's Guide for AMD Athlon 64 and AMD Opteron Processors .br 27532: AMD Athlon Processor Model 10 Revision Guide .br 31177H: AMD Geode NX Processors Data Book .br 31610: Revision Guide for AMD NPT Family 0Fh Processors .br 33234F: AMD Geode LX Processors Data Book .br 40332: AMD64 Architecture Programmer's Manual: Volumes 1-5 .br 41322: Revision Guide for AMD Family 10h Processors .br 41788: Revision Guide for AMD Family 11h Processors .br 44739: Revision Guide for AMD Family 12h Processors .br 47534: Revision Guide for AMD Family 14h Models 00h-0Fh Processors .br 48063: Revision Guide for AMD Family 15h Models 00h-0Fh Processors .br 48931: Revision Guide for AMD Family 15h Models 10h-1Fh Processors .br 51603: Revision Guide for AMD Family 15h Models 30h-3Fh Processors .br 51810: Revision Guide for AMD Family 16h Models 00h-0Fh Processors .br 53072: Revision Guide for AMD Family 16h Models 30h-3Fh Processors .br 54945: Processor Programming Reference (PPR) for AMD Family 17h Models 01h,0h, Revision B2 Processors .br 54945: Processor Programming Reference (PPR) for AMD Family 17h Models 01h,08h Revision B2 Processors .br 55370: Revision Guide for AMD Family 15h Models 70h-7Fh Processors .br 55449: Revision Guide for AMD Family 17h Models 00h-0Fh processors .br 55570-B1: Processor Programming Reference (PPR) for AMD Family 17h Model 18h, Revision B1 Processors .br 55766: Secure Encrypted Virtualization API Version 0.16 Technical Preview .br 55772-A1: Processor Programming Reference (PPR) for AMD Family 17h Model 20h, Revision A1 Processors .br 55898: Preliminary Processor Programming Reference (PPR) for AMD Family 19h Model 01h, Revision B1 Processors .br 56214: Processor Programming Reference (PPR) for AMD Family 19h Model 21h, Revision B0 Processors .br 56569: Processor Programming Reference (PPR) for AMD Family 19h Model 51h, Revision A1 Processors .br 55901: Preliminary Processor Programming Reference (PPR) for AMD Family 19h Model 11h, Revision B2 Processors .br 55922-A1: Processor Programming Reference (PPR) for AMD Family 17h Model 60h, Revision A1 Processors .br 55803: Preliminary Processor Programming Reference (PPR) for AMD Family 17h Model 31h, Revision B0 Processors .br 56176: Processor Programming Reference (PPR) for AMD Family 17h Model 71h, Revision B0 Processors .br 56375: AMD64 Technology Platform Quality of Service Extensions .br 57095: Revision Guide for AMD Family 19h Models 10h-1Fh Processors .br 57228: Processor Programming Reference (PPR) for AMD Family 19h Model A0h, Revision A2 Processors .br 57238: Processor Programming Reference (PPR) for AMD Family 1Ah Model 02h, Revision C1 Processors .br 57896: Processor Programming Reference (PPR) for AMD Family 1Ah Model 44h, Revision B0 Processors .br 58015: AMD EPYC 9004 Series Architecture Overview .br 58268: AMD EPYC 8004 Series Architecture Overview .br AMD64 Technology Indirect Branch Control Extension (White Paper), Revision 4.10.18 .br AMD64 Technology Speculative Store Bypass Disable (White Paper), Revision 5.21.18 .br Technical Guidance For Mitigating Branch Type Confusion (White Paper), Revision 2022-07-12 .RE Information on the CPUID instruction and on specific CPUs is available from the following documents from Transmeta Corporation : .RS .br Processor Recognition, 2002/05/07 .RE Information on the CPUID instruction and on specific CPUs is available from the following documents from Cyrix: .RS .br Application Note 112: Cyrix CPU Detection Guide .br Cyrix 6x86 Processor, Instruction Set .RE The linux kernel can be a source of information on CPUID flags, using X86_FEATURE_* definitions in arch/x86/include/asm/cpufeatures.h. Also, it can be used to learn about Intel microarchitectures in arch/x86/include/asm/intel-family.h. Information on generic hypervisor CPUID leaves is available from this proposal: . Information on KVM hypervisor CPUID leaves is available from the Linux kernel under Documentation/virtual/kvm/cpuid.txt. Information on XEN hypervisor CPUID leaves is deduced from source inspection, mainly from xen's include/public/arch-x86/cpuid.h and arch/x86/traps.c. Information on Microsoft hypervisor CPUID leaves is available from the following documents from Microsoft: and . Also, information is available from the following web sites: .RS .br .br .br .br .br .br .RE .SH AUTHOR Todd Allen cpuid-20250316/cpuinfo2cpuid0000777001234300001440000000631013020030450014422 0ustar toddusers#!/usr/bin/perl use autodie; use strict; use utf8; use warnings qw(all); use Getopt::Long; use Pod::Usage; my $vendor = ''; my $family = ''; my $model = ''; my $stepping = ''; my $help; GetOptions( q(help) => \$help, q(vendor=s) => \$vendor, q(family=i) => \$family, q(model=i) => \$model, q(stepping=i) => \$stepping, ) or pod2usage(q(-verbose) => 1); pod2usage(q(-verbose) => 1) if $help; if ( $vendor ne '' or $family ne '' or $model ne '' or $stepping ne '' ) { if ( $vendor ne 'GenuineIntel' and $vendor ne 'AuthenticAMD' ) { print STDERR "vendor has to be either \"GenuineIntel\" or \"AuthenticAMD\"\n"; pod2usage(q(-verbose) => 1); } if ( $vendor eq '' or $family eq '' or $model eq '' or $stepping eq '' ) { print STDERR "When specifying input manually all input values \"vendor, family, model and stepping\" has to be specified\n"; pod2usage(q(-verbose) => 1); } } else { # Read cpuinfo from STDIN while () { if (/^vendor_id\s*: (.*)$/) { $vendor = $1 } if (/^cpu family\s*: (.*)$/) { $family = $1 } if (/^model\s*: (.*)$/) { $model = $1 } if (/^stepping\s*: (.*)$/) { $stepping = $1 } } } my $xfamily = int($family / 16); $family = $family % 16; my $xmodel = int($model / 16); $model = $model % 16; my $eax = ( (($xfamily & 0xff) << 20) + (($xmodel & 0xf) << 16) + (($family & 0xf) << 8) + (($model & 0xf) << 4) + (($stepping & 0xf) << 0)); printf("CPU:\n"); if ($vendor eq "GenuineIntel") { printf(" 0x%08x 0x%02x: eax=0x%08x ebx=0x%08x ecx=0x%08x edx=0x%08x\n", 0, 0, 1, 0x756e6547, 0x6c65746e, 0x49656e69); } elsif ($vendor eq "AuthenticAMD") { printf(" 0x%08x 0x%02x: eax=0x%08x ebx=0x%08x ecx=0x%08x edx=0x%08x\n", 0, 0, 1, 0x68747541, 0x444d4163, 0x69746e65); } printf(" 0x%08x 0x%02x: eax=0x%08x ebx=0x%08x ecx=0x%08x edx=0x%08x\n", 1, 0, $eax, 0, 0, 0); __END__ =pod =head1 NAME cpuinfo2cpuid =head1 SYNOPSIS cpuinfo2cpuid or cpuinfo2cpuid -help or cpuinfo2cpuid -vendor= -family= -model= -stepping= =head1 DESCRIPTION Expects /proc/cpuinfo data on stdin and converts it to cpuid-like HEX data structure suitable as the input for cpuid -f utility. Alternatively, user can specify CPU vendor, family, model and stepping on the command line. =head1 OPTIONS =over 4 =item -help Displays a brief help message. =item -vendor CPU vendor. Can be either GenuineIntel or AuthenticAMD. =item -family CPU family in decimal notation. =item -model CPU model in decimal notation. =item -stepping CPU stepping in decimal notation. =item -help Displays a brief help message. =back =head1 LIMITATIONS Only Intel & AMD cpuinfo data are supported at the moment. =head1 EXAMPLES cpuinfo2cpuid < /proc/cpuinfo | cpuid -f - | grep '(synth)' Specifying CPU vendor, family, model and stepping on command line cpuinfo2cpuid.pl -vendor=GenuineIntel -family=6 -model=58 -stepping=9 | cpuid -f - | grep '(synth)' =head1 AUTHOR Todd Allen , Jirka Hladky =cut cpuid-20250316/cpuid.c0000666001234300001440000220035314764565627013242 0ustar toddusers/* ** cpuid dumps CPUID information for each CPU. ** Copyright 2003,2004,2005,2006,2010,2011,2012,2013,2014,2015,2016,2017,2018, ** 2020,2021,2022,2023,2024,2025 by Todd Allen. ** ** This program is free software; you can redistribute it and/or ** modify it under the terms of the GNU General Public License ** as published by the Free Software Foundation; either version 2 ** of the License, or (at your option) any later version. ** ** This program is distributed in the hope that it will be useful, ** but WITHOUT ANY WARRANTY; without even the implied warranty of ** MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the ** GNU General Public License for more details. ** ** You should have received a copy of the GNU General Public License ** along with this program; if not, write to the Free Software Foundation, Inc., ** 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA. */ // MSR_CPUID_table* is a table that appears in Intel document 325462, "Intel 64 // and IA-32 Architectures Software Developer's Manual Combined Volumes: 1, 2A, // 2B, 2C, 2D, 3A, 3B, 3C, 3D, and 4" (the name changes from version to version // as more volumes are added). The table moves around from version to version, // but in version 071US, was in "Volume 4: Model-Specific Registers", Table 2-1: // "CPUID Signature Values of DisplayFamily_DisplayModel". // ILPMDF* is the Intel Linux Processor Microcode Data Files, which provides // microcode updates. Its purpose is not to list CPUID values, but it does so // to help identify CPUs for each microcode update. The identifications are in: // releasenote.md // MRG* is a table that forms the bulk of Intel Microcode Revision Guidance (or // Microcode Update Guidance). Its purpose is not to list CPUID values, but // it does so, and sometimes lists values that appear nowhere else. // SSG* is the Software Security Guidance Processors Affected table. It // replaces the MRG* circa 2022. Again, its purpose is not to list CPUID // values, but it does so, and sometimes lists values that appear nowhere else. // It appears to be available only in online HTML form: // https://www.intel.com/content/www/us/en/developer/topic-technology/software-security-guidance/processors-affected-consolidated-product-cpu-model.html // LX* indicates features that I have seen no documentation for, but which are // used by the Linux kernel (which is good evidence that they're correct). // The "hook" to find these generally is an X86_FEATURE_* flag in: // arch/x86/include/asm/cpufeatures.h // For (synth) and (uarch synth) decoding, it often indicates // family/model/stepping values which are documented nowhere else. These // usually can be found in: // arch/x86/include/asm/intel-family.h // Coreboot* indicates (synth) or (uarch synth) decoding for which I have seen // no documentation, but which is used by coreboot, BIOS replacement software. // The core information is in: // src/include/cpu/intel/cpu_ids.h // src/soc/intel/common/block/include/intelblocks/mp_init.h // src/soc/intel/*/include/soc/cpu.h (old) // And strings, for the less obvious cases, are in: // src/soc/intel/*/bootblock/report_platform.c // DPTF* indicates (synth) or (uarch synth) decoding for which I have seen // no documentation, but which is used by Intel DPTF, Intel Dynamic Tuning for // Chromium OS. The core information is in: // Common/esif_ccb_cpuid.h // Xen* indicates features that I have seen no documentation for, but which are // used by the Xen hypervisor. They are listed in: // xen/include/public/arch-x86/cpuid.h // tools/libxl/libxl_cpuid.c (old) // Qemu* indicates features that I have seen no documentation for, but which are // used by the Qemu hypervisor. They are listed in: // target/i386/cpu.c // Google_cpu_features* indicates features that I have seen no documentation for, // but which are used by the Google cpu_features library. They are listed in: // include/cpuinfo_x86.h // src/impl_x86__base_implementation.inl #if defined(__linux__) #define USE_CPUID_MODULE #endif #if defined(__linux__) #define USE_KERNEL_SCHED_SETAFFINITY #elif defined(__sun) #define USE_PROCESSOR_BIND #elif defined(__FreeBSD__) #define USE_CPUSET_SETAFFINITY #elif defined(__NetBSD__) #define USE_SCHED_SETAFFINITY_NP #elif defined(__HAIKU__) #define USE_PTHREAD_SETAFFINITY_NP #else // Default is sched_setaffinity #endif #if defined(__GNUC__) && defined(__GNUC_MINOR__) && defined(__GNUC_PATCHLEVEL__) #if __GNUC__ * 10000 + __GNUC_MINOR__ * 100 + __GNUC_PATCHLEVEL__ >= 40300 #define USE_CPUID_COUNT #endif #endif #if defined(__GNUC__) && defined(__GNUC_MINOR__) && defined(__GNUC_PATCHLEVEL__) #if __GNUC__ * 10000 + __GNUC_MINOR__ * 100 + __GNUC_PATCHLEVEL__ >= 30400 #define USE_BUILTIN_CLZL #endif #endif #if defined(__GNUC__) #define UNUSED __attribute((unused)) #else #define UNUSED #endif #ifndef _GNU_SOURCE #define _GNU_SOURCE #endif #define _LARGEFILE64_SOURCE #include #include #include #include #include #include #include #include #include #include #include #ifdef USE_CPUID_MODULE #include #endif #ifdef USE_CPUID_COUNT #include #endif #if defined(USE_KERNEL_SCHED_SETAFFINITY) #include #include #elif defined(USE_PROCESSOR_BIND) #include #include #include #include #elif defined(USE_SCHED_SETAFFINITY_NP) #include #elif defined(USE_PTHREAD_SETAFFINITY_NP) #include #else #include #include #endif typedef int boolean; #define TRUE 1 #define FALSE 0 typedef char* string; typedef const char* cstring; typedef const char* const ccstring; #define SAME 0 #define STR(x) #x #define XSTR(x) STR(x) #ifndef MAX #define MAX(l,r) ((l) > (r) ? (l) : (r)) #endif #define LENGTH(array) (sizeof(array) / sizeof(array[0])) #define BPI 32 #define POWER2(power) \ (1 << (power)) #define RIGHTMASK(width) \ (((width) >= BPI) ? ~0 : POWER2(width)-1) #define BIT_EXTRACT_LE(value, start, after) \ (((value) & RIGHTMASK(after)) >> start) #define WORD_EAX 0 #define WORD_EBX 1 #define WORD_ECX 2 #define WORD_EDX 3 #define WORD_NUM 4 const char* program = NULL; static boolean strregexp(const char* haystack, const char* needle) { regex_t re; int status; status = regcomp(&re, needle, REG_NOSUB); if (status != 0) { size_t size = regerror(status, &re, NULL, 0); char* buffer = malloc(size + 1); if (buffer == NULL || size + 1 == 0) { fprintf(stderr, "%s: out of memory (strregexp 1)\n", program); exit(1); } regerror(status, &re, buffer, size); fprintf(stderr, "%s: cannot regcomp \"%s\"; error = %s\n", program, needle, buffer); exit(1); } status = regexec(&re, haystack, 0, NULL, 0); if (status != 0 && status != REG_NOMATCH) { size_t size = regerror(status, &re, NULL, 0); char* buffer = malloc(size + 1); if (buffer == NULL || size + 1 == 0) { fprintf(stderr, "%s: out of memory (strregexp 2)\n", program); exit(1); } regerror(status, &re, buffer, size); fprintf(stderr, "%s: cannot regexec string \"%s\" with regexp \"%s\";" " error = %s\n", program, haystack, needle, buffer); exit(1); } regfree(&re); return (status == 0); } typedef struct { ccstring name; unsigned int low_bit; unsigned int high_bit; ccstring* images; } named_item; #define NIL_IMAGES (ccstring*)NULL /* rawValue shown as integer */ #define MINUS1_IMAGES (ccstring*)1 /* rawValue = actualValue-1 */ #define X2_IMAGES (ccstring*)2 /* rawValue = actualValue*2 */ #define MINUS24_IMAGES (ccstring*)3 /* rawValue = actualValue-24 */ #define D4_IMAGES (ccstring*)4 /* rawValue = actualValue/4 */ static unsigned int get_max_len (named_item names[], unsigned int length) { unsigned int result = 0; unsigned int i; for (i = 0; i < length; i++) { result = MAX(result, strlen(names[i].name)); } return result; } static void print_names(unsigned int value, named_item names[], unsigned int length, unsigned int max_len) { unsigned int i; if (max_len == 0) { max_len = get_max_len(names, length); } for (i = 0; i < length; i++) { unsigned int field = BIT_EXTRACT_LE(value, names[i].low_bit, names[i].high_bit + 1); if (names[i].images == D4_IMAGES) { printf(" %-*s = 0x%0llx (%llu)\n", max_len, names[i].name, (unsigned long long)field * 4ULL, (unsigned long long)field * 4ULL); } else if (names[i].images == X2_IMAGES) { printf(" %-*s = %.1f\n", max_len, names[i].name, (double)field / 2.0); } else if (names[i].images == MINUS24_IMAGES) { printf(" %-*s = 0x%0llx (%llu)\n", max_len, names[i].name, (unsigned long long)field + 24ULL, (unsigned long long)field + 24ULL); } else if (names[i].images == MINUS1_IMAGES) { printf(" %-*s = 0x%0llx (%llu)\n", max_len, names[i].name, (unsigned long long)field + 1ULL, (unsigned long long)field + 1ULL); } else if (names[i].images == NIL_IMAGES || names[i].images[field] == NULL) { printf(" %-*s = 0x%0x (%u)\n", max_len, names[i].name, field, field); } else { printf(" %-*s = %s\n", max_len, names[i].name, names[i].images[field]); } } } static ccstring bools[] = { "false", "true" }; typedef enum { VENDOR_UNKNOWN, VENDOR_INTEL, VENDOR_AMD, VENDOR_CYRIX, VENDOR_VIA, VENDOR_TRANSMETA, VENDOR_UMC, VENDOR_NEXGEN, VENDOR_RISE, VENDOR_SIS, VENDOR_NSC, VENDOR_VORTEX, VENDOR_RDC, VENDOR_HYGON, VENDOR_ZHAOXIN, } vendor_t; typedef enum { HYPERVISOR_UNKNOWN, HYPERVISOR_VMWARE, HYPERVISOR_XEN, HYPERVISOR_KVM, HYPERVISOR_MICROSOFT, // a.k.a Hyper-V, Viridian HYPERVISOR_ACRN, } hypervisor_t; #define MaskF(v) ((v) & 0x0ff00f00) #define MaskM(v) ((v) & 0x000f00f0) #define MaskMm(v) ((v) & 0x000f0080) // extended model + high bit of model: 0 or 8: identifies AMD Zen model #define MaskFM(v) ((v) & 0x0fff0ff0) #define MaskFMm(v) ((v) & 0x0fff0f80) // extended model + high bit of model: 0 or 8: identifies AMD Zen model #define MaskFMS(v) ((v) & 0x0fff0fff) #define MaskTF(v) ((v) & 0x0ff03f00) #define MaskTFM(v) ((v) & 0x0fff3ff0) #define MaskTFMS(v) ((v) & 0x0fff3fff) #define ShftT(v) ((v) << 12) #define ShftF(v) ((v) << 8) #define ShftM(v) ((v) << 4) #define ShftS(v) (v) #define ShftXF(v) ((v) << 20) #define ShftXM(v) ((v) << 16) // These two use val_1_ebx, in contrast to all the others that use val_1_eax. #define MaskB(v) ((v) & 0x000000ff) #define ShftB(v) (v) #define ShftFM(xf,f,xm,m) (ShftXF(xf) + ShftF(f) + ShftXM(xm) + ShftM(m)) #define ShftFMS(xf,f,xm,m,s) (ShftXF(xf) + ShftF(f) + ShftXM(xm) + ShftM(m) + ShftS(s)) #define START \ if (0) #define F(xf,f,...) \ else if (MaskF(val) == ShftXF(xf) +ShftF(f) ) ACT(__VA_ARGS__) #define FM(xf,f,xm,m,...) \ else if (MaskFM(val) == ShftXF(xf)+ShftXM(xm)+ShftF(f)+ShftM(m) ) ACT(__VA_ARGS__) #define FMm(xf,f,xm,m,...) \ else if (MaskFMm(val) == ShftXF(xf)+ShftXM(xm)+ShftF(f)+ShftM((m)&0x8) ) ACT(__VA_ARGS__) #define FMS(xf,f,xm,m,s,...) \ else if (MaskFMS(val) == ShftXF(xf)+ShftXM(xm)+ShftF(f)+ShftM(m)+ShftS(s) ) ACT(__VA_ARGS__) #define TF(t,xf,f,...) \ else if (MaskTF(val) == ShftT(t)+ShftXF(xf) +ShftF(f) ) ACT(__VA_ARGS__) #define TFM(t,xf,f,xm,m,...) \ else if (MaskTFM(val) == ShftT(t)+ShftXF(xf)+ShftXM(xm)+ShftF(f)+ShftM(m) ) ACT(__VA_ARGS__) #define TFMS(t,xf,f,xm,m,s,...) \ else if (MaskTFMS(val) == ShftT(t)+ShftXF(xf)+ShftXM(xm)+ShftF(f)+ShftM(m)+ShftS(s) ) ACT(__VA_ARGS__) #define FQ(xf,f,q,...) \ else if (MaskF(val) == ShftXF(xf) +ShftF(f) && (stash) && (q)) ACT(__VA_ARGS__) #define FMQ(xf,f,xm,m,q,...) \ else if (MaskFM(val) == ShftXF(xf)+ShftXM(xm)+ShftF(f)+ShftM(m) && (stash) && (q)) ACT(__VA_ARGS__) #define FMmQ(xf,f,xm,m,q,...) \ else if (MaskFMm(val) == ShftXF(xf)+ShftXM(xm)+ShftF(f)+ShftM((m)&0x8) && (stash) && (q)) ACT(__VA_ARGS__) #define FMSQ(xf,f,xm,m,s,q,...) \ else if (MaskFMS(val) == ShftXF(xf)+ShftXM(xm)+ShftF(f)+ShftM(m)+ShftS(s) && (stash) && (q)) ACT(__VA_ARGS__) #define DEFAULT(...) \ else ACT(__VA_ARGS__) #define FALLBACK(...) \ else __VA_ARGS__ // Synth_Family reflects AMD's "Family" definition: // the sum of the extended family and basic family #define Synth_Family(value) \ (BIT_EXTRACT_LE(value, 20, 28) \ + BIT_EXTRACT_LE(value, 8, 12)) // Synth_Model reflects AMD's "Model" definition: // the bitwise catenation of the extended model and basic model #define Synth_Model(value) \ ((BIT_EXTRACT_LE(value, 16, 20) << 4) \ + BIT_EXTRACT_LE(value, 4, 8)) // This enum combines the topological layers from both Intel & AMD. enum Cotopo { Smt, Core, Cu, Module, Tile, Die, DieGrp, Pkg, NumCotopos, Invalid = NumCotopos, }; #define V2_TOPO_NUM 7 static unsigned int v2TopoToCotopo[V2_TOPO_NUM] = { /* invalid (0) => */ Invalid, /* thread (1) => */ Smt, /* core (2) => */ Core, /* module (3) => */ Module, /* tile (4) => */ Tile, /* die (5) => */ Die, /* die group (6) => */ DieGrp }; typedef struct { vendor_t vendor; boolean saw_4; boolean saw_b; boolean saw_1f; boolean saw_8000001e; unsigned int val_0_eax; unsigned int val_1_eax; unsigned int val_1_ebx; unsigned int val_1_ecx; unsigned int val_1_edx; unsigned int val_4_eax; unsigned int val_7_1_edx; unsigned int val_b_eax[2]; unsigned int val_b_ebx[2]; unsigned int val_b_edx; unsigned int val_1a_0_eax; unsigned int val_1f_eax[V2_TOPO_NUM]; unsigned int val_1f_ebx[V2_TOPO_NUM]; unsigned int val_1f_ecx[V2_TOPO_NUM]; unsigned int val_1f_edx; unsigned int val_80000001_eax; unsigned int val_80000001_ebx; unsigned int val_80000001_ecx; unsigned int val_80000001_edx; unsigned int val_80000008_ecx; unsigned int val_8000001e_eax; unsigned int val_8000001e_ebx; unsigned int transmeta_proc_rev; char brand[48+1]; char transmeta_info[64+1]; char override_brand[48*2+1]; char soc_brand[48+1]; hypervisor_t hypervisor; struct mp { const char* method; unsigned int count[NumCotopos]; } mp; struct br { boolean mobile; struct /* Intel */ { boolean celeron; boolean core; boolean pentium; boolean atom; boolean xeon_mp; boolean xeon; boolean pentium_m; boolean pentium_d; boolean extreme; boolean generic; boolean scalable; boolean u_line; boolean y_line; boolean g_line; boolean i_8000; boolean i_10000; boolean cc150; boolean core_ultra; }; struct /* AMD */ { boolean athlon_lv; boolean athlon_xp; boolean duron; boolean athlon; boolean sempron; boolean phenom; boolean series; boolean a_series; boolean c_series; boolean e_series; boolean g_series; boolean r_series; boolean z_series; boolean geode; boolean turion; boolean neo; boolean athlon_fx; boolean athlon_mp; boolean duron_mp; boolean opteron; boolean fx; boolean firepro; boolean ultra; boolean t_suffix; boolean ryzen; boolean threadripper; boolean epyc; boolean epyc_3000; boolean montage; boolean embedded; boolean embedded_V; boolean embedded_R; int cores; }; struct /* Cyrix */ { boolean mediagx; }; struct /* VIA */ { boolean c7; boolean c7m; boolean c7d; boolean eden; boolean zhaoxin; }; } br; struct bri { boolean desktop_pentium; boolean desktop_celeron; boolean mobile_pentium; boolean mobile_pentium_m; boolean mobile_celeron; boolean xeon_mp; boolean xeon; } bri; /* ==============implications============== */ /* PII (F6, M5) PIII (F6, M7) */ /* ---------------------- --------------- */ boolean L2_4w_1Mor2M; /* Xeon Xeon */ boolean L2_4w_512K; /* normal, Mobile or Xeon normal or Xeon */ boolean L2_4w_256K; /* Mobile - */ boolean L2_8w_1Mor2M; /* - Xeon */ boolean L2_8w_512K; /* - normal */ boolean L2_8w_256K; /* - normal or Xeon */ /* none */ /* Celeron - */ boolean L2_2M; /* Nocona lacks, Irwindale has */ /* Conroe has more, Allendale has this */ boolean L2_6M; /* Yorkfield C1/E0 has this, M1/R0 has less */ boolean L3; /* Cranford lacks, Potomac has */ boolean L2_256K; /* Barton has more, Thorton has this */ boolean L2_512K; /* Toledo has more, Manchester E6 has this */ } code_stash_t; #define NIL_STASH { VENDOR_UNKNOWN, \ FALSE, FALSE, FALSE, FALSE, \ 0, 0, 0, 0, 0, 0, 0, \ { 0, 0 }, \ { 0, 0 }, \ 0, \ 0, \ { 0, 0, 0, 0, 0, 0, 0 }, \ { 0, 0, 0, 0, 0, 0, 0 }, \ { 0, 0, 0, 0, 0, 0, 0 }, \ 0, \ 0, 0, 0, 0, 0, 0, 0, 0, \ "", "", "", "", \ HYPERVISOR_UNKNOWN, \ { NULL, { 0, 0, 0, 0, 0, 0, 0, 0 } }, \ { FALSE, \ { FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, \ FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, \ FALSE, FALSE, FALSE, FALSE }, \ { FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, \ FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, \ FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, \ FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, \ FALSE, FALSE, FALSE, FALSE, 0 }, \ { FALSE }, \ { FALSE, FALSE, FALSE, FALSE, FALSE } }, \ { FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, FALSE }, \ FALSE, FALSE, FALSE, FALSE, FALSE, FALSE, \ FALSE, FALSE, FALSE, \ FALSE, FALSE } typedef struct { boolean raw; boolean simple; boolean debug; } print_opts_t; #define NIL_PRINT_OPTS { FALSE, FALSE, FALSE } static void decode_amd_model(const code_stash_t* stash, const char** brand_pre, const char** brand_post, char proc[34]) { *brand_pre = NULL; *brand_post = NULL; *proc = '\0'; if (stash == NULL) return; if (MaskF(stash->val_1_eax) == ShftXF(0) + ShftF(15) && MaskM(stash->val_1_eax) < ShftXM(4) + ShftM(0)) { /* ** Algorithm from: ** Revision Guide for AMD Athlon 64 and AMD Opteron Processors ** (25759 Rev 3.79), Constructing the Processor Name String. ** But using only the Processor numbers. */ unsigned int bti; unsigned int NN; if (MaskB(stash->val_1_ebx) != 0) { bti = BIT_EXTRACT_LE(MaskB(stash->val_1_ebx), 5, 8) << 2; NN = BIT_EXTRACT_LE(MaskB(stash->val_1_ebx), 0, 5); } else if (BIT_EXTRACT_LE(stash->val_80000001_ebx, 0, 12) != 0) { bti = BIT_EXTRACT_LE(stash->val_80000001_ebx, 6, 12); NN = BIT_EXTRACT_LE(stash->val_80000001_ebx, 0, 6); } else { return; } #define XX (22 + NN) #define YY (38 + 2*NN) #define ZZ (24 + NN) #define TT (24 + NN) #define RR (45 + 5*NN) #define EE ( 9 + NN) switch (bti) { case 0x04: *brand_pre = "AMD Athlon(tm) 64"; sprintf(proc, "Processor %02d00+", XX); break; case 0x05: *brand_pre = "AMD Athlon(tm) 64 X2 Dual Core"; sprintf(proc, "Processor %02d00+", XX); break; case 0x06: *brand_pre = "AMD Athlon(tm) 64"; sprintf(proc, "FX-%02d", ZZ); *brand_post = "Dual Core"; break; case 0x08: *brand_pre = "AMD Athlon(tm) 64"; sprintf(proc, "Processor %02d00+", XX); break; case 0x09: *brand_pre = "AMD Athlon(tm) 64"; sprintf(proc, "Processor %02d00+", XX); break; case 0x0a: *brand_pre = "AMD Turion(tm) Mobile Technology"; sprintf(proc, "ML-%02d", XX); break; case 0x0b: *brand_pre = "AMD Turion(tm) Mobile Technology"; sprintf(proc, "MT-%02d", XX); break; case 0x0c: case 0x0d: *brand_pre = "AMD Opteron(tm)"; sprintf(proc, "Processor 1%02d", YY); break; case 0x0e: *brand_pre = "AMD Opteron(tm)"; sprintf(proc, "Processor 1%02d HE", YY); break; case 0x0f: *brand_pre = "AMD Opteron(tm)"; sprintf(proc, "Processor 1%02d EE", YY); break; case 0x10: case 0x11: *brand_pre = "AMD Opteron(tm)"; sprintf(proc, "Processor 2%02d", YY); break; case 0x12: *brand_pre = "AMD Opteron(tm)"; sprintf(proc, "Processor 2%02d HE", YY); break; case 0x13: *brand_pre = "AMD Opteron(tm)"; sprintf(proc, "Processor 2%02d EE", YY); break; case 0x14: case 0x15: *brand_pre = "AMD Opteron(tm)"; sprintf(proc, "Processor 8%02d", YY); break; case 0x16: *brand_pre = "AMD Opteron(tm)"; sprintf(proc, "Processor 8%02d HE", YY); break; case 0x17: *brand_pre = "AMD Opteron(tm)"; sprintf(proc, "Processor 8%02d EE", YY); break; case 0x18: *brand_pre = "AMD Athlon(tm) 64"; sprintf(proc, "Processor %02d00+", EE); break; case 0x1d: *brand_pre = "Mobile AMD Athlon(tm) XP-M"; sprintf(proc, "Processor %02d00+", XX); break; case 0x1e: *brand_pre = "Mobile AMD Athlon(tm) XP-M"; sprintf(proc, "Processor %02d00+", XX); break; case 0x20: *brand_pre = "AMD Athlon(tm) XP"; sprintf(proc, "Processor %02d00+", XX); break; case 0x21: case 0x23: *brand_pre = "Mobile AMD Sempron(tm)"; sprintf(proc, "Processor %02d00+", TT); break; case 0x22: case 0x26: *brand_pre = "AMD Sempron(tm)"; sprintf(proc, "Processor %02d00+", TT); break; case 0x24: *brand_pre = "AMD Athlon(tm) 64"; sprintf(proc, "FX-%02d", ZZ); break; case 0x29: *brand_pre = "Dual Core AMD Opteron(tm)"; sprintf(proc, "Processor 1%02d SE", RR); break; case 0x2a: *brand_pre = "Dual Core AMD Opteron(tm)"; sprintf(proc, "Processor 2%02d SE", RR); break; case 0x2b: *brand_pre = "Dual Core AMD Opteron(tm)"; sprintf(proc, "Processor 8%02d SE", RR); break; case 0x2c: case 0x2d: case 0x38: case 0x3b: *brand_pre = "Dual Core AMD Opteron(tm)"; sprintf(proc, "Processor 1%02d", RR); break; case 0x30: case 0x31: case 0x39: case 0x3c: *brand_pre = "Dual Core AMD Opteron(tm)"; sprintf(proc, "Processor 2%02d", RR); break; case 0x34: case 0x35: case 0x3a: case 0x3d: *brand_pre = "Dual Core AMD Opteron(tm)"; sprintf(proc, "Processor 8%02d", RR); break; case 0x2e: *brand_pre = "Dual Core AMD Opteron(tm)"; sprintf(proc, "Processor 1%02d HE", RR); break; case 0x2f: *brand_pre = "Dual Core AMD Opteron(tm)"; sprintf(proc, "Processor 1%02d EE", RR); break; case 0x32: *brand_pre = "Dual Core AMD Opteron(tm)"; sprintf(proc, "Processor 2%02d HE", RR); break; case 0x33: *brand_pre = "Dual Core AMD Opteron(tm)"; sprintf(proc, "Processor 2%02d EE", RR); break; case 0x36: *brand_pre = "Dual Core AMD Opteron(tm)"; sprintf(proc, "Processor 8%02d HE", RR); break; case 0x37: *brand_pre = "Dual Core AMD Opteron(tm)"; sprintf(proc, "Processor 8%02d EE", RR); break; } #undef XX #undef YY #undef ZZ #undef TT #undef RR #undef EE } else if (MaskF(stash->val_1_eax) == ShftXF(0) + ShftF(15) && MaskM(stash->val_1_eax) >= ShftXM(4) + ShftM(0)) { /* ** Algorithm from: ** Revision Guide for AMD NPT Family 0Fh Processors (33610 Rev 3.46), ** Constructing the Processor Name String. ** But using only the Processor numbers. */ unsigned int bti; unsigned int pwrlmt; unsigned int NN; unsigned int pkgtype; unsigned int cmpcap; pwrlmt = ((BIT_EXTRACT_LE(stash->val_80000001_ebx, 6, 9) << 1) + BIT_EXTRACT_LE(stash->val_80000001_ebx, 14, 15)); bti = BIT_EXTRACT_LE(stash->val_80000001_ebx, 9, 14); NN = ((BIT_EXTRACT_LE(stash->val_80000001_ebx, 15, 16) << 5) + BIT_EXTRACT_LE(stash->val_80000001_ebx, 0, 5)); pkgtype = BIT_EXTRACT_LE(stash->val_80000001_eax, 4, 6); cmpcap = ((BIT_EXTRACT_LE(stash->val_80000008_ecx, 0, 8) > 0) ? 0x1 : 0x0); #define RR (NN - 1) #define PP (26 + NN) #define TT (15 + cmpcap*10 + NN) #define ZZ (57 + NN) #define YY (29 + NN) #define PKGTYPE(pkgtype) ((pkgtype) << 11) #define CMPCAP(cmpcap) ((cmpcap) << 9) #define BTI(bti) ((bti) << 4) #define PWRLMT(pwrlmt) (pwrlmt) switch (PKGTYPE(pkgtype) + CMPCAP(cmpcap) + BTI(bti) + PWRLMT(pwrlmt)) { /* Table 7: Name String Table for F (1207) and Fr3 (1207) Processors */ case PKGTYPE(1) + CMPCAP(0) + BTI(1) + PWRLMT(2): *brand_pre = "AMD Opteron(tm)"; sprintf(proc, "Processor 22%02d EE", RR); break; case PKGTYPE(1) + CMPCAP(1) + BTI(1) + PWRLMT(2): *brand_pre = "Dual-Core AMD Opteron(tm)"; sprintf(proc, "Processor 22%02d EE", RR); break; case PKGTYPE(1) + CMPCAP(1) + BTI(0) + PWRLMT(2) : *brand_pre = "Dual-Core AMD Opteron(tm)"; sprintf(proc, "Processor 12%02d EE", RR); break; case PKGTYPE(1) + CMPCAP(1) + BTI(0) + PWRLMT(6): *brand_pre = "Dual-Core AMD Opteron(tm)"; sprintf(proc, "Processor 12%02d HE", RR); break; case PKGTYPE(1) + CMPCAP(1) + BTI(1) + PWRLMT(6): *brand_pre = "Dual-Core AMD Opteron(tm)"; sprintf(proc, "Processor 22%02d HE", RR); break; case PKGTYPE(1) + CMPCAP(1) + BTI(1) + PWRLMT(10): *brand_pre = "Dual-Core AMD Opteron(tm)"; sprintf(proc, "Processor 22%02d", RR); break; case PKGTYPE(1) + CMPCAP(1) + BTI(1) + PWRLMT(12): *brand_pre = "Dual-Core AMD Opteron(tm)"; sprintf(proc, "Processor 22%02d SE", RR); break; case PKGTYPE(1) + CMPCAP(1) + BTI(4) + PWRLMT(2): *brand_pre = "Dual-Core AMD Opteron(tm)"; sprintf(proc, "Processor 82%02d EE", RR); break; case PKGTYPE(1) + CMPCAP(1) + BTI(4) + PWRLMT(6): *brand_pre = "Dual-Core AMD Opteron(tm)"; sprintf(proc, "Processor 82%02d HE", RR); break; case PKGTYPE(1) + CMPCAP(1) + BTI(4) + PWRLMT(10): *brand_pre = "Dual-Core AMD Opteron(tm)"; sprintf(proc, "Processor 82%02d", RR); break; case PKGTYPE(1) + CMPCAP(1) + BTI(4) + PWRLMT(12): *brand_pre = "Dual-Core AMD Opteron(tm)"; sprintf(proc, "Processor 82%02d SE", RR); break; case PKGTYPE(1) + CMPCAP(1) + BTI(6) + PWRLMT(14): *brand_pre = "AMD Athlon(tm) 64"; sprintf(proc, "FX-%02d", ZZ); break; /* Table 8: Name String Table for AM2 and ASB1 Processors */ case PKGTYPE(3) + CMPCAP(0) + BTI(1) + PWRLMT(5): *brand_pre = "AMD Sempron(tm)"; sprintf(proc, "Processor LE-1%02d0", RR); break; case PKGTYPE(3) + CMPCAP(0) + BTI(2) + PWRLMT(6): *brand_pre = "AMD Athlon(tm)"; sprintf(proc, "Processor LE-1%02d0", ZZ); break; case PKGTYPE(3) + CMPCAP(0) + BTI(3) + PWRLMT(6): *brand_pre = "AMD Athlon(tm)"; sprintf(proc, "Processor 1%02d0B", ZZ); break; case PKGTYPE(3) + CMPCAP(0) + BTI(4) + PWRLMT(1): case PKGTYPE(3) + CMPCAP(0) + BTI(4) + PWRLMT(2): case PKGTYPE(3) + CMPCAP(0) + BTI(4) + PWRLMT(3): case PKGTYPE(3) + CMPCAP(0) + BTI(4) + PWRLMT(4): case PKGTYPE(3) + CMPCAP(0) + BTI(4) + PWRLMT(5): case PKGTYPE(3) + CMPCAP(0) + BTI(4) + PWRLMT(8): *brand_pre = "AMD Athlon(tm) 64"; sprintf(proc, "Processor %02d00+", TT); break; case PKGTYPE(3) + CMPCAP(0) + BTI(5) + PWRLMT(2): *brand_pre = "AMD Sempron(tm)"; sprintf(proc, "Processor %02d50p", RR); break; case PKGTYPE(3) + CMPCAP(0) + BTI(6) + PWRLMT(4): case PKGTYPE(3) + CMPCAP(0) + BTI(6) + PWRLMT(8): *brand_pre = "AMD Sempron(tm)"; sprintf(proc, "Processor %02d00+", TT); break; case PKGTYPE(3) + CMPCAP(0) + BTI(7) + PWRLMT(1): case PKGTYPE(3) + CMPCAP(0) + BTI(7) + PWRLMT(2): *brand_pre = "AMD Sempron(tm)"; sprintf(proc, "Processor %02d0U", TT); break; case PKGTYPE(3) + CMPCAP(0) + BTI(8) + PWRLMT(2): case PKGTYPE(3) + CMPCAP(0) + BTI(8) + PWRLMT(3): *brand_pre = "AMD Athlon(tm)"; sprintf(proc, "Processor %02d50e", TT); break; case PKGTYPE(3) + CMPCAP(0) + BTI(9) + PWRLMT(2): *brand_pre = "AMD Athlon(tm) Neo"; sprintf(proc, "Processor MV-%02d", TT); break; case PKGTYPE(3) + CMPCAP(0) + BTI(12) + PWRLMT(2): *brand_pre = "AMD Sempron(tm)"; sprintf(proc, "Processor 2%02dU", RR); break; case PKGTYPE(3) + CMPCAP(1) + BTI(1) + PWRLMT(6): *brand_pre = "Dual-Core AMD Opteron(tm)"; sprintf(proc, "Processor 12%02d HE", RR); break; case PKGTYPE(3) + CMPCAP(1) + BTI(1) + PWRLMT(10): *brand_pre = "Dual-Core AMD Opteron(tm)"; sprintf(proc, "Processor 12%02d", RR); break; case PKGTYPE(3) + CMPCAP(1) + BTI(1) + PWRLMT(12): *brand_pre = "Dual-Core AMD Opteron(tm)"; sprintf(proc, "Processor 12%02d SE", RR); break; case PKGTYPE(3) + CMPCAP(1) + BTI(3) + PWRLMT(3): *brand_pre = "AMD Athlon(tm) X2 Dual Core"; sprintf(proc, "Processor BE-2%02d0", TT); break; case PKGTYPE(3) + CMPCAP(1) + BTI(4) + PWRLMT(1): case PKGTYPE(3) + CMPCAP(1) + BTI(4) + PWRLMT(2): case PKGTYPE(3) + CMPCAP(1) + BTI(4) + PWRLMT(6): case PKGTYPE(3) + CMPCAP(1) + BTI(4) + PWRLMT(8): case PKGTYPE(3) + CMPCAP(1) + BTI(4) + PWRLMT(12): *brand_pre = "AMD Athlon(tm) 64 X2 Dual Core"; sprintf(proc, "Processor %02d00+", TT); break; case PKGTYPE(3) + CMPCAP(1) + BTI(5) + PWRLMT(12): *brand_pre = "AMD Athlon(tm) 64"; sprintf(proc, "FX-%02d", ZZ); *brand_post = "Dual Core"; break; case PKGTYPE(3) + CMPCAP(1) + BTI(6) + PWRLMT(6): *brand_pre = "AMD Sempron(tm) Dual Core"; sprintf(proc, "Processor %02d00", RR); break; case PKGTYPE(3) + CMPCAP(1) + BTI(7) + PWRLMT(3): *brand_pre = "AMD Athlon(tm) Dual Core"; sprintf(proc, "Processor %02d50e", TT); break; case PKGTYPE(3) + CMPCAP(1) + BTI(7) + PWRLMT(6): case PKGTYPE(3) + CMPCAP(1) + BTI(7) + PWRLMT(7): *brand_pre = "AMD Athlon(tm) Dual Core"; sprintf(proc, "Processor %02d00B", TT); break; case PKGTYPE(3) + CMPCAP(1) + BTI(8) + PWRLMT(3): *brand_pre = "AMD Athlon(tm) Dual Core"; sprintf(proc, "Processor %02d50B", TT); break; case PKGTYPE(3) + CMPCAP(1) + BTI(9) + PWRLMT(1): *brand_pre = "AMD Athlon(tm) X2 Dual Core"; sprintf(proc, "Processor %02d50e", TT); break; case PKGTYPE(3) + CMPCAP(1) + BTI(10) + PWRLMT(1): case PKGTYPE(3) + CMPCAP(1) + BTI(10) + PWRLMT(2): *brand_pre = "AMD Athlon(tm) Neo X2 Dual Core"; sprintf(proc, "Processor %02d50e", TT); break; case PKGTYPE(3) + CMPCAP(1) + BTI(11) + PWRLMT(0): *brand_pre = "AMD Turion(tm) Neo X2 Dual Core"; sprintf(proc, "Processor L6%02d", RR); break; case PKGTYPE(3) + CMPCAP(1) + BTI(12) + PWRLMT(0): *brand_pre = "AMD Turion(tm) Neo X2 Dual Core"; sprintf(proc, "Processor L3%02d", RR); break; /* Table 9: Name String Table for S1g1 Processors */ case PKGTYPE(0) + CMPCAP(0) + BTI(1) + PWRLMT(2): *brand_pre = "AMD Athlon(tm) 64"; sprintf(proc, "Processor %02d00+", TT); break; case PKGTYPE(0) + CMPCAP(0) + BTI(2) + PWRLMT(12): *brand_pre = "AMD Turion(tm) 64 Mobile Technology"; sprintf(proc, "MK-%02d", YY); break; case PKGTYPE(0) + CMPCAP(0) + BTI(3) + PWRLMT(1): *brand_pre = "Mobile AMD Sempron(tm)"; sprintf(proc, "Processor %02d00+", TT); break; case PKGTYPE(0) + CMPCAP(0) + BTI(3) + PWRLMT(6): case PKGTYPE(0) + CMPCAP(0) + BTI(3) + PWRLMT(12): *brand_pre = "Mobile AMD Sempron(tm)"; sprintf(proc, "Processor %02d00+", PP); break; case PKGTYPE(0) + CMPCAP(0) + BTI(4) + PWRLMT(2): *brand_pre = "AMD Sempron(tm)"; sprintf(proc, "Processor %02d00+", TT); break; case PKGTYPE(0) + CMPCAP(0) + BTI(6) + PWRLMT(4): case PKGTYPE(0) + CMPCAP(0) + BTI(6) + PWRLMT(6): case PKGTYPE(0) + CMPCAP(0) + BTI(6) + PWRLMT(12): *brand_pre = "AMD Athlon(tm)"; sprintf(proc, "Processor TF-%02d", TT); break; case PKGTYPE(0) + CMPCAP(0) + BTI(7) + PWRLMT(3): *brand_pre = "AMD Athlon(tm)"; sprintf(proc, "Processor L1%02d", RR); break; case PKGTYPE(0) + CMPCAP(1) + BTI(1) + PWRLMT(12): *brand_pre = "AMD Sempron(tm)"; sprintf(proc, "Processor TJ-%02d", YY); break; case PKGTYPE(0) + CMPCAP(1) + BTI(2) + PWRLMT(12): *brand_pre = "AMD Turion(tm) 64 X2 Mobile Technology"; sprintf(proc, "Processor TL-%02d", YY); break; case PKGTYPE(0) + CMPCAP(1) + BTI(3) + PWRLMT(4): case PKGTYPE(0) + CMPCAP(1) + BTI(3) + PWRLMT(12): *brand_pre = "AMD Turion(tm) 64 X2 Dual-Core"; sprintf(proc, "Processor TK-%02d", YY); break; case PKGTYPE(0) + CMPCAP(1) + BTI(5) + PWRLMT(4): *brand_pre = "AMD Turion(tm) 64 X2 Dual Core"; sprintf(proc, "Processor %02d00+", TT); break; case PKGTYPE(0) + CMPCAP(1) + BTI(6) + PWRLMT(2): *brand_pre = "AMD Turion(tm) X2 Dual Core"; sprintf(proc, "Processor L3%02d", RR); break; case PKGTYPE(0) + CMPCAP(1) + BTI(7) + PWRLMT(4): *brand_pre = "AMD Turion(tm) X2 Dual Core"; sprintf(proc, "Processor L5%02d", RR); break; } #undef RR #undef PP #undef TT #undef ZZ #undef YY } else if (MaskF(stash->val_1_eax) == ShftXF(1) + ShftF(15) || MaskF(stash->val_1_eax) == ShftXF(2) + ShftF(15) || MaskF(stash->val_1_eax) == ShftXF(3) + ShftF(15) || MaskF(stash->val_1_eax) == ShftXF(5) + ShftF(15)) { /* ** Algorithm from: ** AMD Revision Guide for AMD Family 10h Processors (41322 Rev 3.74) ** AMD Revision Guide for AMD Family 11h Processors (41788 Rev 3.08) ** AMD Revision Guide for AMD Family 12h Processors (44739 Rev 3.10) ** AMD Revision Guide for AMD Family 14h Models 00h-0Fh Processors ** (47534 Rev 3.00) ** But using only the Processor numbers. */ unsigned int str1; unsigned int str2; unsigned int pg; unsigned int partialmodel; unsigned int pkgtype; unsigned int nc; const char* s1; const char* s2; str2 = BIT_EXTRACT_LE(stash->val_80000001_ebx, 0, 4); partialmodel = BIT_EXTRACT_LE(stash->val_80000001_ebx, 4, 11); str1 = BIT_EXTRACT_LE(stash->val_80000001_ebx, 11, 15); pg = BIT_EXTRACT_LE(stash->val_80000001_ebx, 15, 16); pkgtype = BIT_EXTRACT_LE(stash->val_80000001_ebx, 28, 32); nc = BIT_EXTRACT_LE(stash->val_80000008_ecx, 0, 8); #define NC(nc) ((nc) << 9) #define PG(pg) ((pg) << 8) #define STR1(str1) ((str1) << 4) #define STR2(str2) (str2) /* ** In every String2 Values table, there were special cases for ** pg == 0 && str2 == 15 which defined them as the empty string. ** But that produces the same result as an undefined string, so ** don't bother trying to handle them. */ if (MaskF(stash->val_1_eax) == ShftXF(1) + ShftF(15)) { if (pkgtype >= 2) { partialmodel--; } /* Family 10h tables */ switch (pkgtype) { case 0: /* 41322 3.74: table 14: String1 Values for Fr2, Fr5, and Fr6 (1207) Processors */ switch (PG(pg) + NC(nc) + STR1(str1)) { case PG(0) + NC(3) + STR1(0): *brand_pre = "Quad-Core AMD Opteron(tm)"; s1 = "Processor 83"; break; case PG(0) + NC(3) + STR1(1): *brand_pre = "Quad-Core AMD Opteron(tm)"; s1 = "Processor 23"; break; case PG(0) + NC(5) + STR1(0): *brand_pre = "Six-Core AMD Opteron(tm)"; s1 = "Processor 84"; break; case PG(0) + NC(5) + STR1(1): *brand_pre = "Six-Core AMD Opteron(tm)"; s1 = "Processor 24"; break; case PG(1) + NC(3) + STR1(1): *brand_pre = "Embedded AMD Opteron(tm)"; s1 = "Processor "; break; case PG(1) + NC(5) + STR1(1): *brand_pre = "Embedded AMD Opteron(tm)"; s1 = "Processor "; break; default: s1 = NULL; break; } /* 41322 3.74: table 15: String2 Values for Fr2, Fr5, and Fr6 (1207) Processors */ switch (PG(pg) + NC(nc) + STR2(str2)) { case PG(0) + NC(3) + STR2(10): s2 = " SE"; break; case PG(0) + NC(3) + STR2(11): s2 = " HE"; break; case PG(0) + NC(3) + STR2(12): s2 = " EE"; break; case PG(0) + NC(5) + STR2(0): s2 = " SE"; break; case PG(0) + NC(5) + STR2(1): s2 = " HE"; break; case PG(0) + NC(5) + STR2(2): s2 = " EE"; break; case PG(1) + NC(3) + STR2(1): s2 = "GF HE"; break; case PG(1) + NC(3) + STR2(2): s2 = "HF HE"; break; case PG(1) + NC(3) + STR2(3): s2 = "VS"; break; case PG(1) + NC(3) + STR2(4): s2 = "QS HE"; break; case PG(1) + NC(3) + STR2(5): s2 = "NP HE"; break; case PG(1) + NC(3) + STR2(6): s2 = "KH HE"; break; case PG(1) + NC(3) + STR2(7): s2 = "KS HE"; break; case PG(1) + NC(5) + STR2(1): s2 = "QS"; break; case PG(1) + NC(5) + STR2(2): s2 = "KS HE"; break; default: s2 = NULL; break; } break; case 1: /* 41322 3.74: table 16: String1 Values for AM2r2 and AM3 Processors */ switch (PG(pg) + NC(nc) + STR1(str1)) { case PG(0) + NC(0) + STR1(2): *brand_pre = "AMD Sempron(tm)"; s1 = "1"; break; /* This case obviously collides with one later */ /* case PG(0) + NC(0) + STR1(3): *brand_pre = "AMD Athlon(tm) II"; s1 = "AMD Athlon(tm) II 1"; */ case PG(0) + NC(0) + STR1(1): *brand_pre = "AMD Athlon(tm)"; s1 = ""; break; case PG(0) + NC(0) + STR1(3): *brand_pre = "AMD Athlon(tm) II X2"; s1 = "2"; break; case PG(0) + NC(0) + STR1(4): *brand_pre = "AMD Athlon(tm) II X2"; s1 = "B"; break; case PG(0) + NC(0) + STR1(5): *brand_pre = "AMD Athlon(tm) II X2"; s1 = ""; break; case PG(0) + NC(0) + STR1(7): *brand_pre = "AMD Phenom(tm) II X2"; s1 = "5"; break; case PG(0) + NC(0) + STR1(10): *brand_pre = "AMD Phenom(tm) II X2"; s1 = ""; break; case PG(0) + NC(0) + STR1(11): *brand_pre = "AMD Phenom(tm) II X2"; s1 = "B"; break; case PG(0) + NC(0) + STR1(12): *brand_pre = "AMD Sempron(tm) X2"; s1 = "1"; break; case PG(0) + NC(2) + STR1(0): *brand_pre = "AMD Phenom(tm)"; s1 = ""; break; case PG(0) + NC(2) + STR1(3): *brand_pre = "AMD Phenom(tm) II X3"; s1 = "B"; break; case PG(0) + NC(2) + STR1(4): *brand_pre = "AMD Phenom(tm) II X3"; s1 = ""; break; case PG(0) + NC(2) + STR1(7): *brand_pre = "AMD Phenom(tm) II X3"; s1 = "4"; break; case PG(0) + NC(2) + STR1(8): *brand_pre = "AMD Phenom(tm) II X3"; s1 = "7"; break; case PG(0) + NC(2) + STR1(10): *brand_pre = "AMD Phenom(tm) II X3"; s1 = ""; break; case PG(0) + NC(3) + STR1(0): *brand_pre = "Quad-Core AMD Opteron(tm)"; s1 = "Processor 13"; break; case PG(0) + NC(3) + STR1(2): *brand_pre = "AMD Phenom(tm)"; s1 = ""; break; case PG(0) + NC(3) + STR1(3): *brand_pre = "AMD Phenom(tm) II X4"; s1 = "9"; break; case PG(0) + NC(3) + STR1(4): *brand_pre = "AMD Phenom(tm) II X4"; s1 = "8"; break; case PG(0) + NC(3) + STR1(7): *brand_pre = "AMD Phenom(tm) II X4"; s1 = "B"; break; case PG(0) + NC(3) + STR1(8): *brand_pre = "AMD Phenom(tm) II X4"; s1 = ""; break; case PG(0) + NC(3) + STR1(10): *brand_pre = "AMD Athlon(tm) II X4"; s1 = "6"; break; case PG(0) + NC(3) + STR1(15): *brand_pre = "AMD Athlon(tm) II X4"; s1 = ""; break; case PG(0) + NC(5) + STR1(0): *brand_pre = "AMD Phenom(tm) II X6"; s1 = "1"; break; case PG(1) + NC(1) + STR1(1): *brand_pre = "AMD Athlon(tm) II XLT V"; s1 = ""; break; case PG(1) + NC(1) + STR1(2): *brand_pre = "AMD Athlon(tm) II XL V"; s1 = ""; break; case PG(1) + NC(3) + STR1(1): *brand_pre = "AMD Phenom(tm) II XLT Q"; s1 = ""; break; case PG(1) + NC(3) + STR1(2): *brand_pre = "AMD Phenom(tm) II X4"; s1 = "9"; break; case PG(1) + NC(3) + STR1(3): *brand_pre = "AMD Phenom(tm) II X4"; s1 = "8"; break; case PG(1) + NC(3) + STR1(4): *brand_pre = "AMD Phenom(tm) II X4"; s1 = "6"; break; default: s1 = NULL; break; } /* 41322 3.74: table 17: String2 Values for AM2r2 and AM3 Processors */ switch (PG(pg) + NC(nc) + STR2(str2)) { case PG(0) + NC(0) + STR2(10): s2 = " Processor"; break; case PG(0) + NC(0) + STR2(11): s2 = "u Processor"; break; case PG(0) + NC(1) + STR2(3): s2 = "50 Dual-Core Processor"; break; case PG(0) + NC(1) + STR2(6): s2 = " Processor"; break; case PG(0) + NC(1) + STR2(7): s2 = "e Processor"; break; case PG(0) + NC(1) + STR2(9): s2 = "0 Processor"; break; case PG(0) + NC(1) + STR2(10): s2 = "0e Processor"; break; case PG(0) + NC(1) + STR2(11): s2 = "u Processor"; break; case PG(0) + NC(2) + STR2(0): s2 = "00 Triple-Core Processor"; break; case PG(0) + NC(2) + STR2(1): s2 = "00e Triple-Core Processor"; break; case PG(0) + NC(2) + STR2(2): s2 = "00B Triple-Core Processor"; break; case PG(0) + NC(2) + STR2(3): s2 = "50 Triple-Core Processor"; break; case PG(0) + NC(2) + STR2(4): s2 = "50e Triple-Core Processor"; break; case PG(0) + NC(2) + STR2(5): s2 = "50B Triple-Core Processor"; break; case PG(0) + NC(2) + STR2(6): s2 = " Processor"; break; case PG(0) + NC(2) + STR2(7): s2 = "e Processor"; break; case PG(0) + NC(2) + STR2(9): s2 = "0e Processor"; break; case PG(0) + NC(2) + STR2(10): s2 = "0 Processor"; break; case PG(0) + NC(3) + STR2(0): s2 = "00 Quad-Core Processor"; break; case PG(0) + NC(3) + STR2(1): s2 = "00e Quad-Core Processor"; break; case PG(0) + NC(3) + STR2(2): s2 = "00B Quad-Core Processor"; break; case PG(0) + NC(3) + STR2(3): s2 = "50 Quad-Core Processor"; break; case PG(0) + NC(3) + STR2(4): s2 = "50e Quad-Core Processor"; break; case PG(0) + NC(3) + STR2(5): s2 = "50B Quad-Core Processor"; break; case PG(0) + NC(3) + STR2(6): s2 = " Processor"; break; case PG(0) + NC(3) + STR2(7): s2 = "e Processor"; break; case PG(0) + NC(3) + STR2(9): s2 = "0e Processor"; break; case PG(0) + NC(3) + STR2(14): s2 = "0 Processor"; break; case PG(0) + NC(5) + STR2(0): s2 = "5T Processor"; break; case PG(0) + NC(5) + STR2(1): s2 = "0T Processor"; break; case PG(1) + NC(1) + STR2(1): s2 = "L Processor"; break; case PG(1) + NC(1) + STR2(2): s2 = "C Processor"; break; case PG(1) + NC(3) + STR2(1): s2 = "L Processor"; break; case PG(1) + NC(3) + STR2(4): s2 = "T Processor"; break; default: s2 = NULL; break; } break; case 2: /* 41322 3.74: table 18: String1 Values for S1g3 and S1g4 Processors */ switch (PG(pg) + NC(nc) + STR1(str1)) { case PG(0) + NC(0) + STR1(0): *brand_pre = "AMD Sempron(tm)"; s1 = "M1"; break; case PG(0) + NC(0) + STR1(1): *brand_pre = "AMD"; s1 = "V"; break; case PG(0) + NC(1) + STR1(0): *brand_pre = "AMD Turion(tm) II Ultra Dual-Core Mobile"; s1 = "M6"; break; case PG(0) + NC(1) + STR1(1): *brand_pre = "AMD Turion(tm) II Dual-Core Mobile"; s1 = "M5"; break; case PG(0) + NC(1) + STR1(2): *brand_pre = "AMD Athlon(tm) II Dual-Core"; s1 = "M3"; break; case PG(0) + NC(1) + STR1(3): *brand_pre = "AMD Turion(tm) II"; s1 = "P"; break; case PG(0) + NC(1) + STR1(4): *brand_pre = "AMD Athlon(tm) II"; s1 = "P"; break; case PG(0) + NC(1) + STR1(5): *brand_pre = "AMD Phenom(tm) II"; s1 = "X"; break; case PG(0) + NC(1) + STR1(6): *brand_pre = "AMD Phenom(tm) II"; s1 = "N"; break; case PG(0) + NC(1) + STR1(7): *brand_pre = "AMD Turion(tm) II"; s1 = "N"; break; case PG(0) + NC(1) + STR1(8): *brand_pre = "AMD Athlon(tm) II"; s1 = "N"; break; case PG(0) + NC(2) + STR1(2): *brand_pre = "AMD Phenom(tm) II"; s1 = "P"; break; case PG(0) + NC(2) + STR1(3): *brand_pre = "AMD Phenom(tm) II"; s1 = "N"; break; case PG(0) + NC(3) + STR1(1): *brand_pre = "AMD Phenom(tm) II"; s1 = "P"; break; case PG(0) + NC(3) + STR1(2): *brand_pre = "AMD Phenom(tm) II"; s1 = "X"; break; case PG(0) + NC(3) + STR1(3): *brand_pre = "AMD Phenom(tm) II"; s1 = "N"; break; default: s1 = NULL; break; } /* 41322 3.74: table 19: String1 Values for S1g3 and S1g4 Processors */ switch (PG(pg) + NC(nc) + STR2(str2)) { case PG(0) + NC(0) + STR2(1): s2 = "0 Processor"; break; case PG(0) + NC(1) + STR2(2): s2 = "0 Dual-Core Processor"; break; case PG(0) + NC(2) + STR2(2): s2 = "0 Triple-Core Processor"; break; case PG(0) + NC(3) + STR2(1): s2 = "0 Quad-Core Processor"; break; default: s2 = NULL; break; } break; case 3: /* 41322 3.74: table 20: String1 Values for G34r1 Processors */ switch (PG(pg) + NC(nc) + STR1(str1)) { case PG(0) + NC(7) + STR1(0): *brand_pre = "AMD Opteron(tm)"; s1 = "Processor 61"; break; case PG(0) + NC(11) + STR1(0): *brand_pre = "AMD Opteron(tm)"; s1 = "Processor 61"; break; case PG(1) + NC(7) + STR1(1): *brand_pre = "Embedded AMD Opteron(tm)"; s1 = "Processor "; break; /* It sure is odd that there are no 0/7/1 or 0/11/1 cases here. */ default: s1 = NULL; break; } /* 41322 3.74: table 21: String2 Values for G34r1 Processors */ switch (PG(pg) + NC(nc) + STR2(str2)) { case PG(0) + NC(7) + STR1(0): s2 = " HE"; break; case PG(0) + NC(7) + STR1(1): s2 = " SE"; break; case PG(0) + NC(11) + STR1(0): s2 = " HE"; break; case PG(0) + NC(11) + STR1(1): s2 = " SE"; break; case PG(1) + NC(7) + STR1(1): s2 = "QS"; break; case PG(1) + NC(7) + STR1(2): s2 = "KS"; break; default: s2 = NULL; break; } break; case 4: /* 41322 3.74: table 22: String1 Values for ASB2 Processors */ switch (PG(pg) + NC(nc) + STR1(str1)) { case PG(0) + NC(0) + STR1(1): *brand_pre = "AMD Athlon(tm) II Neo"; s1 = "K"; break; case PG(0) + NC(0) + STR1(2): *brand_pre = "AMD"; s1 = "V"; break; case PG(0) + NC(0) + STR1(3): *brand_pre = "AMD Athlon(tm) II Neo"; s1 = "R"; break; case PG(0) + NC(1) + STR1(1): *brand_pre = "AMD Turion(tm) II Neo"; s1 = "K"; break; case PG(0) + NC(1) + STR1(2): *brand_pre = "AMD Athlon(tm) II Neo"; s1 = "K"; break; case PG(0) + NC(1) + STR1(3): *brand_pre = "AMD"; s1 = "V"; break; case PG(0) + NC(1) + STR1(4): *brand_pre = "AMD Turion(tm) II Neo"; s1 = "N"; break; case PG(0) + NC(1) + STR1(5): *brand_pre = "AMD Athlon(tm) II Neo"; s1 = "N"; break; default: s1 = NULL; break; } /* 41322 3.74: table 23: String2 Values for ASB2 Processors */ switch (PG(pg) + NC(nc) + STR2(str2)) { case PG(0) + NC(0) + STR1(1): s2 = "5 Processor"; break; case PG(0) + NC(0) + STR1(2): s2 = "L Processor"; break; case PG(0) + NC(1) + STR1(1): s2 = "5 Dual-Core Processor"; break; case PG(0) + NC(1) + STR1(2): s2 = "L Dual-Core Processor"; break; default: s2 = NULL; break; } break; case 5: /* 41322 3.74: table 24: String1 Values for C32r1 Processors */ switch (PG(pg) + NC(nc) + STR1(str1)) { case PG(0) + NC(3) + STR1(0): *brand_pre = "AMD Opteron(tm)"; s1 = "41"; break; case PG(0) + NC(5) + STR1(0): *brand_pre = "AMD Opteron(tm)"; s1 = "41"; break; case PG(1) + NC(3) + STR1(1): *brand_pre = "Embedded AMD Opteron(tm)"; s1 = " "; break; case PG(1) + NC(5) + STR1(1): *brand_pre = "Embedded AMD Opteron(tm)"; s1 = " "; break; /* It sure is odd that there are no 0/3/1 or 0/5/1 cases here. */ default: s1 = NULL; break; } /* 41322 3.74: table 25: String2 Values for C32r1 Processors */ /* 41322 3.74: table 25 */ switch (PG(pg) + NC(nc) + STR2(str2)) { case PG(0) + NC(3) + STR1(0): s2 = " HE"; break; case PG(0) + NC(3) + STR1(1): s2 = " EE"; break; case PG(0) + NC(5) + STR1(0): s2 = " HE"; break; case PG(0) + NC(5) + STR1(1): s2 = " EE"; break; case PG(1) + NC(3) + STR1(1): s2 = "QS HE"; break; case PG(1) + NC(3) + STR1(2): s2 = "LE HE"; break; case PG(1) + NC(3) + STR1(3): s2 = "CL EE"; break; case PG(1) + NC(5) + STR1(1): s2 = "KX HE"; break; case PG(1) + NC(5) + STR1(2): s2 = "GL EE"; break; default: s2 = NULL; break; } break; default: s1 = NULL; s2 = NULL; break; } } else if (MaskF(stash->val_1_eax) == ShftXF(2) + ShftF(15)) { /* Family 11h tables */ switch (pkgtype) { case 2: /* 41788 3.08: table 3: String1 Values for S1g2 Processors */ switch (PG(pg) + NC(nc) + STR1(str1)) { case PG(0) + NC(0) + STR1(0): *brand_pre = "AMD Sempron(tm)"; s1 = "SI-"; break; case PG(0) + NC(0) + STR1(1): *brand_pre = "AMD Athlon(tm)"; s1 = "QI-"; break; case PG(0) + NC(1) + STR1(0): *brand_pre = "AMD Turion(tm) X2 Ultra Dual-Core Mobile"; s1 = "ZM-"; break; case PG(0) + NC(1) + STR1(1): *brand_pre = "AMD Turion(tm) X2 Dual-Core Mobile"; s1 = "RM-"; break; case PG(0) + NC(1) + STR1(2): *brand_pre = "AMD Athlon(tm) X2 Dual-Core"; s1 = "QL-"; break; case PG(0) + NC(1) + STR1(3): *brand_pre = "AMD Sempron(tm) X2 Dual-Core"; s1 = "NI-"; break; default: s1 = NULL; break; } /* 41788 3.08: table 4: String2 Values for S1g2 Processors */ switch (PG(pg) + NC(nc) + STR2(str2)) { case PG(0) + NC(0) + STR2(0): s2 = ""; break; case PG(0) + NC(1) + STR2(0): s2 = ""; break; default: s2 = NULL; break; } break; default: s1 = NULL; s2 = NULL; break; } } else if (MaskF(stash->val_1_eax) == ShftXF(3) + ShftF(15)) { partialmodel--; /* Family 12h tables */ switch (pkgtype) { case 1: /* 44739 3.10: table 6: String1 Values for FS1 Processors */ switch (PG(pg) + NC(nc) + STR1(str1)) { case PG(0) + NC(1) + STR1(3): *brand_pre = "AMD"; s1 = "A4-33"; break; case PG(0) + NC(1) + STR1(5): *brand_pre = "AMD"; s1 = "E2-30"; break; case PG(0) + NC(3) + STR1(1): *brand_pre = "AMD"; s1 = "A8-35"; break; case PG(0) + NC(3) + STR1(3): *brand_pre = "AMD"; s1 = "A6-34"; break; default: s1 = NULL; break; } /* 44739 3.10: table 7: String2 Values for FS1 Processors */ switch (PG(pg) + NC(nc) + STR2(str2)) { case PG(0) + NC(1) + STR2(1): s2 = "M"; break; case PG(0) + NC(1) + STR2(2): s2 = "MX"; break; case PG(0) + NC(3) + STR2(1): s2 = "M"; break; case PG(0) + NC(3) + STR2(2): s2 = "MX"; break; default: s2 = NULL; break; } break; case 2: /* 44739 3.10: table 8: String1 Values for FM1 Processors */ switch (PG(pg) + NC(nc) + STR1(str1)) { case PG(0) + NC(1) + STR1(1): *brand_pre = "AMD"; s1 = "A4-33"; break; case PG(0) + NC(1) + STR1(2): *brand_pre = "AMD"; s1 = "E2-32"; break; case PG(0) + NC(1) + STR1(4): *brand_pre = "AMD Athlon(tm) II X2"; s1 = "2"; break; case PG(0) + NC(1) + STR1(5): *brand_pre = "AMD"; s1 = "A4-34"; break; case PG(0) + NC(1) + STR1(12): *brand_pre = "AMD Sempron(tm) X2"; s1 = "1"; break; case PG(0) + NC(2) + STR1(5): *brand_pre = "AMD"; s1 = "A6-35"; break; case PG(0) + NC(3) + STR1(5): *brand_pre = "AMD"; s1 = "A8-38"; break; case PG(0) + NC(3) + STR1(6): *brand_pre = "AMD"; s1 = "A6-36"; break; case PG(0) + NC(3) + STR1(13): *brand_pre = "AMD Athlon(tm) II X4"; s1 = "6"; break; default: s1 = NULL; break; } /* 44739 3.10: table 9: String2 Values for FM1 Processors */ switch (PG(pg) + NC(nc) + STR2(str2)) { case PG(0) + NC(1) + STR2(1): s2 = " APU with Radeon(tm) HD Graphics"; break; case PG(0) + NC(1) + STR2(2): s2 = " Dual-Core Processor"; break; case PG(0) + NC(2) + STR2(1): s2 = " APU with Radeon(tm) HD Graphics"; break; case PG(0) + NC(3) + STR2(1): s2 = " APU with Radeon(tm) HD Graphics"; break; case PG(0) + NC(3) + STR2(3): s2 = " Quad-Core Processor"; break; default: s2 = NULL; break; } break; default: s1 = NULL; s2 = NULL; break; } } else if (MaskF(stash->val_1_eax) == ShftXF(5) + ShftF(15)) { partialmodel--; /* Family 14h Models 00h-0Fh tables */ switch (pkgtype) { case 0: /* 47534 3.00: table 4: String1 Values for FT1 Processors */ switch (PG(pg) + NC(nc) + STR1(str1)) { case PG(0) + NC(0) + STR1(1): *brand_pre = "AMD"; s1 = "C-"; break; case PG(0) + NC(0) + STR1(2): *brand_pre = "AMD"; s1 = "E-"; break; case PG(0) + NC(0) + STR1(4): *brand_pre = "AMD"; s1 = "G-T"; break; case PG(0) + NC(1) + STR1(1): *brand_pre = "AMD"; s1 = "C-"; break; case PG(0) + NC(1) + STR1(2): *brand_pre = "AMD"; s1 = "E-"; break; case PG(0) + NC(1) + STR1(3): *brand_pre = "AMD"; s1 = "Z-"; break; case PG(0) + NC(1) + STR1(4): *brand_pre = "AMD"; s1 = "G-T"; break; case PG(0) + NC(1) + STR1(5): *brand_pre = "AMD"; s1 = "E1-1"; break; case PG(0) + NC(1) + STR1(6): *brand_pre = "AMD"; s1 = "E2-1"; break; case PG(0) + NC(1) + STR1(7): *brand_pre = "AMD"; s1 = "E2-2"; break; default: s1 = NULL; break; } /* 47534 3.00: table 5: String2 Values for FT1 Processors */ switch (PG(pg) + NC(nc) + STR2(str2)) { case PG(0) + NC(0) + STR2(1): s2 = ""; break; case PG(0) + NC(0) + STR2(2): s2 = "0"; break; case PG(0) + NC(0) + STR2(3): s2 = "5"; break; case PG(0) + NC(0) + STR2(4): s2 = "0x"; break; case PG(0) + NC(0) + STR2(5): s2 = "5x"; break; case PG(0) + NC(0) + STR2(6): s2 = "x"; break; case PG(0) + NC(0) + STR2(7): s2 = "L"; break; case PG(0) + NC(0) + STR2(8): s2 = "N"; break; case PG(0) + NC(0) + STR2(9): s2 = "R"; break; case PG(0) + NC(0) + STR2(10): s2 = "0"; break; case PG(0) + NC(0) + STR2(11): s2 = "5"; break; case PG(0) + NC(0) + STR2(12): s2 = ""; break; case PG(0) + NC(0) + STR2(13): s2 = "0D"; break; case PG(0) + NC(1) + STR2(1): s2 = ""; break; case PG(0) + NC(1) + STR2(2): s2 = "0"; break; case PG(0) + NC(1) + STR2(3): s2 = "5"; break; case PG(0) + NC(1) + STR2(4): s2 = "0x"; break; case PG(0) + NC(1) + STR2(5): s2 = "5x"; break; case PG(0) + NC(1) + STR2(6): s2 = "x"; break; case PG(0) + NC(1) + STR2(7): s2 = "L"; break; case PG(0) + NC(1) + STR2(8): s2 = "N"; break; case PG(0) + NC(1) + STR2(9): s2 = "0"; break; case PG(0) + NC(1) + STR2(10): s2 = "5"; break; case PG(0) + NC(1) + STR2(11): s2 = ""; break; case PG(0) + NC(1) + STR2(12): s2 = "E"; break; case PG(0) + NC(1) + STR2(13): s2 = "0D"; break; default: s2 = NULL; break; } break; default: s1 = NULL; s2 = NULL; break; } } else { s1 = NULL; s2 = NULL; } #undef NC #undef PG #undef STR1 #undef STR2 if (s1 != NULL) { char* p = proc; p += sprintf(p, "%s%02d", s1, partialmodel); if (s2) sprintf(p, "%s", s2); } } } static void decode_override_brand(code_stash_t* stash) { if ((stash->vendor == VENDOR_AMD || stash->vendor == VENDOR_HYGON) && strstr(stash->brand, "model unknown") != NULL) { /* ** AMD has this exotic architecture where the BIOS decodes the brand ** string from tables and feeds it back into the CPU via MSR's. If an old ** BIOS cannot understand a new CPU, it uses the string "model unknown". ** In this case, I use my own copies of tables to deduce the brand string ** and decode that. */ const char* brand_pre; const char* brand_post; char proc[34]; decode_amd_model(stash, &brand_pre, &brand_post, proc); if (brand_pre != NULL) { char* b = stash->override_brand; b += sprintf(b, "%s %s", brand_pre, proc); if (brand_post != NULL) sprintf(b, " %s", brand_post); } } } static void print_override_brand(code_stash_t* stash) { if (stash->override_brand[0] != '\0') { printf(" (override brand synth) = %s\n", stash->override_brand); } } static void stash_intel_cache(code_stash_t* stash, unsigned char value) { switch (value) { case 0x42: stash->L2_4w_256K = TRUE; break; case 0x43: stash->L2_4w_512K = TRUE; break; case 0x44: stash->L2_4w_1Mor2M = TRUE; break; case 0x45: stash->L2_4w_1Mor2M = TRUE; break; case 0x80: stash->L2_8w_512K = TRUE; break; case 0x82: stash->L2_8w_256K = TRUE; break; case 0x83: stash->L2_8w_512K = TRUE; break; case 0x84: stash->L2_8w_1Mor2M = TRUE; break; case 0x85: stash->L2_8w_1Mor2M = TRUE; break; } switch (value) { case 0x45: case 0x7d: case 0x85: stash->L2_2M = TRUE; break; } switch (value) { case 0x4e: stash->L2_6M = TRUE; break; } switch (value) { case 0x22: case 0x23: case 0x25: case 0x29: case 0x46: case 0x47: case 0x49: case 0x4a: case 0x4b: case 0x4c: case 0x4d: case 0x88: case 0x89: case 0x8a: case 0x8d: case 0xd0: case 0xd1: case 0xd2: case 0xd6: case 0xd7: case 0xd8: case 0xdc: case 0xdd: case 0xde: case 0xe2: case 0xe3: case 0xe4: case 0xea: case 0xeb: case 0xec: stash->L3 = TRUE; break; } switch (value) { case 0x21: case 0x3c: case 0x42: case 0x7a: case 0x7e: case 0x82: stash->L2_256K = TRUE; break; } switch (value) { case 0x3e: case 0x43: case 0x7b: case 0x7f: case 0x83: case 0x86: stash->L2_512K = TRUE; break; } } static void decode_brand_id_stash(code_stash_t* stash) { unsigned int val_1_eax = stash->val_1_eax; unsigned int val_1_ebx = stash->val_1_ebx; switch (MaskB(val_1_ebx)) { case ShftB(0): break; case ShftB(1): stash->bri.desktop_celeron = TRUE; break; case ShftB(2): stash->bri.desktop_pentium = TRUE; break; case ShftB(3): if (MaskFMS(val_1_eax) == ShftFMS(0,6, 0,11, 1)) { stash->bri.desktop_celeron = TRUE; } else { stash->bri.xeon = TRUE; } break; case ShftB(4): stash->bri.desktop_pentium = TRUE; break; case ShftB(6): stash->bri.desktop_pentium = TRUE; break; case ShftB(7): stash->bri.desktop_celeron = TRUE; break; case ShftB(8): stash->bri.desktop_pentium = TRUE; break; case ShftB(9): stash->bri.desktop_pentium = TRUE; break; case ShftB(10): stash->bri.desktop_celeron = TRUE; break; case ShftB(11): if (MaskFMS(val_1_eax) <= ShftFMS(0,15, 0,1, 2)) { stash->bri.xeon_mp = TRUE; } else { stash->bri.xeon = TRUE; } break; case ShftB(12): stash->bri.xeon_mp = TRUE; break; case ShftB(14): if (MaskFMS(val_1_eax) <= ShftFMS(0,15, 0,1, 3)) { stash->bri.xeon = TRUE; } else { stash->bri.mobile_pentium_m = TRUE; } break; case ShftB(15): if (MaskFM(val_1_eax) == ShftFM(0,15, 0,2)) { stash->bri.mobile_pentium_m = TRUE; } else { stash->bri.mobile_celeron = TRUE; } break; case ShftB(16): stash->bri.desktop_celeron = TRUE; break; case ShftB(17): stash->bri.mobile_pentium = TRUE; break; case ShftB(18): stash->bri.desktop_celeron = TRUE; break; case ShftB(19): stash->bri.mobile_celeron = TRUE; break; case ShftB(20): stash->bri.desktop_celeron = TRUE; break; case ShftB(21): stash->bri.mobile_pentium = TRUE; break; case ShftB(22): stash->bri.desktop_pentium = TRUE; break; case ShftB(23): stash->bri.mobile_celeron = TRUE; break; default: break; } } static void decode_brand_string(const char* brand, code_stash_t* stash) { stash->br.mobile = (strstr(brand, "Mobile") != NULL || strstr(brand, "mobile") != NULL); stash->br.celeron = strstr(brand, "Celeron") != NULL; stash->br.core = (strstr(brand, "Core(TM)") != NULL || strstr(brand, "CoreT") != NULL); stash->br.pentium = strstr(brand, "Pentium") != NULL; stash->br.atom = strstr(brand, "Atom") != NULL; stash->br.xeon_mp = (strstr(brand, "Xeon MP") != NULL || strstr(brand, "Xeon(TM) MP") != NULL || strstr(brand, "Xeon(R)") != NULL); stash->br.xeon = (strstr(brand, "Xeon") != NULL || strstr(brand, "XEON") != NULL); stash->br.pentium_m = strstr(brand, "Pentium(R) M") != NULL; stash->br.pentium_d = strstr(brand, "Pentium(R) D") != NULL; stash->br.extreme = strregexp(brand, " ?X[0-9][0-9][0-9][0-9]"); stash->br.generic = strstr(brand, "Genuine Intel(R) CPU") != NULL; stash->br.scalable = (strstr(brand, "Bronze") != NULL || strstr(brand, "Silver") != NULL || strstr(brand, "Gold") != NULL || strstr(brand, "Platinum") != NULL || strstr(brand, "BRONZE") != NULL || strstr(brand, "SILVER") != NULL || strstr(brand, "GOLD") != NULL || strstr(brand, "PLATINUM") != NULL); stash->br.u_line = (strregexp(brand, "Core.* [im][3579]-[0-9]*U") || strregexp(brand, "Pentium.* [0-9]*U") || strregexp(brand, "Celeron.* [0-9]*U")); stash->br.y_line = (strregexp(brand, "Core.* [im][3579]-[0-9]*Y") || strregexp(brand, "Pentium.* [0-9]*Y") || strregexp(brand, "Celeron.* [0-9]*Y")); stash->br.g_line = strregexp(brand, "Core.* [im][3579]-[0-9]*G"); stash->br.i_8000 = strregexp(brand, "Core.* [im][3579]-8[0-9][0-9][0-9]"); stash->br.i_10000 = strregexp(brand, "Core.* i[3579]-10[0-9][0-9][0-9]"); stash->br.cc150 = strregexp(brand, "CC150"); stash->br.core_ultra = strstr(brand, "Core(TM) Ultra") != NULL; stash->br.athlon_lv = strstr(brand, "Athlon(tm) XP-M (LV)") != NULL; stash->br.athlon_xp = (strstr(brand, "Athlon(tm) XP") != NULL || strstr(brand, "Athlon(TM) XP") != NULL); stash->br.duron = strstr(brand, "Duron") != NULL; stash->br.athlon = strstr(brand, "Athlon") != NULL; stash->br.sempron = strstr(brand, "Sempron") != NULL; stash->br.phenom = strstr(brand, "Phenom") != NULL; stash->br.series = strstr(brand, "Series") != NULL; stash->br.a_series = (strstr(brand, "AMD A") != NULL || strstr(brand, "AMD PRO A") != NULL); stash->br.c_series = strstr(brand, "AMD C") != NULL; stash->br.e_series = strstr(brand, "AMD E") != NULL; stash->br.g_series = strstr(brand, "AMD G") != NULL; stash->br.r_series = strstr(brand, "AMD R") != NULL; stash->br.z_series = strstr(brand, "AMD Z") != NULL; stash->br.geode = strstr(brand, "Geode") != NULL; stash->br.turion = strstr(brand, "Turion") != NULL; stash->br.neo = strstr(brand, "Neo") != NULL; stash->br.athlon_fx = strstr(brand, "Athlon(tm) 64 FX") != NULL; stash->br.athlon_mp = strstr(brand, "Athlon(tm) MP") != NULL; stash->br.duron_mp = strstr(brand, "Duron(tm) MP") != NULL; stash->br.opteron = strstr(brand, "Opteron") != NULL; stash->br.fx = strstr(brand, "AMD FX") != NULL; stash->br.firepro = strstr(brand, "Firepro") != NULL; // total guess stash->br.ultra = strstr(brand, "Ultra") != NULL; stash->br.t_suffix = strregexp(brand, "[0-9][0-9][0-9][0-9]T"); stash->br.ryzen = strstr(brand, "Ryzen") != NULL; stash->br.threadripper = strstr(brand, "Threadripper") != NULL; stash->br.epyc = strstr(brand, "EPYC") != NULL; stash->br.epyc_3000 = strregexp(brand, "EPYC 3[0-9][0-9][0-9]"); stash->br.montage = strstr(brand, "Montage(R)") != NULL; stash->br.embedded = strstr(brand, "Embedded") != NULL; stash->br.embedded_V = strstr(brand, "Embedded V") != NULL; stash->br.embedded_R = strstr(brand, "Embedded R") != NULL; if (strstr(brand, "Dual Core") != NULL || strstr(brand, " X2 ") != NULL) { stash->br.cores = 2; } else if (strstr(brand, "Triple-Core") != NULL || strstr(brand, " X3 ") != NULL) { stash->br.cores = 3; } else if (strstr(brand, "Quad-Core") != NULL || strstr(brand, " X4 ") != NULL) { stash->br.cores = 4; } else if (strstr(brand, "Six-Core") != NULL || strstr(brand, " X6 ") != NULL) { stash->br.cores = 6; } else { stash->br.cores = 0; // means unspecified by the brand string } stash->br.mediagx = strstr(brand, "MediaGXtm") != NULL; stash->br.c7 = strstr(brand, "C7") != NULL; stash->br.c7m = strstr(brand, "C7-M") != NULL; stash->br.c7d = strstr(brand, "C7-D") != NULL; stash->br.eden = strstr(brand, "Eden") != NULL; stash->br.zhaoxin = strstr(brand, "ZHAOXIN") != NULL; } static void decode_brand_stash(code_stash_t* stash) { if (stash->override_brand[0] != '\0') { decode_brand_string(stash->override_brand, stash); } else { decode_brand_string(stash->brand, stash); } } /* ** Query macros are used in the synth tables to disambiguate multiple chips ** with the same family, model, and/or stepping. */ #define is_intel (stash->vendor == VENDOR_INTEL) #define is_amd (stash->vendor == VENDOR_AMD) #define is_cyrix (stash->vendor == VENDOR_CYRIX) #define is_via (stash->vendor == VENDOR_VIA) #define is_transmeta (stash->vendor == VENDOR_TRANSMETA) #define is_mobile (stash->br.mobile) /* ** Intel major queries: ** ** d? = think "desktop" (or unspecified) ** s? = think "server" (multiprocessor) ** M? = think "mobile" ** X? = think "Extreme Edition" ** L? = think "Line" ** ** ?G = think generic CPU ** ?P = think Pentium ** ?C = think Celeron ** ?a = think Atom ** ?X = think Xeon ** ?M = think Xeon MP / Pentium M ** ?c = think Core ** ?U = think Core Ultra ** ?d = think Pentium D ** ?S = think Scalable (Bronze/Silver/Gold/Platinum) */ #define dG (is_intel && !is_mobile && stash->br.generic) #define dP ((is_intel && stash->br.pentium) \ || stash->bri.desktop_pentium) #define dC ((is_intel && !is_mobile && stash->br.celeron) \ || stash->bri.desktop_celeron) #define da (is_intel && stash->br.atom) #define dd (is_intel && stash->br.pentium_d) #define dc (is_intel && !is_mobile && stash->br.core) #define dU (is_intel && !is_mobile && stash->br.core_ultra) #define sX ((is_intel && stash->br.xeon) || stash->bri.xeon) #define sM ((is_intel && stash->br.xeon_mp) \ || stash->bri.xeon_mp) #define sS (is_intel && stash->br.xeon && stash->br.scalable) #define MP ((is_intel && is_mobile && stash->br.pentium) \ || stash->bri.mobile_pentium) #define MC ((is_intel && is_mobile && stash->br.celeron) \ || stash->bri.mobile_celeron) #define MM ((is_intel && stash->br.pentium_m)\ || stash->bri.mobile_pentium_m) #define Mc (is_intel && is_mobile && stash->br.core) #define Xc (is_intel && stash->br.extreme) #define LU (is_intel && stash->br.u_line) #define LY (is_intel && stash->br.y_line) #define LG (is_intel && stash->br.g_line) #define UC (dC && stash->br.u_line) #define UP (dP && stash->br.u_line) #define YC (dC && stash->br.y_line) #define YP (dP && stash->br.y_line) #define d1 (is_intel && stash->br.cc150) #define iM (is_intel && stash->br.montage) /* ** Intel special cases */ /* Pentium II Xeon (Deschutes), distinguished from Pentium II (Deschutes) */ #define xD (stash->L2_4w_1Mor2M) /* Mobile Pentium II (Deschutes), distinguished from Pentium II (Deschutes) */ #define mD (stash->L2_4w_256K) /* Intel Celeron (Deschutes), distinguished from Pentium II (Deschutes) */ #define cD (!stash->L2_4w_1Mor2M && !stash->L2_4w_512K && !stash->L2_4w_256K) /* Pentium III Xeon (Katmai), distinguished from Pentium III (Katmai) */ #define xK (stash->L2_4w_1Mor2M || stash->L2_8w_1Mor2M) /* Pentium II (Katmai), verified, so distinguished from fallback case */ #define pK ((stash->L2_4w_512K || stash->L2_8w_256K || stash->L2_8w_512K) \ && !stash->L2_4w_1Mor2M && !stash->L2_8w_1Mor2M) /* Irwindale, distinguished from Nocona */ #define sI (sX && stash->L2_2M) /* Potomac, distinguished from Cranford */ #define sP (sM && stash->L3) /* Allendale, distinguished from Conroe */ #define dL (dc && stash->L2_2M) /* Dual-Core Xeon Processor 5100 (Woodcrest B1) pre-production, distinguished from Core 2 Duo (Conroe B1) */ #define QW (dG && stash->br.generic \ && (stash->mp.count[Core] == 4 \ || (stash->mp.count[Core] == 2 && stash->mp.count[Smt] == 2))) /* Core Duo (Yonah), distinguished from Core Solo (Yonah) */ #define DG (dG && stash->mp.count[Core] == 2) /* Core 2 Quad, distinguished from Core 2 Duo */ #define Qc (dc && stash->mp.count[Core] == 4) /* Core 2 Extreme (Conroe B1), distinguished from Core 2 Duo (Conroe B1) */ #define XE (dc && strstr(stash->brand, " E6800") != NULL) /* Quad-Core Xeon, distinguished from Xeon; and Xeon Processor 3300, distinguished from Xeon Processor 3100 */ #define sQ (sX && stash->mp.count[Core] == 4) /* Xeon Processor 7000, distinguished from Xeon */ #define IS_VMX(val_1_ecx) (BIT_EXTRACT_LE((val_1_ecx), 5, 6)) #define s7 (sX && IS_VMX(stash->val_1_ecx)) /* Wolfdale C0/E0, distinguished from Wolfdale M0/R0 */ #define de (dc && stash->L2_6M) /* Penryn C0/E0, distinguished from Penryn M0/R0 */ #define Me (Mc && stash->L2_6M) /* Yorkfield C1/E0, distinguished from Yorkfield M1/E0 */ #define Qe (Qc && stash->L2_6M) /* Yorkfield E0, distinguished from Yorkfield R0 */ #define se (sQ && stash->L2_6M) /* Amber Lake-Y, distinguished from Kaby Lake-Y */ #define Y8 (LY && stash->br.i_8000) /* Comet Lake V1, distinguished from Whiskey Lake V0 */ #define UX (LU && stash->br.i_10000) /* Hybrids: Lakefield: E-core (Tremont), distinguished from P-core (Sunny Cove) Alder Lake: E-core (Gracemont), distinguished from P-core (Golden Cove) Raptor Lake: E-core (Gracemont), distinguished from P-core (Raptor Cove) 0x1a/0/eax coretype == n/a (0x00) (used by some non-hybrid Alder Lake's) 0x1a/0/eax coretype == Atom (0x20) 0x1a/0/eax coretype == Core (0x40) */ #define HYBRID_CORE_TYPE(val_1a_0_eax) (BIT_EXTRACT_LE(val_1a_0_eax, 24, 32)) #define Hz (is_intel && HYBRID_CORE_TYPE(stash->val_1a_0_eax) == 0x00) #define Ha (is_intel && HYBRID_CORE_TYPE(stash->val_1a_0_eax) == 0x20) #define Hc (is_intel && HYBRID_CORE_TYPE(stash->val_1a_0_eax) == 0x40) /* Hybrid special case with Pentium Gold branding, instead of Core */ #define Pa (is_intel && stash->br.pentium && HYBRID_CORE_TYPE(stash->val_1a_0_eax) == 0x20) #define Pc (is_intel && stash->br.pentium && HYBRID_CORE_TYPE(stash->val_1a_0_eax) == 0x40) /* Hybrid special cases where "Core" implies a different branding than usual, such as the Core i3 N-Series */ #define Ia (is_intel && stash->br.core && HYBRID_CORE_TYPE(stash->val_1a_0_eax) == 0x20) #define Ic (is_intel && stash->br.core && HYBRID_CORE_TYPE(stash->val_1a_0_eax) == 0x40) /* ** AMD major queries: ** ** d? = think "desktop" ** s? = think "server" (MP) ** M? = think "mobile" ** S? = think "Series" ** T? = think "Tablet" ** A? = think "any" ** E? = think "Embedded" ** V? = think "Embedded V" ** R? = think "Embedded R" ** ** ?A = think Athlon ** ?X = think Athlon XP ** ?L = think Athlon XP (LV) ** ?E = think EPYC ** ?f = think FX ** ?F = think Athlon FX ** ?D = think Duron ** ?S = think Sempron ** ?O = think Opteron ** ?T = think Turion ** ?U = think Turion Ultra ** ?p = think Phenom ** ?R = think Ryzen ** ?H = think Threadripper ** ?s = think ?-Series ** ?n = think Turion Neo ** ?N = think Neo */ #define dA (is_amd && !is_mobile && stash->br.athlon) #define dX (is_amd && !is_mobile && stash->br.athlon_xp) #define dF (is_amd && !is_mobile && stash->br.athlon_fx) #define df (is_amd && !is_mobile && stash->br.fx) #define dD (is_amd && !is_mobile && stash->br.duron) #define dS (is_amd && !is_mobile && stash->br.sempron) #define dp (is_amd && !is_mobile && stash->br.phenom) #define dI (is_amd && !is_mobile && stash->br.firepro) #define dR (is_amd && !is_mobile && stash->br.ryzen) #define dH (is_amd && !is_mobile && stash->br.threadripper) #define sO (is_amd && !is_mobile && stash->br.opteron) #define sA (is_amd && !is_mobile && stash->br.athlon_mp) #define sD (is_amd && !is_mobile && stash->br.duron_mp) #define sE (is_amd && !is_mobile && stash->br.epyc) #define MA (is_amd && is_mobile && stash->br.athlon) #define MX (is_amd && is_mobile && stash->br.athlon_xp) #define ML (is_amd && is_mobile && stash->br.athlon_lv) #define MD (is_amd && is_mobile && stash->br.duron) #define MS (is_amd && is_mobile && stash->br.sempron) #define Mp (is_amd && is_mobile && stash->br.phenom) #define Ms (is_amd && is_mobile && stash->br.series) #define Mr (is_amd && is_mobile && stash->br.r_series) #define MG (is_amd && stash->br.geode) #define MT (is_amd && stash->br.turion) #define MU (is_amd && stash->br.ultra) #define Mn (is_amd && stash->br.turion && stash->br.neo) #define MN (is_amd && stash->br.neo) #define Sa (is_amd && !is_mobile && stash->br.a_series) #define Sc (is_amd && !is_mobile && stash->br.c_series) #define Se (is_amd && !is_mobile && stash->br.e_series) #define Sg (is_amd && !is_mobile && stash->br.g_series) #define Sr (is_amd && !is_mobile && stash->br.r_series) #define Sz (is_amd && !is_mobile && stash->br.z_series) #define Ta (is_amd && stash->br.t_suffix && stash->br.a_series) #define Te (is_amd && stash->br.t_suffix && stash->br.e_series) #define AR (is_amd && stash->br.ryzen) #define ER (is_amd && stash->br.ryzen && stash->br.embedded) #define VR (is_amd && stash->br.ryzen && stash->br.embedded_V) #define RR (is_amd && stash->br.ryzen && stash->br.embedded_R) #define EE (is_amd && stash->br.epyc_3000) /* ** AMD special cases */ static boolean is_amd_egypt_athens_8xx(const code_stash_t* stash) { /* ** This makes its determination based on the Processor model ** logic from: ** Revision Guide for AMD Athlon 64 and AMD Opteron Processors ** (25759 Rev 3.79), Constructing the Processor Name String. ** See also decode_amd_model(). */ if (stash->vendor == VENDOR_AMD && stash->br.opteron) { switch (MaskFM(stash->val_1_eax)) { case ShftFM(0,15, 2,1): /* Italy/Egypt */ case ShftFM(0,15, 2,5): /* Troy/Athens */ { unsigned int bti; if (MaskB(stash->val_1_ebx) != 0) { bti = BIT_EXTRACT_LE(MaskB(stash->val_1_ebx), 5, 8) << 2; } else if (BIT_EXTRACT_LE(stash->val_80000001_ebx, 0, 12) != 0) { bti = BIT_EXTRACT_LE(stash->val_80000001_ebx, 6, 12); } else { return FALSE; } switch (bti) { case 0x10: case 0x11: case 0x12: case 0x13: case 0x2a: case 0x30: case 0x31: case 0x39: case 0x3c: case 0x32: case 0x33: /* It's a 2xx */ return FALSE; case 0x14: case 0x15: case 0x16: case 0x17: case 0x2b: case 0x34: case 0x35: case 0x3a: case 0x3d: case 0x36: case 0x37: /* It's an 8xx */ return TRUE; } } } } return FALSE; } /* Embedded Opteron, distinguished from Opteron (Barcelona & Shanghai) */ #define EO (sO && stash->br.embedded) /* Opterons, distinguished by number of processors */ #define DO (sO && stash->br.cores == 2) #define SO (sO && stash->br.cores == 6) /* Athlons, distinguished by number of processors */ #define DA (dA && stash->br.cores == 2) #define TA (dA && stash->br.cores == 3) #define QA (dA && stash->br.cores == 4) /* Phenoms distinguished by number of processors */ #define Dp (dp && stash->br.cores == 2) #define Tp (dp && stash->br.cores == 3) #define Qp (dp && stash->br.cores == 4) #define Sp (dp && stash->br.cores == 6) /* Semprons, distinguished by number of processors */ #define DS (dS && stash->br.cores == 2) /* Egypt, distinguished from Italy; and Athens, distingushed from Troy */ #define s8 (sO && is_amd_egypt_athens_8xx(stash)) /* Thorton A2, distinguished from Barton A2 */ #define dt (dX && stash->L2_256K) /* Manchester E6, distinguished from from Toledo E6 */ #define dm (dA && stash->L2_512K) /* Propus, distinguished from Regor */ #define dr (dA && stash->L2_512K) /* Trinidad, distinguished from Taylor */ #define Mt (MT && stash->L2_512K) /* ** Cyrix major query */ #define cm (is_cyrix && stash->br.mediagx) /* ** VIA major query */ #define v7 (is_via && stash->br.c7) #define vM (is_via && stash->br.c7m) #define vD (is_via && stash->br.c7d) #define vE (is_via && stash->br.eden) #define vZ (is_via && stash->br.zhaoxin) /* ** Transmeta major queries ** ** t2 = TMx200 ** t4 = TMx400 ** t5 = TMx500 ** t6 = TMx600 ** t8 = TMx800 */ #define tm_rev(rev) (is_transmeta \ && (stash->transmeta_proc_rev & 0xffff0000) == rev) /* TODO: Add cases for Transmeta Crusoe TM5700/TM5900 */ /* TODO: Add cases for Transmeta Efficeon */ #define t2 (tm_rev(0x01010000)) #define t4 (tm_rev(0x01020000) || (tm_rev(0x01030000) && stash->L2_4w_256K)) #define t5 ((tm_rev(0x01040000) || tm_rev(0x01040000)) && stash->L2_4w_256K) #define t6 (tm_rev(0x01030000) && stash->L2_4w_512K) #define t8 ((tm_rev(0x01040000) || tm_rev(0x01040000)) && stash->L2_4w_512K) static cstring decode_vendor(vendor_t vendor, const code_stash_t* stash) { switch (vendor) { case VENDOR_INTEL: if (stash->br.montage) { return "Montage"; } else { return "Intel"; } case VENDOR_AMD: return "AMD"; case VENDOR_CYRIX: return "Cyrix"; case VENDOR_VIA: if (stash->br.zhaoxin) { return "Zhaoxin"; } else { return "VIA"; } case VENDOR_TRANSMETA: return "Transmeta"; case VENDOR_UMC: return "UMC"; case VENDOR_NEXGEN: return "NexGen"; case VENDOR_RISE: return "Rise"; case VENDOR_SIS: return "SiS"; case VENDOR_NSC: return "NSC"; case VENDOR_VORTEX: return "Vortex"; case VENDOR_RDC: return "RDC"; case VENDOR_HYGON: return "Hygon"; case VENDOR_ZHAOXIN: return "Zhaoxin"; case VENDOR_UNKNOWN: default: return NULL; } } #define ACT(...) (__VA_ARGS__) typedef struct { cstring uarch; // process-dependent name cstring family; // process-neutral name: // sometimes independent (e.g. Core) // sometimes based on lead uarch (e.g. Nehalem) cstring phys; // physical properties: die process, #pins, etc. boolean core_is_uarch; // for some uarches, the core names are based on the // uarch names, so the uarch name becomes redundant } arch_t; static void init_arch(arch_t* arch) { arch->uarch = NULL; arch->family = NULL; arch->phys = NULL; arch->core_is_uarch = FALSE; } static void decode_uarch_intel(unsigned int val, arch_t* arch, const code_stash_t* stash) { init_arch(arch); cstring* u = &arch->uarch; boolean* ciu = &arch->core_is_uarch; cstring* f = &arch->family; cstring* p = &arch->phys; // Intel calls "Whiskey Lake", "Amber Lake", and "Comet Lake" distinct // uarch's optimized from "Kaby Lake". That just leads to confusion and long // uarch names with slashes. Their families & models overlap, and just // differ based on brand (based on target market): // (0,6),(8,14),9 = Kaby Lake -or- Amber Lake-Y // (0,6),(8,14),11 = Whiskey Lake-U -or- Amber Lake-Y // (0,6),(8,14),12 = Whiskey Lake-U -or- Amber Lake-Y -or- Comet Lake-U // If the only way to distinguish two uarch's is by brand, I am skeptical // that they really are distinct uarch's! This is analogous to the multitude // of core names in pre-Sandy Bridge days. So I am treating those 3 as // distinct cores within the "Kaby Lake" uarch. This reduces the number of // uarches in the Skylake-based era to: // // [Skylake] = lead uarch in {Skylake} family // [Cascade Lake] = Skylake + DL Boost + spectre/meltdown fixes // [Cooper Lake] = Cascade Lake + bfloat16 + more cores // [Kaby Lake] = Skylake, 14nm+ (includes Whiskey, Amber, Comet) // [Coffee Lake] = Kaby Lake, 14nm++, 1.5x CPUs/die // [Palm Cove] = Coffee Lake, 10nm, AVX-512 // // That is a more manageable set. // START; F ( 0, 4, *f = "i486"); // *p depends on core FM ( 0, 5, 0, 0, *f = "P5", *p = ".8um"); FM ( 0, 5, 0, 1, *f = "P5", *p = ".8um"); FM ( 0, 5, 0, 2, *f = "P5"); FM ( 0, 5, 0, 3, *f = "P5", *p = ".6um"); FM ( 0, 5, 0, 4, *f = "P5 MMX"); FM ( 0, 5, 0, 7, *f = "P5 MMX"); FM ( 0, 5, 0, 8, *f = "P5 MMX", *p = ".25um"); FM ( 0, 5, 0, 9, *f = "P5 MMX"); FM ( 0, 6, 0, 0, *f = "P6 Pentium II"); FM ( 0, 6, 0, 1, *f = "P6 Pentium II"); // *p depends on core FM ( 0, 6, 0, 2, *f = "P6 Pentium II"); FM ( 0, 6, 0, 3, *f = "P6 Pentium II", *p = ".35um"); FM ( 0, 6, 0, 4, *f = "P6 Pentium II"); FM ( 0, 6, 0, 5, *f = "P6 Pentium II", *p = ".25um"); FM ( 0, 6, 0, 6, *f = "P6 Pentium II", *p = "L2 cache"); FM ( 0, 6, 0, 7, *f = "P6 Pentium III", *p = ".25um"); FM ( 0, 6, 0, 8, *f = "P6 Pentium III", *p = ".18um"); FM ( 0, 6, 0, 9, *f = "P6 Pentium M", *p = ".13um"); FM ( 0, 6, 0,10, *f = "P6 Pentium III", *p = ".18um"); FM ( 0, 6, 0,11, *f = "P6 Pentium III", *p = ".13um"); FM ( 0, 6, 0,13, *u = "Dothan", *f = "P6 Pentium M"); // *p depends on core FM ( 0, 6, 0,14, *u = "Yonah", *f = "P6 Pentium M", *p = "65nm"); FM ( 0, 6, 0,15, *u = "Merom", *f = "Core", *p = "65nm"); FM ( 0, 6, 1, 5, *u = "Dothan", *f = "P6 Pentium M", *p = "90nm"); FM ( 0, 6, 1, 6, *u = "Merom", *f = "Core", *p = "65nm"); FM ( 0, 6, 1, 7, *u = "Penryn", *f = "Core", *p = "45nm"); FM ( 0, 6, 1,10, *u = "Nehalem", *f = "Nehalem", *p = "45nm"); FM ( 0, 6, 1,12, *u = "Bonnell", *p = "45nm"); FM ( 0, 6, 1,13, *u = "Penryn", *f = "Core", *p = "45nm"); FM ( 0, 6, 1,14, *u = "Nehalem", *f = "Nehalem", *p = "45nm"); FM ( 0, 6, 1,15, *u = "Nehalem", *f = "Nehalem", *p = "45nm"); FM ( 0, 6, 2, 5, *u = "Westmere", *f = "shrink of Nehalem", *p = "32nm"); FM ( 0, 6, 2, 6, *u = "Bonnell", *p = "45nm"); FM ( 0, 6, 2, 7, *u = "Saltwell", *p = "32nm"); FM ( 0, 6, 2,10, *u = "Sandy Bridge", *ciu = TRUE, *f = "Sandy Bridge", *p = "32nm"); FM ( 0, 6, 2,12, *u = "Westmere", *f = "shrink of Nehalem", *p = "32nm"); FM ( 0, 6, 2,13, *u = "Sandy Bridge", *ciu = TRUE, *f = "Sandy Bridge", *p = "32nm"); FM ( 0, 6, 2,14, *u = "Nehalem", *f = "Nehalem", *p = "45nm"); FM ( 0, 6, 2,15, *u = "Westmere", *f = "shrink of Nehalem", *p = "32nm"); FM ( 0, 6, 3, 5, *u = "Saltwell", *p = "14nm"); FM ( 0, 6, 3, 6, *u = "Saltwell", *p = "32nm"); FM ( 0, 6, 3, 7, *u = "Silvermont", *p = "22nm"); FM ( 0, 6, 3,10, *u = "Ivy Bridge", *ciu = TRUE, *f = "shrink of Sandy Bridge", *p = "22nm"); FM ( 0, 6, 3,12, *u = "Haswell", *ciu = TRUE, *f = "Haswell", *p = "22nm"); FM ( 0, 6, 3,13, *u = "Broadwell", *ciu = TRUE, *f = "shrink of Haswell", *p = "14nm"); FM ( 0, 6, 3,14, *u = "Ivy Bridge", *ciu = TRUE, *f = "shrink of Sandy Bridge", *p = "22nm"); FM ( 0, 6, 3,15, *u = "Haswell", *ciu = TRUE, *f = "Haswell", *p = "22nm"); FM ( 0, 6, 4, 5, *u = "Haswell", *ciu = TRUE, *f = "Haswell", *p = "22nm"); FM ( 0, 6, 4, 6, *u = "Haswell", *ciu = TRUE, *f = "Haswell", *p = "22nm"); FM ( 0, 6, 4, 7, *u = "Broadwell", *ciu = TRUE, *f = "shrink of Haswell", *p = "14nm"); FM ( 0, 6, 4,10, *u = "Silvermont", *p = "22nm"); // no docs, but /proc/cpuinfo seen in wild FM ( 0, 6, 4,12, *u = "Airmont", *p = "14nm"); FM ( 0, 6, 4,13, *u = "Silvermont", *p = "22nm"); FMS ( 0, 6, 4,14, 8, *u = "Kaby Lake", *f = "optim of Skylake", *p = "14nm+"); FM ( 0, 6, 4,14, *u = "Skylake", *ciu = TRUE, *f = "Skylake", *p = "14nm"); FM ( 0, 6, 4,15, *u = "Broadwell", *ciu = TRUE, *f = "shrink of Haswell", *p = "14nm"); FMQ ( 0, 6, 5, 5, iM, *u = "Jintide Gen1", *ciu = TRUE, *f = "Intel Skylake"); // undocumented; only instlatx64 example FMS ( 0, 6, 5, 5, 6, *u = "Cascade Lake", *ciu = TRUE, *f = "optim of Skylake", *p = "14nm++"); // no docs, but example from Greg Stewart FMS ( 0, 6, 5, 5, 7, *u = "Cascade Lake", *ciu = TRUE, *f = "optim of Skylake", *p = "14nm++"); FMS ( 0, 6, 5, 5, 10, *u = "Cooper Lake", *ciu = TRUE, *f = "optim of Cascade Lake, optim of Skylake", *p = "14nm++"); FMS ( 0, 6, 5, 5, 11, *u = "Cooper Lake", *ciu = TRUE, *f = "optim of Cascade Lake, optim of Skylake", *p = "14nm++"); FM ( 0, 6, 5, 5, *u = "Skylake", *ciu = TRUE, *f = "Skylake", *p = "14nm"); FM ( 0, 6, 5, 6, *u = "Broadwell", *ciu = TRUE, *f = "shrink of Haswell", *p = "14nm"); FM ( 0, 6, 5, 7, *u = "Knights Landing", *ciu = TRUE, *p = "14nm"); FM ( 0, 6, 5,10, *u = "Silvermont", *p = "22nm"); // no spec update; only MSR_CPUID_table* so far FM ( 0, 6, 5,12, *u = "Goldmont", *p = "14nm"); // no spec update for Atom; only MSR_CPUID_table* so far FM ( 0, 6, 5,13, *u = "Silvermont", *p = "22nm"); // no spec update; only MSR_CPUID_table* so far FMS ( 0, 6, 5,14, 8, *u = "Kaby Lake", *f = "optim of Skylake", *p = "14nm+"); FM ( 0, 6, 5,14, *u = "Skylake", *ciu = TRUE, *f = "Skylake", *p = "14nm"); FM ( 0, 6, 5,15, *u = "Goldmont", *p = "14nm"); FM ( 0, 6, 6, 6, *u = "Palm Cove", *f = "Palm Cove", *p = "10nm"); // no spec update; only MSR_CPUID_table* so far FM ( 0, 6, 6, 7, *u = "Palm Cove", *f = "Palm Cove", *p = "10nm"); // DPTF* FM ( 0, 6, 6,10, *u = "Sunny Cove", *f = "Sunny Cove", *p = "10nm+"); FM ( 0, 6, 6,12, *u = "Sunny Cove", *f = "Sunny Cove", *p = "10nm+"); // no spec update; only MSR_CPUID_table* so far; DPTF* claims this is Meteor Lake S => Redwood Cove FM ( 0, 6, 6,14, *u = "Airmont", *p = "14nm"); // no spec update; only Intel's "Retpoline: A Branch Target Injection Mitigation" FM ( 0, 6, 7, 5, *u = "Airmont", *p = "14nm"); // no spec update; whispers & rumors FM ( 0, 6, 7,10, *u = "Goldmont Plus", *p = "14nm"); FM ( 0, 6, 7,13, *u = "Sunny Cove", *f = "Sunny Cove", *p = "10nm+"); // no spec update; only MSR_CPUID_table* so far FM ( 0, 6, 7,14, *u = "Sunny Cove", *f = "Sunny Cove", *p = "10nm+"); FM ( 0, 6, 8, 5, *u = "Knights Mill", *ciu = TRUE, *p = "14nm"); // no spec update; only MSR_CPUID_table* so far FM ( 0, 6, 8, 6, *u = "Tremont", *p = "10nm"); // LX* FMQ ( 0, 6, 8,10, Ha, *u = "Tremont", *p = "10nm"); // no spec update; LX* FMQ ( 0, 6, 8,10, Hc, *u = "Sunny Cove", *p = "10nm"); // no spec update; LX* FM ( 0, 6, 8,12, *u = "Willow Cove", *f = "optim of Sunny Cove", *p = "10nm++"); // no spec update; only MSR_CPUID_table* so far FM ( 0, 6, 8,13, *u = "Willow Cove", *f = "optim of Sunny Cove", *p = "10nm++"); // no spec update; only MSR_CPUID_table* so far FM ( 0, 6, 8,14, *u = "Kaby Lake", *f = "optim of Skylake", *p = "14nm+/14nm++"); FM ( 0, 6, 8,15, *u = "Sapphire Rapids", *ciu = TRUE, *f = "Golden Cove", *p = "Intel 7"); // LX* FM ( 0, 6, 9, 5, *u = "Sapphire Rapids", *ciu = TRUE, *f = "Golden Cove", *p = "Intel 7"); // Intel SDE 9.24.0 misc/cpuid/spr/cpuid.def FM ( 0, 6, 9, 6, *u = "Tremont", *p = "10nm"); // LX* FMQ ( 0, 6, 9, 7, Ha, *u = "Gracemont", *p = "Intel 7"); FMQ ( 0, 6, 9, 7, Hc, *u = "Golden Cove", *p = "Intel 7"); FMQ ( 0, 6, 9, 7, Hz, *u = "Golden Cove", *p = "Intel 7"); FMQ ( 0, 6, 9,10, Ha, *u = "Gracemont", *p = "Intel 7"); // Coreboot* FMQ ( 0, 6, 9,10, Hc, *u = "Golden Cove", *p = "Intel 7"); // Coreboot* FM ( 0, 6, 9,12, *u = "Tremont", *p = "10nm"); // LX* FM ( 0, 6, 9,13, *u = "Sunny Cove", *f = "Sunny Cove", *p = "10nm+"); // LX* FMS ( 0, 6, 9,14, 9, *u = "Kaby Lake", *f = "optim of Skylake", *p = "14nm+"); FMS ( 0, 6, 9,14, 10, *u = "Coffee Lake", *ciu = TRUE, *f = "optim of Kaby Lake, optim of Skylake", *p = "14nm++"); FMS ( 0, 6, 9,14, 11, *u = "Coffee Lake", *ciu = TRUE, *f = "optim of Kaby Lake, optim of Skylake", *p = "14nm++"); FMS ( 0, 6, 9,14, 12, *u = "Coffee Lake", *ciu = TRUE, *f = "optim of Kaby Lake, optim of Skylake", *p = "14nm++"); FMS ( 0, 6, 9,14, 13, *u = "Coffee Lake", *ciu = TRUE, *f = "optim of Kaby Lake, optim of Skylake", *p = "14nm++"); FM ( 0, 6, 9,14, *u = "Kaby Lake / Coffee Lake", *f = "optim of Skylake", *p = "14nm+/14nm++"); FM ( 0, 6, 9,15, *u = "Sunny Cove", *f = "Sunny Cove", *p = "10nm+"); // undocumented, but (engr?) sample via instlatx64 from Komachi_ENSAKA FM ( 0, 6, 10, 5, *u = "Kaby Lake", *f = "optim of Skylake", *p = "14nm+++"); // LX* FM ( 0, 6, 10, 6, *u = "Kaby Lake", *f = "optim of Skylake", *p = "14nm+++"); // no spec update; only instlatx64 example FM ( 0, 6, 10, 7, *u = "Cypress Cove", *f = "backport of Sunny Cove", *p = "14nm+++"); // LX* FM ( 0, 6, 10, 8, *u = "Cypress Cove", *f = "backport of Sunny Cove", *p = "14nm+++"); // undocumented, but (engr?) sample via instlatx64 from Komachi_ENSAKA FMQ ( 0, 6, 10,10, Ha, *u = "Crestmont", *p = "Intel 4"); // MSR_CPUID_table*; DPTF*, LX* (but -L); (engr?) sample via instlatx64 from Komachi_ENSAKA FMQ ( 0, 6, 10,10, Hc, *u = "Redwood Cove", *f = "shrink of Raptor Cove, optim of Golden Cove", *p = "Intel 4"); // MSR_CPUID_table*; DPTF*, LX* (but -L); (engr?) sample via instlatx64 from Komachi_ENSAKA FMQ ( 0, 6, 10,11, Ha, *u = "Crestmont", *p = "Intel 4"); // DPTF* FMQ ( 0, 6, 10,11, Hc, *u = "Redwood Cove", *f = "shrink of Raptor Cove, optim of Golden Cove", *p = "Intel 4"); // DPTF* FMQ ( 0, 6, 10,12, Ha, *u = "Crestmont", *p = "Intel 4"); // MSR_CPUID_table*; (engr?) sample via instlatx64 from Komachi_ENSAKA FMQ ( 0, 6, 10,12, Hc, *u = "Redwood Cove", *f = "shrink of Raptor Cove, optim of Golden Cove", *p = "Intel 4"); // MSR_CPUID_table*; (engr?) sample via instlatx64 from Komachi_ENSAKA FM ( 0, 6, 10,13, *u = "Granite Rapids", *ciu = TRUE, *f = "Redwood Cove, shrink of Raptor Cove, optim of Golden Cove", *p = "Intel 4"); // MSR_CPUID_table*; LX*; (engr?) sample via instlatx64 from Komachi_ENSAKA FM ( 0, 6, 10,14, *u = "Granite Rapids", *ciu = TRUE, *f = "Redwood Cove, shrink of Raptor Cove, optim of Golden Cove", *p = "Intel 4"); // MSR_CPUID_table*; LX* FM ( 0, 6, 10,15, *u = "Crestmont", *p = "Intel 3"); // MSR_CPUID_table*; LX*; (engr?) sample via instlatx64 from Komachi_ENSAKA FMQ ( 0, 6, 11, 5, Ha, *u = "Skymont", *p = "TSMC N3B"); // MSR_CPUID_table* FMQ ( 0, 6, 11, 5, Hc, *u = "Lion Cove", *p = "TSMC N3B"); // MSR_CPUID_table* FM ( 0, 6, 11, 6, *u = "Crestmont", *p = "Intel 7"); // MSR_CPUID_table*; LX*; SSG* specifies Crestmont FMQ ( 0, 6, 11, 7, Ha, *u = "Gracemont", *p = "Intel 7"); // MSR_CPUID_table*; LX*; DPTF* FMQ ( 0, 6, 11, 7, Hc, *u = "Raptor Cove", *f = "optim of Golden Cove", *p = "Intel 7"); // MSR_CPUID_table*; LX*; DPTF* FMQ ( 0, 6, 11,10, Ha, *u = "Gracemont", *p = "Intel 7"); // DPTF*; Coreboot* FMQ ( 0, 6, 11,10, Hc, *u = "Raptor Cove", *f = "optim of Golden Cove", *p = "Intel 7"); // DPTF*; Coreboot* FMQ ( 0, 6, 11,12, Ha, *u = "Skymont", *p = "Intel 18A"); FMQ ( 0, 6, 11,12, Hc, *u = "Lion Cove", *p = "Intel 18A"); FMQ ( 0, 6, 11,13, Ha, *u = "Skymont", *p = "TSMC N3B"); FMQ ( 0, 6, 11,13, Hc, *u = "Lion Cove", *p = "TSMC N3B"); FMQ ( 0, 6, 11,14, Ha, *u = "Gracemont", *p = "Intel 7"); FMQ ( 0, 6, 11,14, Hc, *u = "Golden Cove", *p = "Intel 7"); // possibly no P-cores ever for this model FMQ ( 0, 6, 11,15, Ha, *u = "Gracemont", *p = "Intel 7"); // MSR_CPUID_table* FMQ ( 0, 6, 11,15, Hc, *u = "Raptor Cove", *f = "optim of Golden Cove", *p = "Intel 7"); // MSR_CPUID_table* FMQ ( 0, 6, 12, 5, Ha, *u = "Skymont", *p = "TSMC N3"); FMQ ( 0, 6, 12, 5, Hc, *u = "Lion Cove", *p = "TSMC N3"); FMQ ( 0, 6, 12, 6, Ha, *u = "Skymont", *p = "TSMC N3"); FMQ ( 0, 6, 12, 6, Hc, *u = "Lion Cove", *p = "TSMC N3"); // Whatever uarch namess are correct for (0,6),(12,12) Panther Lake (expect Intel 18A) FM ( 0, 6, 12,15, *u = "Emerald Rapids", *ciu = TRUE, *f = "Raptor Cove, optim of Golden Cove", *p = "Intel 7"); // MSR_CPUID_table*; LX* FM ( 0, 6, 13,13, *u = "Darkmont", *p = "Intel 18A"); // MSR_CPUID_table*; LX* F ( 0, 7, *u = "Itanium"); FM ( 0,11, 0, 0, *u = "Knights Ferry", *ciu = TRUE, *f = "K1OM", *p = "45nm"); // found only on en.wikichip.org FM ( 0,11, 0, 1, *u = "Knights Corner", *ciu = TRUE, *f = "K1OM", *p = "22nm"); FM ( 0,15, 0, 0, *u = "Willamette", *f = "Netburst", *p = ".18um"); FM ( 0,15, 0, 1, *u = "Willamette", *f = "Netburst", *p = ".18um"); FM ( 0,15, 0, 2, *u = "Northwood", *f = "Netburst", *p = ".13um"); FM ( 0,15, 0, 3, *u = "Prescott", *f = "Netburst", *p = "90nm"); FM ( 0,15, 0, 4, *u = "Prescott", *f = "Netburst", *p = "90nm"); FM ( 0,15, 0, 6, *u = "Cedar Mill", *f = "Netburst", *p = "65nm"); F ( 0,15, *f = "Netburst"); FM ( 1,15, 0, 0, *u = "Itanium2", *p = ".18um"); FM ( 1,15, 0, 1, *u = "Itanium2", *p = ".13um"); FM ( 1,15, 0, 2, *u = "Itanium2", *p = ".13um"); F ( 1,15, *u = "Itanium2"); F ( 2, 0, *u = "Itanium2", *p = "90nm"); F ( 2, 1, *u = "Itanium2"); FM ( 4,15, 0, 0, *u = "Panther Cove", *p = "Intel 18A"); // MSR_CPUID_table* (-054, quickly retracted in -055), LX* FM ( 4,15, 0, 1, *u = "Panther Cove", *p = "Intel 18A"); // MSR_CPUID_table*, LX* DEFAULT ((void)NULL); } static void decode_uarch_amd(unsigned int val, arch_t* arch) { init_arch(arch); cstring* u = &arch->uarch; cstring* p = &arch->phys; START; FM ( 0, 4, 0, 3, *u = "Am486"); FM ( 0, 4, 0, 7, *u = "Am486"); FM ( 0, 4, 0, 8, *u = "Am486"); FM ( 0, 4, 0, 9, *u = "Am486"); F ( 0, 4, *u = "Am5x86"); FM ( 0, 5, 0, 6, *u = "K6", *p = ".30um"); FM ( 0, 5, 0, 7, *u = "K6", *p = ".25um"); // *p from sandpile.org FM ( 0, 5, 0,13, *u = "K6", *p = ".18um"); // *p from sandpile.org F ( 0, 5, *u = "K6"); FM ( 0, 6, 0, 1, *u = "K7", *p = ".25um"); FM ( 0, 6, 0, 2, *u = "K7", *p = ".18um"); F ( 0, 6, *u = "K7"); FMS ( 0,15, 0, 4, 8, *u = "K8", *p = "754-pin, .13um"); FM ( 0,15, 0, 4, *u = "K8", *p = "940-pin, .13um"); FM ( 0,15, 0, 5, *u = "K8", *p = "940-pin, .13um"); FM ( 0,15, 0, 7, *u = "K8", *p = "939-pin, .13um"); FM ( 0,15, 0, 8, *u = "K8", *p = "754-pin, .13um"); FM ( 0,15, 0,11, *u = "K8", *p = "939-pin, .13um"); FM ( 0,15, 0,12, *u = "K8", *p = "754-pin, .13um"); FM ( 0,15, 0,14, *u = "K8", *p = "754-pin, .13um"); FM ( 0,15, 0,15, *u = "K8", *p = "939-pin, .13um"); FM ( 0,15, 1, 4, *u = "K8", *p = "754-pin, 90nm"); FM ( 0,15, 1, 5, *u = "K8", *p = "940-pin, 90nm"); FM ( 0,15, 1, 7, *u = "K8", *p = "939-pin, 90nm"); FM ( 0,15, 1, 8, *u = "K8", *p = "754-pin, 90nm"); FM ( 0,15, 1,11, *u = "K8", *p = "939-pin, 90nm"); FM ( 0,15, 1,12, *u = "K8", *p = "754-pin, 90nm"); FM ( 0,15, 1,15, *u = "K8", *p = "939-pin, 90nm"); FM ( 0,15, 2, 1, *u = "K8", *p = "940-pin, 90nm"); FM ( 0,15, 2, 3, *u = "K8", *p = "939-pin, 90nm"); FM ( 0,15, 2, 4, *u = "K8", *p = "754-pin, 90nm"); FM ( 0,15, 2, 5, *u = "K8", *p = "940-pin, 90nm"); FM ( 0,15, 2, 7, *u = "K8", *p = "939-pin, 90nm"); FM ( 0,15, 2,11, *u = "K8", *p = "939-pin, 90nm"); FM ( 0,15, 2,12, *u = "K8", *p = "754-pin, 90nm"); FM ( 0,15, 2,15, *u = "K8", *p = "939-pin, 90nm"); FM ( 0,15, 4, 1, *u = "K8", *p = "90nm"); FM ( 0,15, 4, 3, *u = "K8", *p = "90nm"); FM ( 0,15, 4, 8, *u = "K8", *p = "90nm"); FM ( 0,15, 4,11, *u = "K8", *p = "90nm"); FM ( 0,15, 4,12, *u = "K8", *p = "90nm"); FM ( 0,15, 4,15, *u = "K8", *p = "90nm"); FM ( 0,15, 5,13, *u = "K8", *p = "90nm"); FM ( 0,15, 5,15, *u = "K8", *p = "90nm"); FM ( 0,15, 6, 8, *u = "K8", *p = "65nm"); FM ( 0,15, 6,11, *u = "K8", *p = "65nm"); FM ( 0,15, 6,12, *u = "K8", *p = "65nm"); FM ( 0,15, 6,15, *u = "K8", *p = "65nm"); FM ( 0,15, 7,12, *u = "K8", *p = "65nm"); FM ( 0,15, 7,15, *u = "K8", *p = "65nm"); FM ( 0,15, 12, 1, *u = "K8", *p = "90nm"); FM ( 1,15, 0, 0, *u = "K10", *p = "65nm"); // sandpile.org FM ( 1,15, 0, 2, *u = "K10", *p = "65nm"); FM ( 1,15, 0, 4, *u = "K10", *p = "45nm"); FM ( 1,15, 0, 5, *u = "K10", *p = "45nm"); FM ( 1,15, 0, 6, *u = "K10", *p = "45nm"); FM ( 1,15, 0, 8, *u = "K10", *p = "45nm"); FM ( 1,15, 0, 9, *u = "K10", *p = "45nm"); FM ( 1,15, 0,10, *u = "K10", *p = "45nm"); F ( 2,15, *u = "Puma 2008", *p = "65nm"); F ( 3,15, *u = "K10", *p = "32nm"); F ( 5,15, *u = "Bobcat", *p = "40nm"); FM ( 6,15, 0, 0, *u = "Bulldozer", *p = "32nm"); // instlatx64 engr sample FM ( 6,15, 0, 1, *u = "Bulldozer", *p = "32nm"); FM ( 6,15, 0, 2, *u = "Piledriver", *p = "32nm"); FM ( 6,15, 1, 0, *u = "Piledriver", *p = "32nm"); FM ( 6,15, 1, 3, *u = "Piledriver", *p = "32nm"); FM ( 6,15, 3, 0, *u = "Steamroller", *p = "28nm"); FM ( 6,15, 3, 8, *u = "Steamroller", *p = "28nm"); FM ( 6,15, 4, 0, *u = "Steamroller", *p = "28nm"); // Software Optimization Guide (15h) says it has the same inst latencies as (6,15),(3,x). FM ( 6,15, 6, 0, *u = "Excavator", *p = "28nm"); // undocumented, but instlatx64 samples FM ( 6,15, 6, 5, *u = "Excavator", *p = "28nm"); // undocumented, but sample from Alexandros Couloumbis FM ( 6,15, 7, 0, *u = "Excavator", *p = "28nm"); FM ( 7,15, 0, 0, *u = "Jaguar", *p = "28nm"); FM ( 7,15, 2, 6, *u = "Cato", *p = "28nm"); // only instlatx64 example; engr sample? FM ( 7,15, 3, 0, *u = "Puma 2014", *p = "28nm"); // In Zen-based CPUs, the model uses only the extended model and the // high-order bit of the model. The low-order 3 bits of the model are part // of the stepping. FMm ( 8,15, 0, 0, *u = "Zen", *p = "14nm"); FMm ( 8,15, 0, 8, *u = "Zen+", *p = "12nm"); FMm ( 8,15, 1, 0, *u = "Zen", *p = "14nm"); // found only on en.wikichip.org & instlatx64 examples FMm ( 8,15, 1, 8, *u = "Zen+", *p = "12nm"); FMm ( 8,15, 2, 0, *u = "Zen", *p = "14nm"); FMm ( 8,15, 3, 0, *u = "Zen 2", *p = "7nm"); // found only on en.wikichip.org FMm ( 8,15, 4, 0, *u = "Zen 2", *p = "7nm"); // only instlatx64 example; engr sample? FMm ( 8,15, 6, 0, *u = "Zen 2", *p = "7nm"); FMm ( 8,15, 6, 8, *u = "Zen 2", *p = "7nm"); // undocumented, but instlatx64 samples FMm ( 8,15, 7, 0, *u = "Zen 2", *p = "7nm"); // undocumented, but samples from Steven Noonan FMm ( 8,15, 8, 0, *u = "Zen 2", *p = "7nm"); // undocumented, but sample via instlatx64 FMm ( 8,15, 9, 0, *u = "Zen 2", *p = "7nm"); // undocumented, but sample via instlatx64 from @patrickschur_ FMm ( 8,15, 9, 8, *u = "Zen 2", *p = "7nm"); // undocumented, but sample via instlatx64 from @zimogorets FMm ( 8,15, 10, 0, *u = "Zen 2", *p = "7nm"); // sample via instlatx64 from @ExecuFix FMm (10,15, 0, 0, *u = "Zen 3", *p = "TSMC 7nm"); FMm (10,15, 0, 8, *u = "Zen 3", *p = "TSMC 7nm"); // undocumented, but sample via instlatx64 from @ExecuFix FMm (10,15, 1, 0, *u = "Zen 4", *p = "TSMC N5"); FMm (10,15, 1, 8, *u = "Zen 4", *p = "TSMC 5FF"); // undocumented, but sample via instlatx64 from @patrickschur_ FMm (10,15, 2, 0, *u = "Zen 3", *p = "TSMC 7FF"); FMm (10,15, 3, 0, *u = "Zen 3", *p = "TSMC N5P"); // undocumented, but sample via instlatx64 from @patrickschur_ FMm (10,15, 4, 0, *u = "Zen 3", *p = "TSMC N6"); // undocumented, but instlatx64 sample FMm (10,15, 5, 0, *u = "Zen 3", *p = "TSMC 7nm"); FMm (10,15, 6, 0, *u = "Zen 4", *p = "TSMC N5"); // undocumented, but instlatx64 sample FMm (10,15, 7, 0, *u = "Zen 4", *p = "TSMC 4nm"); // undocumented, but engr sample via instlatx64 from bakerlab.org (6220795) FMm (10,15, 7, 8, *u = "Zen 4", *p = "TSMC 4nm"); // Coreboot* FMm (10,15, 8, 0, *u = "Zen 4", *p = "TSMC N5"); // undocumented, but LKML: https://lkml.org/lkml/2023/7/21/835 from AMD's Yazen Ghannam FMm (10,15, 9, 0, *u = "Zen 4", *p = "TSMC N5"); // undocumented, but LKML: https://lkml.org/lkml/2023/7/21/835 from AMD's Yazen Ghannam FMm (10,15, 10, 0, *u = "Zen 4c", *p = "TSMC N5"); FMm (11,15, 0, 0, *u = "Zen 5", *p = "TSMC N4P"); // LX* & tangentially documented: 58088 AMD 1Ah Models 00h-0Fh and Models 10h-1Fh ACPI v6.5 Porting Guide FMm (11,15, 0, 8, *u = "Zen 5", *p = "TSMC N4P"); // undocumented, but LLVM patch from AMD's Ganesh Gopalasubramanian FMm (11,15, 1, 0, *u = "Zen 5c", *p = "TSMC N3"); // tangentially documented: 58088 AMD 1Ah Models 00h-0Fh and Models 10h-1Fh ACPI v6.5 Porting Guide FMm (11,15, 1, 8, *u = "Zen 5c", *p = "TSMC N3"); // undocumented, but LLVM patch from AMD's Ganesh Gopalasubramanian FMm (11,15, 2, 0, *u = "Zen 5", *p = "TSMC N4P"); // undocumented, but engr sample via instlatx64 from milkyway.cs.rpi.edu (996435) FMm (11,15, 2, 8, *u = "Zen 5", *p = "TSMC N4P"); // undocumented, but LLVM patch from AMD's Ganesh Gopalasubramanian FMm (11,15, 3, 0, *u = "Zen 5", *p = "TSMC N4P"); // undocumented, but LLVM patch from AMD's Ganesh Gopalasubramanian FMm (11,15, 3, 8, *u = "Zen 5", *p = "TSMC N4P"); // undocumented, but LLVM patch from AMD's Ganesh Gopalasubramanian FMm (11,15, 4, 0, *u = "Zen 5", *p = "TSMC N4P"); // undocumented, but LX* & engr sample via instlatx64 from einsteinathome.org (13142934) FMm (11,15, 4, 8, *u = "Zen 5", *p = "TSMC N4P"); // undocumented, but LLVM patch from AMD's Ganesh Gopalasubramanian FMm (11,15, 5, 0, *u = "Zen 5", *p = "TSMC N4P"); // undocumented, but LLVM patch from AMD's Ganesh Gopalasubramanian FMm (11,15, 5, 8, *u = "Zen 5", *p = "TSMC N4P"); // undocumented, but LLVM patch from AMD's Ganesh Gopalasubramanian FMm (11,15, 6, 0, *u = "Zen 5", *p = "TSMC N4P"); // undocumented, but engr sample via instlatx64 from @kepler_l2 FMm (11,15, 6, 8, *u = "Zen 5", *p = "TSMC N4P"); // undocumented, but LLVM patch from AMD's Ganesh Gopalasubramanian FMm (11,15, 7, 0, *u = "Zen 5", *p = "TSMC N4P"); // undocumented, but LX* & engr sample via instlatx64 from @kepler_l2 FMm (11,15, 7, 8, *u = "Zen 5", *p = "TSMC N4P"); // undocumented, but LLVM patch from AMD's Ganesh Gopalasubramanian DEFAULT ((void)NULL); } static void decode_uarch_cyrix(unsigned int val, arch_t* arch) { init_arch(arch); cstring* u = &arch->uarch; boolean* ciu = &arch->core_is_uarch; START; F (0, 5, *u = "M1", *ciu = TRUE); F (0, 6, *u = "M2", *ciu = TRUE); DEFAULT ((void)NULL); } static void decode_uarch_via(unsigned int val, arch_t* arch, const code_stash_t* stash) { init_arch(arch); cstring* u = &arch->uarch; boolean* ciu = &arch->core_is_uarch; cstring* f = &arch->family; cstring* p = &arch->phys; START; F (0, 5, *u = "WinChip", *ciu = TRUE); FM (0, 6, 0, 6, *u = "C3", *ciu = TRUE, *p = ".18um"); FM (0, 6, 0, 7, *u = "C3", *ciu = TRUE); // *p depends on core FM (0, 6, 0, 8, *u = "C3", *ciu = TRUE, *p = ".13um"); FM (0, 6, 0, 9, *u = "C3", *ciu = TRUE, *p = ".13um"); FM (0, 6, 0,10, *u = "C7", *p = "90nm"); FM (0, 6, 0,13, *u = "C7", *p = "90nm"); FMSQ(0, 6, 0,15, 14, vZ, *u = "ZhangJiang", *f = "VIA C7", *p = "28nm"); FM (0, 6, 0,15, *u = "C7"); // *p depends on core FMQ (0, 6, 1, 9, vZ, *u = "ZhangJiang", *f = "VIA C7", *p = "28nm"); // Google_cpu_features* FM (0, 6, 4, 7, *u = "CNS", *p = "16nm"); FM (0, 7, 0,11, *u = "WuDaoKou", *p = "28nm"); FM (0, 7, 1,11, *u = "WuDaoKou", *p = "28nm"); // Google_cpu_features* FM (0, 7, 3,11, *u = "LuJiaZui", *p = "16nm"); // Google_cpu_features* FM (0, 7, 5,11, *u = "YongFeng", *p = "7nm"); // Google_cpu_features* (speculative?) DEFAULT ((void)NULL); } static void decode_uarch_umc(unsigned int val, arch_t* arch) { init_arch(arch); cstring* u = &arch->uarch; boolean* ciu = &arch->core_is_uarch; START; F (0, 4, *u = "486 U5", *ciu = TRUE); DEFAULT ((void)NULL); } static void decode_uarch_nexgen(unsigned int val, arch_t* arch) { init_arch(arch); cstring* u = &arch->uarch; START; F (0, 5, *u = "Nx586"); DEFAULT ((void)NULL); } static void decode_uarch_rise(unsigned int val, arch_t* arch) { init_arch(arch); cstring* u = &arch->uarch; boolean* ciu = &arch->core_is_uarch; START; F (0, 5, *u = "mP6", *ciu = TRUE); DEFAULT ((void)NULL); } static void decode_uarch_transmeta(unsigned int val, arch_t* arch) { init_arch(arch); cstring* u = &arch->uarch; boolean* ciu = &arch->core_is_uarch; START; F (0, 5, *u = "Crusoe", *ciu = TRUE); F (0,15, *u = "Efficeon", *ciu = TRUE); DEFAULT ((void)NULL); } static void decode_uarch_sis(unsigned int val, arch_t* arch) { init_arch(arch); cstring* u = &arch->uarch; boolean* ciu = &arch->core_is_uarch; START; F (0, 5, *u = "mP6", *ciu = TRUE); DEFAULT ((void)NULL); } static void decode_uarch_hygon(unsigned int val, arch_t* arch) { init_arch(arch); cstring* u = &arch->uarch; cstring* f = &arch->family; cstring* p = &arch->phys; START; F (9,15, *u = "Moksha", *f = "AMD Zen", *p = "14nm"); DEFAULT ((void)NULL); } static void decode_uarch_zhaoxin(unsigned int val, arch_t* arch) { init_arch(arch); cstring* u = &arch->uarch; boolean* ciu = &arch->core_is_uarch; cstring* p = &arch->phys; START; FM (0, 7, 1,11, *u = "WuDaoKou", *ciu = TRUE, *p = "28nm"); FM (0, 7, 3,11, *u = "LuJiaZui", *ciu = TRUE, *p = "16nm"); DEFAULT ((void)NULL); } #undef ACT static void decode_uarch(unsigned int val, vendor_t vendor, const code_stash_t* stash, arch_t* arch) { init_arch(arch); switch (vendor) { case VENDOR_INTEL: decode_uarch_intel(val, arch, stash); break; case VENDOR_AMD: decode_uarch_amd(val, arch); break; case VENDOR_CYRIX: decode_uarch_cyrix(val, arch); break; case VENDOR_VIA: decode_uarch_via(val, arch, stash); break; case VENDOR_TRANSMETA: decode_uarch_transmeta(val, arch); break; case VENDOR_UMC: decode_uarch_umc(val, arch); break; case VENDOR_NEXGEN: decode_uarch_nexgen(val, arch); break; case VENDOR_RISE: decode_uarch_rise(val, arch); break; case VENDOR_SIS: decode_uarch_sis(val, arch); break; case VENDOR_HYGON: decode_uarch_hygon(val, arch); break; case VENDOR_ZHAOXIN: decode_uarch_zhaoxin(val, arch); break; case VENDOR_NSC: case VENDOR_VORTEX: case VENDOR_RDC: case VENDOR_UNKNOWN: break; } } static void print_uarch(const code_stash_t* stash) { arch_t arch; decode_uarch(stash->val_1_eax, stash->vendor, stash, &arch); if (arch.uarch != NULL || arch.family != NULL || arch.phys != NULL) { ccstring vendor = decode_vendor(stash->vendor, stash); printf(" (uarch synth) ="); if (vendor != NULL) { printf(" %s", vendor); } if (arch.uarch != NULL) { printf(" %s", arch.uarch); } if (arch.family != NULL) { printf(" {%s}", arch.family); } if (arch.phys != NULL) { printf(", %s", arch.phys); } printf("\n"); } } static cstring append_uarch(ccstring synth, unsigned int val, vendor_t vendor, const code_stash_t* stash) { if (synth != NULL) { arch_t arch; decode_uarch(val, vendor, stash, &arch); if ((arch.uarch != NULL && !arch.core_is_uarch) || arch.family != NULL || arch.phys != NULL) { static char buffer[1024]; char* ptr = buffer; ptr += sprintf(ptr, "%s", synth); if (arch.uarch != NULL && !arch.core_is_uarch) { ptr += sprintf(ptr, " [%s]", arch.uarch); } if (arch.family != NULL) { ptr += sprintf(ptr, " {%s}", arch.family); } if (arch.phys != NULL) { ptr += sprintf(ptr, ", %s", arch.phys); } return buffer; } } return synth; } static void debug_queries(const code_stash_t* stash) { #define DEBUGQ(q) printf("%s = %s\n", #q, (q) ? "TRUE" : "FALSE") #define DEBUGF(f) printf("%s = %s\n", #f, f(stash) ? "TRUE" : "FALSE") DEBUGQ(is_intel); DEBUGQ(is_amd); DEBUGQ(is_transmeta); DEBUGQ(is_mobile); DEBUGQ(MC); DEBUGQ(Mc); DEBUGQ(MP); DEBUGQ(sM); DEBUGQ(sX); DEBUGQ(dC); DEBUGQ(da); DEBUGQ(MM); DEBUGQ(dd); DEBUGQ(dP); DEBUGQ(Xc); DEBUGQ(dc); DEBUGQ(dG); DEBUGQ(xD); DEBUGQ(mD); DEBUGQ(cD); DEBUGQ(xK); DEBUGQ(pK); DEBUGQ(sI); DEBUGQ(sP); DEBUGQ(dL); DEBUGQ(QW); DEBUGQ(DG); DEBUGQ(Qc); DEBUGQ(XE); DEBUGQ(sQ); DEBUGQ(s7); DEBUGQ(de); DEBUGQ(Me); DEBUGQ(Qe); DEBUGQ(se); DEBUGQ(dp); DEBUGQ(dX); DEBUGQ(dF); DEBUGQ(df); DEBUGQ(dD); DEBUGQ(dS); DEBUGQ(dR); DEBUGQ(sO); DEBUGQ(sA); DEBUGQ(sD); DEBUGQ(sE); DEBUGQ(dD); DEBUGQ(dA); DEBUGQ(dS); DEBUGQ(ML); DEBUGQ(MX); DEBUGQ(MD); DEBUGQ(MA); DEBUGQ(MS); DEBUGQ(Mp); DEBUGQ(Ms); DEBUGQ(MG); DEBUGQ(MT); DEBUGQ(Mn); DEBUGQ(MN); DEBUGQ(Sa); DEBUGF(is_amd_egypt_athens_8xx); DEBUGQ(EO); DEBUGQ(DO); DEBUGQ(SO); DEBUGQ(DA); DEBUGQ(TA); DEBUGQ(QA); DEBUGQ(Dp); DEBUGQ(Tp); DEBUGQ(Qp); DEBUGQ(Sp); DEBUGQ(DS); DEBUGQ(s8); DEBUGQ(dt); DEBUGQ(dm); DEBUGQ(dr); DEBUGQ(Mt); DEBUGQ(t2); DEBUGQ(t4); DEBUGQ(t5); DEBUGQ(t6); DEBUGQ(t8); #undef DEBUGQ #undef DEBUGF } #define ACT(str) (result = (str)) static cstring decode_synth_intel(unsigned int val, /* val_1_eax */ const code_stash_t* stash) { cstring result = NULL; START; FM ( 0, 4, 0, 0, "Intel i80486DX-25/33, .18um"); // process from sandpile.org FM ( 0, 4, 0, 1, "Intel i80486DX-50, .18um"); // process from sandpile.org FM ( 0, 4, 0, 2, "Intel i80486SX, .18um"); // process from sandpile.org FM ( 0, 4, 0, 3, "Intel i80486DX/2"); FM ( 0, 4, 0, 4, "Intel i80486SL, .8um"); FM ( 0, 4, 0, 5, "Intel i80486SX/2, .8um"); FM ( 0, 4, 0, 7, "Intel i80486DX/2-WB, .8um"); FM ( 0, 4, 0, 8, "Intel i80486DX/4, .6um"); FM ( 0, 4, 0, 9, "Intel i80486DX/4-WB, .6um"); F ( 0, 4, "Intel i80486 (unknown model)"); FM ( 0, 5, 0, 0, "Intel Pentium 60/66 A-step"); // no docs // Intel docs (243326). TFM (1, 0, 5, 0, 1, "Intel Pentium 60/66 OverDrive for P5"); FMS ( 0, 5, 0, 1, 3, "Intel Pentium 60/66 (B1)"); FMS ( 0, 5, 0, 1, 5, "Intel Pentium 60/66 (C1)"); FMS ( 0, 5, 0, 1, 7, "Intel Pentium 60/66 (D1)"); FM ( 0, 5, 0, 1, "Intel Pentium 60/66"); // Intel docs (242480). TFM (1, 0, 5, 0, 2, "Intel Pentium 75 - 200 OverDrive for P54C"); FMS ( 0, 5, 0, 2, 1, "Intel Pentium P54C 75 - 200 (B1)"); FMS ( 0, 5, 0, 2, 2, "Intel Pentium P54C 75 - 200 (B3)"); FMS ( 0, 5, 0, 2, 4, "Intel Pentium P54C 75 - 200 (B5)"); FMS ( 0, 5, 0, 2, 5, "Intel Pentium P54C 75 - 200 (C2/mA1)"); FMS ( 0, 5, 0, 2, 6, "Intel Pentium P54C 75 - 200 (E0)"); FMS ( 0, 5, 0, 2, 11, "Intel Pentium P54C 75 - 200 (cB1)"); FMS ( 0, 5, 0, 2, 12, "Intel Pentium P54C 75 - 200 (cC0)"); FM ( 0, 5, 0, 2, "Intel Pentium P54C 75 - 200"); // An instlatx64 sample claims stepping 2 is C0. TFMS(1, 0, 5, 0, 3, 2, "Intel Pentium OverDrive for i486 (P24T C0)"); // no docs TFM (1, 0, 5, 0, 3, "Intel Pentium OverDrive for i486 (P24T)"); // no docs // Intel docs (242480). TFM (1, 0, 5, 0, 4, "Intel Pentium OverDrive for P54C"); FMS ( 0, 5, 0, 4, 3, "Intel Pentium MMX P55C (B1)"); FMS ( 0, 5, 0, 4, 4, "Intel Pentium MMX P55C (A3)"); FM ( 0, 5, 0, 4, "Intel Pentium MMX P55C"); // Intel docs (242480). FMS ( 0, 5, 0, 7, 0, "Intel Pentium MMX P54C 75 - 200 (A4)"); FM ( 0, 5, 0, 7, "Intel Pentium MMX P54C 75 - 200"); // Intel docs (242480). FMS ( 0, 5, 0, 8, 1, "Intel Pentium MMX P55C (Tillamook A0)"); FMS ( 0, 5, 0, 8, 2, "Intel Pentium MMX P55C (Tillamook B2)"); FM ( 0, 5, 0, 8, "Intel Pentium MMX P55C (Tillamook)"); // Intel docs (329676) provides stepping names, but no numbers. // However, A0 is the only name. FM ( 0, 5, 0, 9, "Intel Quark X1000 / D1000 / D2000 / C1000 (Lakemont)"); F ( 0, 5, "Intel Pentium (unknown model)"); FM ( 0, 6, 0, 0, "Intel Pentium Pro A-step"); // Intel docs (242689). FMS ( 0, 6, 0, 1, 1, "Intel Pentium Pro (B0)"); FMS ( 0, 6, 0, 1, 2, "Intel Pentium Pro (C0)"); FMS ( 0, 6, 0, 1, 6, "Intel Pentium Pro (sA0)"); FMS ( 0, 6, 0, 1, 7, "Intel Pentium Pro (sA1), .35um"); FMS ( 0, 6, 0, 1, 9, "Intel Pentium Pro (sB1), .35um"); FM ( 0, 6, 0, 1, "Intel Pentium Pro"); // Intel docs (243337) TFM (1, 0, 6, 0, 3, "Intel Pentium II OverDrive"); FMS ( 0, 6, 0, 3, 3, "Intel Pentium II (Klamath C0)"); FMS ( 0, 6, 0, 3, 4, "Intel Pentium II (Klamath C1)"); FM ( 0, 6, 0, 3, "Intel Pentium II (Klamath)"); FM ( 0, 6, 0, 4, "Intel Pentium P55CT OverDrive (Deschutes)"); // Intel docs (243337, 243748, 243776, 243887). FMSQ( 0, 6, 0, 5, 0, xD, "Intel Pentium II Xeon (Deschutes A0)"); FMSQ( 0, 6, 0, 5, 0, mD, "Intel Mobile Pentium II (Deschutes A0)"); FMSQ( 0, 6, 0, 5, 0, cD, "Intel Celeron (Deschutes A0)"); FMS ( 0, 6, 0, 5, 0, "Intel Pentium II (unknown type) (Deschutes A0)"); FMSQ( 0, 6, 0, 5, 1, xD, "Intel Pentium II Xeon (Deschutes A1)"); FMSQ( 0, 6, 0, 5, 1, cD, "Intel Celeron (Deschutes A1)"); FMS ( 0, 6, 0, 5, 1, "Intel Pentium II (unknown type) (Deschutes A1)"); FMSQ( 0, 6, 0, 5, 2, xD, "Intel Pentium II Xeon (Deschutes B0)"); FMSQ( 0, 6, 0, 5, 2, mD, "Intel Mobile Pentium II (Deschutes B0)"); FMSQ( 0, 6, 0, 5, 2, cD, "Intel Celeron (Deschutes B0)"); FMS ( 0, 6, 0, 5, 2, "Intel Pentium II (unknown type) (Deschutes B0)"); FMSQ( 0, 6, 0, 5, 3, xD, "Intel Pentium II Xeon (Deschutes B1)"); FMSQ( 0, 6, 0, 5, 3, cD, "Intel Celeron (Deschutes B1)"); FMS ( 0, 6, 0, 5, 3, "Intel Pentium II (unknown type) (Deschutes B1)"); FMQ ( 0, 6, 0, 5, xD, "Intel Pentium II Xeon (Deschutes)"); FMQ ( 0, 6, 0, 5, mD, "Intel Mobile Pentium II (Deschutes)"); FMQ ( 0, 6, 0, 5, cD, "Intel Celeron (Deschutes)"); FM ( 0, 6, 0, 5, "Intel Pentium II (unknown type) (Deschutes)"); // Intel docs (243748, 243887, 244444). FMSQ( 0, 6, 0, 6, 0, dP, "Intel Pentium II (Mendocino A0)"); FMSQ( 0, 6, 0, 6, 0, dC, "Intel Celeron (Mendocino A0)"); FMS ( 0, 6, 0, 6, 0, "Intel Pentium II (unknown type) (Mendocino A0)"); FMSQ( 0, 6, 0, 6, 5, dC, "Intel Celeron (Mendocino B0)"); FMSQ( 0, 6, 0, 6, 5, dP, "Intel Pentium II (Mendocino B0)"); FMS ( 0, 6, 0, 6, 5, "Intel Pentium II (unknown type) (Mendocino B0)"); FMS ( 0, 6, 0, 6, 10, "Intel Mobile Pentium II (Mendocino A0)"); FM ( 0, 6, 0, 6, "Intel Pentium II (Mendocino)"); // Intel docs (244453, 244460). FMSQ( 0, 6, 0, 7, 2, pK, "Intel Pentium III (Katmai B0)"); FMSQ( 0, 6, 0, 7, 2, xK, "Intel Pentium III Xeon (Katmai B0)"); FMS ( 0, 6, 0, 7, 2, "Intel Pentium III (unknown type) (Katmai B0)"); FMSQ( 0, 6, 0, 7, 3, pK, "Intel Pentium III (Katmai C0)"); FMSQ( 0, 6, 0, 7, 3, xK, "Intel Pentium III Xeon (Katmai C0)"); FMS ( 0, 6, 0, 7, 3, "Intel Pentium III (unknown type) (Katmai C0)"); FMQ ( 0, 6, 0, 7, pK, "Intel Pentium III (Katmai)"); FMQ ( 0, 6, 0, 7, xK, "Intel Pentium III Xeon (Katmai)"); FM ( 0, 6, 0, 7, "Intel Pentium III (unknown type) (Katmai)"); // Intel docs (243748, 244453, 244460, 245306, 245421). FMSQ( 0, 6, 0, 8, 1, sX, "Intel Pentium III Xeon (Coppermine A2)"); FMSQ( 0, 6, 0, 8, 1, MC, "Intel Mobile Celeron (Coppermine A2)"); FMSQ( 0, 6, 0, 8, 1, dC, "Intel Celeron (Coppermine A2)"); FMSQ( 0, 6, 0, 8, 1, MP, "Intel Mobile Pentium III (Coppermine A2)"); FMSQ( 0, 6, 0, 8, 1, dP, "Intel Pentium III (Coppermine A2)"); FMS ( 0, 6, 0, 8, 1, "Intel Pentium III (unknown type) (Coppermine A2)"); FMSQ( 0, 6, 0, 8, 3, sX, "Intel Pentium III Xeon (Coppermine B0)"); FMSQ( 0, 6, 0, 8, 3, MC, "Intel Mobile Celeron (Coppermine B0)"); FMSQ( 0, 6, 0, 8, 3, dC, "Intel Celeron (Coppermine B0)"); FMSQ( 0, 6, 0, 8, 3, MP, "Intel Mobile Pentium III (Coppermine B0)"); FMSQ( 0, 6, 0, 8, 3, dP, "Intel Pentium III (Coppermine B0)"); FMS ( 0, 6, 0, 8, 3, "Intel Pentium III (unknown type) (Coppermine B0)"); FMSQ( 0, 6, 0, 8, 6, sX, "Intel Pentium III Xeon (Coppermine C0)"); FMSQ( 0, 6, 0, 8, 6, MC, "Intel Mobile Celeron (Coppermine C0)"); FMSQ( 0, 6, 0, 8, 6, dC, "Intel Celeron (Coppermine C0)"); FMSQ( 0, 6, 0, 8, 6, MP, "Intel Mobile Pentium III (Coppermine C0)"); FMSQ( 0, 6, 0, 8, 6, dP, "Intel Pentium III (Coppermine C0)"); FMS ( 0, 6, 0, 8, 6, "Intel Pentium III (unknown type) (Coppermine C0)"); FMSQ( 0, 6, 0, 8, 10, sX, "Intel Pentium III Xeon (Coppermine D0)"); FMSQ( 0, 6, 0, 8, 10, MC, "Intel Mobile Celeron (Coppermine D0)"); FMSQ( 0, 6, 0, 8, 10, dC, "Intel Celeron (Coppermine D0)"); FMSQ( 0, 6, 0, 8, 10, MP, "Intel Mobile Pentium III (Coppermine D0)"); FMSQ( 0, 6, 0, 8, 10, dP, "Intel Pentium III (Coppermine D0)"); FMS ( 0, 6, 0, 8, 10, "Intel Pentium III (unknown type) (Coppermine D0)"); FMQ ( 0, 6, 0, 8, sX, "Intel Pentium III Xeon (Coppermine)"); FMQ ( 0, 6, 0, 8, MC, "Intel Mobile Celeron (Coppermine)"); FMQ ( 0, 6, 0, 8, dC, "Intel Celeron (Coppermine)"); FMQ ( 0, 6, 0, 8, MP, "Intel Mobile Pentium III (Coppermine)"); FMQ ( 0, 6, 0, 8, dP, "Intel Pentium III (Coppermine)"); FM ( 0, 6, 0, 8, "Intel Pentium III (unknown type) (Coppermine)"); // Intel docs (252665, 300303). FMSQ( 0, 6, 0, 9, 2, dC, "Intel Celeron (Timna)"); FMSQ( 0, 6, 0, 9, 2, dP, "Intel Pentium (Timna)"); FMS ( 0, 6, 0, 9, 2, "Intel Pentium (unknown type) (Timna)"); FMSQ( 0, 6, 0, 9, 5, dC, "Intel Celeron M (Banias B1)"); FMSQ( 0, 6, 0, 9, 5, dP, "Intel Pentium M (Banias B1)"); FMS ( 0, 6, 0, 9, 5, "Intel Pentium M (unknown type) (Banias B1)"); FMQ ( 0, 6, 0, 9, dC, "Intel Celeron M (Banias)"); FMQ ( 0, 6, 0, 9, dP, "Intel Pentium M (Banias)"); FM ( 0, 6, 0, 9, "Intel Pentium M (unknown type) (Banias)"); // Intel docs (244460). FMS ( 0, 6, 0,10, 0, "Intel Pentium III Xeon (Cascades A0)"); FMS ( 0, 6, 0,10, 1, "Intel Pentium III Xeon (Cascades A1)"); FMS ( 0, 6, 0,10, 4, "Intel Pentium III Xeon (Cascades B0)"); FM ( 0, 6, 0,10, "Intel Pentium III Xeon (Cascades)"); // Intel docs (243748, 244453, 245306, 245421). FMSQ( 0, 6, 0,11, 1, dC, "Intel Celeron (Tualatin A1)"); FMSQ( 0, 6, 0,11, 1, MC, "Intel Mobile Celeron (Tualatin A1)"); FMSQ( 0, 6, 0,11, 1, dP, "Intel Pentium III (Tualatin A1)"); FMS ( 0, 6, 0,11, 1, "Intel Pentium III (unknown type) (Tualatin A1)"); FMSQ( 0, 6, 0,11, 4, dC, "Intel Celeron (Tualatin B1)"); FMSQ( 0, 6, 0,11, 4, MC, "Intel Mobile Celeron (Tualatin B1)"); FMSQ( 0, 6, 0,11, 4, dP, "Intel Pentium III (Tualatin B1)"); FMS ( 0, 6, 0,11, 4, "Intel Pentium III (unknown type) (Tualatin B1)"); FMQ ( 0, 6, 0,11, dC, "Intel Celeron (Tualatin)"); FMQ ( 0, 6, 0,11, MC, "Intel Mobile Celeron (Tualatin)"); FMQ ( 0, 6, 0,11, dP, "Intel Pentium III (Tualatin)"); FM ( 0, 6, 0,11, "Intel Pentium III (unknown type) (Tualatin)"); // Intel docs (300303, 302209). FMSQ( 0, 6, 0,13, 6, dC, "Intel Celeron M (Dothan B1), 90nm"); FMSQ( 0, 6, 0,13, 6, dP, "Intel Pentium M (Dothan B1), 90nm"); FMS ( 0, 6, 0,13, 6, "Intel Pentium M (unknown type) (Dothan B1), 90nm"); FMSQ( 0, 6, 0,13, 8, dC, "Intel Celeron M (Dothan C0), 90nm/65nm"); FMSQ( 0, 6, 0,13, 8, MP, "Intel Processor A100/A110 (Stealey C0) / Pentium M (Crofton C0), 90nm"); FMSQ( 0, 6, 0,13, 8, dP, "Intel Pentium M (Dothan C0), 90nm"); FMS ( 0, 6, 0,13, 8, "Intel Pentium M (unknown type) (Dothan/Stealey/Crofton C0), 90nm/65nm"); FMQ ( 0, 6, 0,13, dC, "Intel Celeron M (Dothan)"); FMQ ( 0, 6, 0,13, MP, "Intel Processor A100/A110 (Stealey)"); FMQ ( 0, 6, 0,13, dP, "Intel Pentium M (Dothan)"); FM ( 0, 6, 0,13, "Intel Pentium M (unknown type) (Dothan/Crofton)"); // Intel docs (300303, 309222, 311392, 316515). FMSQ( 0, 6, 0,14, 8, sX, "Intel Xeon Processor LV (Sossaman C0)"); FMSQ( 0, 6, 0,14, 8, dC, "Intel Celeron (Yonah C0)"); FMSQ( 0, 6, 0,14, 8, DG, "Intel Core Duo (Yonah C0)"); FMSQ( 0, 6, 0,14, 8, dG, "Intel Core Solo (Yonah C0)"); FMS ( 0, 6, 0,14, 8, "Intel Core (unknown type) (Yonah/Sossaman C0)"); FMSQ( 0, 6, 0,14, 12, sX, "Intel Xeon Processor LV (Sossaman D0)"); FMSQ( 0, 6, 0,14, 12, dC, "Intel Celeron M (Yonah D0)"); FMSQ( 0, 6, 0,14, 12, MP, "Intel Pentium Dual-Core Mobile T2000 (Yonah D0)"); FMSQ( 0, 6, 0,14, 12, DG, "Intel Core Duo (Yonah D0)"); FMSQ( 0, 6, 0,14, 12, dG, "Intel Core Solo (Yonah D0)"); FMS ( 0, 6, 0,14, 12, "Intel Core (unknown type) (Yonah/Sossaman D0)"); FMS ( 0, 6, 0,14, 13, "Intel Pentium Dual-Core Mobile T2000 (Yonah M0)"); FMQ ( 0, 6, 0,14, sX, "Intel Xeon Processor LV (Sossaman)"); FMQ ( 0, 6, 0,14, dC, "Intel Celeron (Yonah)"); FMQ ( 0, 6, 0,14, MP, "Intel Pentium Dual-Core Mobile (Yonah)"); FMQ ( 0, 6, 0,14, DG, "Intel Core Duo (Yonah)"); FMQ ( 0, 6, 0,14, dG, "Intel Core Solo (Yonah)"); FM ( 0, 6, 0,14, "Intel Core (unknown type) (Yonah/Sossaman)"); // Intel docs (313279, 313356, 314079, 314916, 315338, 315593, 316134, // 316515, 316982, 317667, 318081, 318925, 319735). FMSQ( 0, 6, 0,15, 2, sX, "Intel Dual-Core Xeon Processor 3000 (Conroe L2)"); FMSQ( 0, 6, 0,15, 2, Mc, "Intel Core Duo Mobile (Merom L2)"); FMSQ( 0, 6, 0,15, 2, dc, "Intel Core Duo (Conroe L2)"); FMSQ( 0, 6, 0,15, 2, dP, "Intel Pentium Dual-Core Desktop Processor E2000 (Allendale L2)"); FMS ( 0, 6, 0,15, 2, "Intel Core (unknown type) (Conroe/Merom/Allendale L2)"); FMS ( 0, 6, 0,15, 4, "Intel Core 2 Duo (Conroe B0) / Xeon Processor 5100 (Woodcrest B0) (pre-production)"); FMSQ( 0, 6, 0,15, 5, QW, "Intel Dual-Core Xeon Processor 5100 (Woodcrest B1) (pre-production)"); FMSQ( 0, 6, 0,15, 5, XE, "Intel Core 2 Extreme Processor (Conroe B1)"); FMSQ( 0, 6, 0,15, 5, dL, "Intel Core 2 Duo (Allendale B1)"); FMSQ( 0, 6, 0,15, 5, dc, "Intel Core 2 Duo (Conroe B1)"); FMS ( 0, 6, 0,15, 5, "Intel Core 2 (unknown type) (Conroe/Allendale B1)"); FMSQ( 0, 6, 0,15, 6, Xc, "Intel Core 2 Extreme Processor (Conroe B2)"); FMSQ( 0, 6, 0,15, 6, Mc, "Intel Core 2 Duo Mobile (Merom B2)"); FMSQ( 0, 6, 0,15, 6, dL, "Intel Core 2 Duo (Allendale B2)"); FMSQ( 0, 6, 0,15, 6, dc, "Intel Core 2 Duo (Conroe B2)"); FMSQ( 0, 6, 0,15, 6, dC, "Intel Celeron M (Conroe B2)"); FMSQ( 0, 6, 0,15, 6, sX, "Intel Dual-Core Xeon Processor 3000 (Conroe B2) / Dual-Core Xeon Processor 5100 (Woodcrest B2)"); FMS ( 0, 6, 0,15, 6, "Intel Core 2 (unknown type) (Conroe/Allendale/Woodcrest B2)"); FMSQ( 0, 6, 0,15, 7, sX, "Intel Quad-Core Xeon Processor 3200 (Kentsfield B3) / Quad-Core Xeon Processor 5300 (Clovertown B3)"); FMSQ( 0, 6, 0,15, 7, Xc, "Intel Core 2 Extreme Quad-Core Processor QX6xx0 (Kentsfield B3)"); FMS ( 0, 6, 0,15, 7, "Intel Core 2 (unknown type) (Kentsfield/Clovertown B3)"); FMSQ( 0, 6, 0,15, 10, Mc, "Intel Core 2 Duo Mobile (Merom E1)"); FMSQ( 0, 6, 0,15, 10, dC, "Intel Celeron Processor 500 (Merom E1)"); FMS ( 0, 6, 0,15, 10, "Intel Core 2 (unknown type) (Merom E1)"); FMSQ( 0, 6, 0,15, 11, sQ, "Intel Quad-Core Xeon Processor 5300 (Clovertown G0)"); FMSQ( 0, 6, 0,15, 11, sX, "Intel Xeon Processor 3000 (Conroe G0) / Xeon Processor 3200 (Kentsfield G0) / Xeon Processor 7200/7300 (Tigerton G0)"); FMSQ( 0, 6, 0,15, 11, Xc, "Intel Core 2 Extreme Quad-Core Processor QX6xx0 (Kentsfield G0)"); FMSQ( 0, 6, 0,15, 11, Mc, "Intel Core 2 Duo Mobile (Merom G2)"); FMSQ( 0, 6, 0,15, 11, Qc, "Intel Core 2 Quad (Conroe G0)"); FMSQ( 0, 6, 0,15, 11, dc, "Intel Core 2 Duo (Conroe G0)"); FMS ( 0, 6, 0,15, 11, "Intel Core 2 (unknown type) (Merom/Conroe/Kentsfield/Clovertown/Tigerton G0)"); FMSQ( 0, 6, 0,15, 13, Mc, "Intel Core 2 Duo Mobile (Merom M1) / Celeron Processor 500 (Merom E1)"); FMSQ( 0, 6, 0,15, 13, Qc, "Intel Core 2 Quad (Conroe M0)"); FMSQ( 0, 6, 0,15, 13, dc, "Intel Core 2 Duo (Conroe M0)"); FMSQ( 0, 6, 0,15, 13, dP, "Intel Pentium Dual-Core Desktop Processor E2000 (Allendale M0)"); FMSQ( 0, 6, 0,15, 13, dC, "Intel Celeron Dual-Core E1000 (Allendale M0) / Celeron Dual-Core T1000 (Merom M0)"); FMS ( 0, 6, 0,15, 13, "Intel Core 2 (unknown type) (Merom/Conroe/Allendale M0 / Merom E1)"); FMQ ( 0, 6, 0,15, sQ, "Intel Quad-Core Xeon (Woodcrest)"); FMQ ( 0, 6, 0,15, sX, "Intel Dual-Core Xeon (Conroe / Woodcrest) / Quad-Core Xeon (Kentsfield / Clovertown) / Xeon (Tigerton G0)"); FMQ ( 0, 6, 0,15, Xc, "Intel Core 2 Extreme Processor (Conroe) / Core 2 Extreme Quad-Core (Kentsfield)"); FMQ ( 0, 6, 0,15, Mc, "Intel Core Duo Mobile / Core 2 Duo Mobile (Merom) / Celeron (Merom)"); FMQ ( 0, 6, 0,15, Qc, "Intel Core 2 Quad (Conroe)"); FMQ ( 0, 6, 0,15, dc, "Intel Core Duo / Core 2 Duo (Conroe)"); FMQ ( 0, 6, 0,15, dP, "Intel Pentium Dual-Core (Allendale)"); FMQ ( 0, 6, 0,15, dC, "Intel Celeron M (Conroe) / Celeron (Merom) / Celeron Dual-Core (Allendale)"); FM ( 0, 6, 0,15, "Intel Core 2 (unknown type) (Merom/Conroe/Allendale/Kentsfield/Allendale/Clovertown/Woodcrest/Tigerton)"); // Intel docs (320257). FMS ( 0, 6, 1, 5, 0, "Intel EP80579 (Tolapai B0)"); // Intel docs (314079, 316964, 317667, 318547). FMSQ( 0, 6, 1, 6, 1, MC, "Intel Celeron Processor 200/400/500 (Conroe-L/Merom-L A1)"); FMSQ( 0, 6, 1, 6, 1, dC, "Intel Celeron M (Merom-L A1)"); FMSQ( 0, 6, 1, 6, 1, Mc, "Intel Core 2 Duo Mobile (Merom A1)"); FMS ( 0, 6, 1, 6, 1, "Intel Core 2 (unknown type) (Merom/Conroe A1)"); FMQ ( 0, 6, 1, 6, MC, "Intel Celeron Processor 200/400/500 (Conroe-L/Merom-L)"); FMQ ( 0, 6, 1, 6, dC, "Intel Celeron M (Merom-L)"); FMQ ( 0, 6, 1, 6, Mc, "Intel Core 2 Duo Mobile (Merom)"); FM ( 0, 6, 1, 6, "Intel Core 2 (unknown type) (Merom/Conroe)"); // Intel docs (318585, 318586, 318727, 318733, 318915, 319006, 319007, // 319129, 320121, 320468, 320469, 322568). FMSQ( 0, 6, 1, 7, 6, sQ, "Intel Xeon Processor 3300 (Yorkfield C0) / Xeon Processor 5200 (Wolfdale C0) / Xeon Processor 5400 (Harpertown C0)"); FMSQ( 0, 6, 1, 7, 6, sX, "Intel Xeon Processor 3100 (Wolfdale C0) / Xeon Processor 5200 (Wolfdale C0) / Xeon Processor 5400 (Harpertown C0)"); FMSQ( 0, 6, 1, 7, 6, Xc, "Intel Core 2 Extreme QX9000 (Yorkfield C0)"); FMSQ( 0, 6, 1, 7, 6, Me, "Intel Mobile Core 2 Duo (Penryn C0)"); FMSQ( 0, 6, 1, 7, 6, Mc, "Intel Mobile Core 2 Duo (Penryn M0)"); FMSQ( 0, 6, 1, 7, 6, de, "Intel Core 2 Duo (Wolfdale C0)"); FMSQ( 0, 6, 1, 7, 6, dc, "Intel Core 2 Duo (Wolfdale M0)"); FMSQ( 0, 6, 1, 7, 6, dP, "Intel Pentium Dual-Core Processor E5000 (Wolfdale M0)"); FMS ( 0, 6, 1, 7, 6, "Intel Core 2 (unknown type) (Penryn/Wolfdale/Yorkfield/Harpertown C0/M0)"); FMSQ( 0, 6, 1, 7, 7, sQ, "Intel Xeon Processor 3300 (Yorkfield C1)"); FMSQ( 0, 6, 1, 7, 7, Xc, "Intel Core 2 Extreme QX9000 (Yorkfield C1)"); FMSQ( 0, 6, 1, 7, 7, Qe, "Intel Core 2 Quad-Core Q9000 (Yorkfield C1)"); FMSQ( 0, 6, 1, 7, 7, Qc, "Intel Core 2 Quad-Core Q9000 (Yorkfield M1)"); FMS ( 0, 6, 1, 7, 7, "Intel Core 2 (unknown type) (Penryn/Wolfdale/Yorkfield/Harpertown C1/M1)"); FMSQ( 0, 6, 1, 7, 10, Me, "Intel Mobile Core 2 (Penryn E0)"); FMSQ( 0, 6, 1, 7, 10, Mc, "Intel Mobile Core 2 (Penryn R0)"); FMSQ( 0, 6, 1, 7, 10, Qe, "Intel Core 2 Quad-Core Q9000 (Yorkfield E0)"); FMSQ( 0, 6, 1, 7, 10, Qc, "Intel Core 2 Quad-Core Q9000 (Yorkfield R0)"); FMSQ( 0, 6, 1, 7, 10, de, "Intel Core 2 Duo (Wolfdale E0)"); FMSQ( 0, 6, 1, 7, 10, dc, "Intel Core 2 Duo (Wolfdale R0)"); FMSQ( 0, 6, 1, 7, 10, dP, "Intel Pentium Dual-Core Processor E5000/E6000 / Pentium T4000 (Wolfdale R0)"); FMSQ( 0, 6, 1, 7, 10, dC, "Intel Celeron E3000 / T3000 / 900 / SU2300 (Wolfdale R0)"); // T3000 & 900 names from MRG* 2018-03-06 FMSQ( 0, 6, 1, 7, 10, MC, "Intel Celeron M ULV 700 (Penryn R0)"); FMSQ( 0, 6, 1, 7, 10, se, "Intel Xeon Processor 3300 (Yorkfield E0)"); FMSQ( 0, 6, 1, 7, 10, sQ, "Intel Xeon Processor 3300 (Yorkfield R0)"); FMSQ( 0, 6, 1, 7, 10, sX, "Intel Xeon Processor 3100 (Wolfdale E0) / Xeon Processor 3300 (Yorkfield R0) / Xeon Processor 5200 (Wolfdale E0) / Xeon Processor 5400 (Harpertown E0)"); FMS ( 0, 6, 1, 7, 10, "Intel Core 2 (unknown type) (Penryn/Wolfdale/Yorkfield/Harpertown E0/R0)"); FMQ ( 0, 6, 1, 7, se, "Intel Xeon (Wolfdale / Yorkfield / Harpertown)"); FMQ ( 0, 6, 1, 7, sQ, "Intel Xeon (Wolfdale / Yorkfield / Harpertown)"); FMQ ( 0, 6, 1, 7, sX, "Intel Xeon (Wolfdale / Yorkfield / Harpertown)"); FMQ ( 0, 6, 1, 7, Mc, "Intel Mobile Core 2 (Penryn)"); FMQ ( 0, 6, 1, 7, Xc, "Intel Core 2 Extreme (Yorkfield)"); FMQ ( 0, 6, 1, 7, Qc, "Intel Core 2 Quad-Core (Yorkfield)"); FMQ ( 0, 6, 1, 7, dc, "Intel Core 2 Duo (Wolfdale)"); FMQ ( 0, 6, 1, 7, dC, "Intel Celeron (Wolfdale)"); FMQ ( 0, 6, 1, 7, MC, "Intel Celeron M ULV (Penryn)"); FMQ ( 0, 6, 1, 7, dP, "Intel Pentium (Wolfdale)"); FM ( 0, 6, 1, 7, "Intel Core 2 (unknown type) (Penryn/Wolfdale/Yorkfield/Harpertown)"); // Intel docs (320836, 321324, 321333). FMS ( 0, 6, 1,10, 4, "Intel Core i7-900 (Bloomfield C0)"); FMSQ( 0, 6, 1,10, 5, dc, "Intel Core i7-900 (Bloomfield D0)"); FMSQ( 0, 6, 1,10, 5, sX, "Intel Xeon Processor 3500 (Bloomfield D0) / Xeon Processor 5500 (Gainestown D0)"); FMS ( 0, 6, 1,10, 5, "Intel Core (unknown type) (Bloomfield/Gainestown D0)"); FMQ ( 0, 6, 1,10, dc, "Intel Core (Bloomfield)"); FMQ ( 0, 6, 1,10, sX, "Intel Xeon (Bloomfield / Gainestown)"); FM ( 0, 6, 1,10, "Intel Core (unknown type) (Bloomfield / Gainestown)"); // Intel docs (319536, 319974, 320047, 320529, 322861, 322862, 322849, // 324341). FMS ( 0, 6, 1,12, 1, "Intel Atom N270 (Diamondville B0)"); FMS ( 0, 6, 1,12, 2, "Intel Atom 200/N200/300 (Diamondville C0) / Atom Z500 (Silverthorne C0)"); FMS ( 0, 6, 1,12, 10, "Intel Atom D400/N400 (Pineview A0) / Atom D500/N500 (Pineview B0)"); FM ( 0, 6, 1,12, "Intel Atom (Diamondville / Silverthorne / Pineview)"); // Intel docs (320336). FMS ( 0, 6, 1,13, 1, "Intel Xeon Processor 7400 (Dunnington A1)"); FM ( 0, 6, 1,13, "Intel Xeon (unknown type) (Dunnington)"); // Intel docs (320767, 322166, 322373, 323105). FMSQ( 0, 6, 1,14, 4, sX, "Intel Xeon Processor EC3500/EC5500 (Jasper Forest B0)"); // EC names from MRG* 2018-03-06 FMSQ( 0, 6, 1,14, 4, dC, "Intel Celeron P1053 (Jasper Forest B0)"); FMS ( 0, 6, 1,14, 4, "Intel Xeon (unknown type) (Jasper Forest B0)"); FMSQ( 0, 6, 1,14, 5, sX, "Intel Xeon Processor 3400 (Lynnfield B1)"); FMSQ( 0, 6, 1,14, 5, Mc, "Intel Core i7-700/800/900 Mobile (Clarksfield B1)"); FMSQ( 0, 6, 1,14, 5, dc, "Intel Core i*-700/800/900 (Lynnfield B1)"); // 900 from MRG* 2018-03-06 FMS ( 0, 6, 1,14, 5, "Intel Core (unknown type) (Lynnfield/Clarksfield B1)"); FMQ ( 0, 6, 1,14, sX, "Intel Xeon (Lynnfield) / Xeon (Jasper Forest)"); FMQ ( 0, 6, 1,14, dC, "Intel Celeron (Jasper Forest)"); FMQ ( 0, 6, 1,14, Mc, "Intel Core Mobile (Clarksfield)"); FMQ ( 0, 6, 1,14, dc, "Intel Core (Lynnfield)"); FM ( 0, 6, 1,14, "Intel Core (unknown type) (Lynnfield/Clarksfield)"); FM ( 0, 6, 1,15, "Intel (unknown model) (Havendale/Auburndale)"); // Intel docs (322814, 322911, 323179, 323847, 323056, 324456). FMSQ( 0, 6, 2, 5, 2, sX, "Intel Xeon Processor L3406 (Clarkdale C2)"); FMSQ( 0, 6, 2, 5, 2, MC, "Intel Celeron Mobile P4500 (Arrandale C2)"); FMSQ( 0, 6, 2, 5, 2, MP, "Intel Pentium P6000 Mobile (Arrandale C2)"); FMSQ( 0, 6, 2, 5, 2, dP, "Intel Pentium G6900 / P4500 (Clarkdale C2)"); FMSQ( 0, 6, 2, 5, 2, Mc, "Intel Core i*-300/400/500/600 Mobile (Arrandale C2)"); FMSQ( 0, 6, 2, 5, 2, dc, "Intel Core i*-300/500/600 (Clarkdale C2)"); FMS ( 0, 6, 2, 5, 2, "Intel Core (unknown type) (Clarkdale/Arrandale C2)"); FMSQ( 0, 6, 2, 5, 5, MC, "Intel Celeron Mobile U3400 (Arrandale K0) / Celeron Mobile P4600 (Arrandale K0)"); FMSQ( 0, 6, 2, 5, 5, MP, "Intel Pentium U5000 Mobile (Arrandale K0)"); FMSQ( 0, 6, 2, 5, 5, dP, "Intel Pentium P4500 / U3400 / G6900 (Clarkdale K0)"); // G6900 only from MRG* 2018-03-06 FMSQ( 0, 6, 2, 5, 5, dc, "Intel Core i*-300/400/500/600 (Clarkdale K0)"); FMS ( 0, 6, 2, 5, 5, "Intel Core (unknown type) (Clarkdale/Arrandale K0)"); FMQ ( 0, 6, 2, 5, sX, "Intel Xeon Processor L3406 (Clarkdale)"); FMQ ( 0, 6, 2, 5, MC, "Intel Celeron Mobile (Arrandale)"); FMQ ( 0, 6, 2, 5, MP, "Intel Pentium Mobile (Arrandale)"); FMQ ( 0, 6, 2, 5, dP, "Intel Pentium (Clarkdale)"); FMQ ( 0, 6, 2, 5, Mc, "Intel Core Mobile (Arrandale)"); FMQ ( 0, 6, 2, 5, dc, "Intel Core (Clarkdale)"); FM ( 0, 6, 2, 5, "Intel Core (unknown type) (Clarkdale/Arrandale)"); // Intel docs (324209, 325307, 325309, 325630). FMS ( 0, 6, 2, 6, 1, "Intel Atom Z600 (Lincroft C0) / Atom E600 (Tunnel Creek B0/B1)"); FM ( 0, 6, 2, 6, "Intel Atom Z600 (Lincroft) / Atom E600 (Tunnel Creek B0/B1)"); FM ( 0, 6, 2, 7, "Intel Atom Z2000 (Medfield)"); // no spec update, only instlatx64 example (stepping 1) // Intel docs (327335) omit stepping numbers, but (324643, 324827, 324972) // provide some. An instlatx64 stepping 6 example has been spoted, but it // isn't known which stepping name that is. FMSQ( 0, 6, 2,10, 7, Xc, "Intel Mobile Core i7 Extreme (Sandy Bridge D2/J1/Q0)"); FMSQ( 0, 6, 2,10, 7, Mc, "Intel Mobile Core i*-2000 (Sandy Bridge D2/J1/Q0)"); FMSQ( 0, 6, 2,10, 7, dc, "Intel Core i*-2000 (Sandy Bridge D2/J1/Q0)"); FMSQ( 0, 6, 2,10, 7, MC, "Intel Celeron G400/G500/700/800/B800 (Sandy Bridge J1/Q0)"); FMSQ( 0, 6, 2,10, 7, sX, "Intel Xeon E3-1100 / E3-1200 v1 (Sandy Bridge D2/J1/Q0)"); FMSQ( 0, 6, 2,10, 7, dP, "Intel Pentium G500/G600/G800 / Pentium 900 (Sandy Bridge Q0)"); FMS ( 0, 6, 2,10, 7, "Intel Core (unknown type) (Sandy Bridge D2/J1/Q0)"); FMQ ( 0, 6, 2,10, Xc, "Intel Mobile Core i7 Extreme (Sandy Bridge)"); FMQ ( 0, 6, 2,10, Mc, "Intel Mobile Core i*-2000 (Sandy Bridge)"); FMQ ( 0, 6, 2,10, dc, "Intel Core i*-2000 (Sandy Bridge)"); FMQ ( 0, 6, 2,10, MC, "Intel Celeron G400/G500/700/800/B800 (Sandy Bridge)"); FMQ ( 0, 6, 2,10, sX, "Intel Xeon E3-1100 / E3-1200 v1 (Sandy Bridge)"); FMQ ( 0, 6, 2,10, dP, "Intel Pentium G500/G600/G800 / Pentium 900 (Sandy Bridge)"); FM ( 0, 6, 2,10, "Intel Core (unknown type) (Sandy Bridge)"); // Intel docs (323254: i7-900, 323338: Xeon 3600, 323372: Xeon 5600). // https://en.wikipedia.org/wiki/Westmere_(microarchitecture) provided // A0 & B0 stepping values. FMSQ( 0, 6, 2,12, 0, dc, "Intel Core i7-900 / Core i7-980X (Gulftown A0)"); FMSQ( 0, 6, 2,12, 0, sX, "Intel Xeon Processor 3600 / 5600 (Westmere-EP A0)"); FMS ( 0, 6, 2,12, 0, "Intel Core (unknown type) (Gulftown/Westmere-EP A0)"); FMSQ( 0, 6, 2,12, 1, dc, "Intel Core i7-900 / Core i7-980X (Gulftown B0)"); FMSQ( 0, 6, 2,12, 1, sX, "Intel Xeon Processor 3600 / 5600 (Westmere-EP B0)"); FMS ( 0, 6, 2,12, 1, "Intel Core (unknown type) (Gulftown/Westmere-EP B0)"); FMSQ( 0, 6, 2,12, 2, dc, "Intel Core i7-900 / Core i7-980X (Gulftown B1)"); FMSQ( 0, 6, 2,12, 2, sX, "Intel Xeon Processor 3600 / 5600 (Westmere-EP B1)"); FMS ( 0, 6, 2,12, 2, "Intel Core (unknown type) (Gulftown/Westmere-EP B1)"); FMQ ( 0, 6, 2,12, dc, "Intel Core (unknown type) (Gulftown)"); FMQ ( 0, 6, 2,12, sX, "Intel Xeon (unknown type) (Westmere-EP)"); FM ( 0, 6, 2,12, "Intel (unknown type) (Gulftown/Westmere-EP)"); // Intel docs (326198, 326510). FMSQ( 0, 6, 2,13, 6, sX, "Intel Xeon E5-1600/2600 (Sandy Bridge-E C1/M0)"); FMSQ( 0, 6, 2,13, 6, dc, "Intel Core i7-3800/3900 (Sandy Bridge-E C1)"); FMS ( 0, 6, 2,13, 6, "Intel Core (unknown type) (Sandy Bridge-E C1)"); FMSQ( 0, 6, 2,13, 7, sX, "Intel Xeon E5-1600/2600/4600 (Sandy Bridge-E C2/M1)"); FMSQ( 0, 6, 2,13, 7, dc, "Intel Core i7-3800/3900 (Sandy Bridge-E C2)"); FMSQ( 0, 6, 2,13, 7, dP, "Intel Pentium 1405 (Sandy Bridge-E C1)"); // MRG* 2018-03-06 FMS ( 0, 6, 2,13, 7, "Intel Core (unknown type) (Sandy Bridge-E C2/M1)"); FMQ ( 0, 6, 2,13, sX, "Intel Xeon E5-1600/2600 (Sandy Bridge-E)"); FMQ ( 0, 6, 2,13, dc, "Intel Core i7-3800/3900 (Sandy Bridge-E)"); FMQ ( 0, 6, 2,13, dP, "Intel Pentium 1405 (Sandy Bridge-E)"); // MRG* 2018-03-06 FM ( 0, 6, 2,13, "Intel Core (unknown type) (Sandy Bridge-E)"); // Intel docs (323344) are inconsistent. Using Table 2 information. // instlatx64 samples have steppings 4 & 5, but no idea which stepping names // those are. FMS ( 0, 6, 2,14, 6, "Intel Xeon Processor 6500 / 7500 (Beckton D0)"); FM ( 0, 6, 2,14, "Intel Xeon Processor 6500 / 7500 (Beckton)"); // Intel docs (325122). FMS ( 0, 6, 2,15, 2, "Intel Xeon E7-8800 / Xeon E7-4800 / Xeon E7-2800 (Westmere-EX A2)"); FM ( 0, 6, 2,15, "Intel Xeon (unknown type) (Westmere-EX)"); // Intel docs (332067) omit stepping numbers for D1, but (328105) provide // some. FMS ( 0, 6, 3, 5, 1, "Intel Atom Z2760 (Clover Trail C0) / Z8000 (Cherry Trail C0)"); FM ( 0, 6, 3, 5, "Intel Atom Z2760 (Clover Trail) / Z8000 (Cherry Trail)"); // Intel docs (326140) for Cedarview // Intel docs (328198) do not provide any FMS for Centerton, but an example // from jhladky@redhat.com does. // instlatx64 has example with stepping 9, but no idea what stepping name // that is. FMS ( 0, 6, 3, 6, 1, "Intel Atom D2000/N2000 (Cedarview B1/B2/B3) / S1200 (Centerton B1)"); FM ( 0, 6, 3, 6, "Intel Atom D2000/N2000 (Cedarview) / S1200 (Centerton)"); // Intel docs (329475, 329671, 329901, 600827). FMS ( 0, 6, 3, 7, 1, "Intel Atom Z3000 (Bay Trail-T A0)"); FMSQ( 0, 6, 3, 7, 2, dC, "Intel Celeron N2800 / N2900 (Bay Trail-M B0/B1)"); FMSQ( 0, 6, 3, 7, 2, dP, "Intel Pentium N3500 / J2800 / J2900 (Bay Trail-M B0/B1)"); FMS ( 0, 6, 3, 7, 2, "Intel Atom (unknown type) (Bay Trail-M B0/B1)"); FMSQ( 0, 6, 3, 7, 3, dC, "Intel Celeron N1700 / N1800 / N2800 / N2900 / J1700 / J1800 / J1900 (Bay Trail-M B2/B3)"); FMSQ( 0, 6, 3, 7, 3, dP, "Intel Pentium N3500 / J2800 / J2900 (Bay Trail-M B2/B3) / Atom E3800 (Bay Trail-I B3)"); FMSQ( 0, 6, 3, 7, 3, da, "Intel Atom E3800 / Z3700 (Bay Trail-I B3)"); // Z3700 only from MRG* 2019-08-31 FMS ( 0, 6, 3, 7, 3, "Intel Atom (unknown type) (Bay Trail B2/B3)"); FMSQ( 0, 6, 3, 7, 4, dC, "Intel Celeron N2800 / N2900 (Bay Trail-M C0)"); FMSQ( 0, 6, 3, 7, 4, dP, "Intel Pentium N3500 / J2800 / J2900 (Bay Trail-M C0)"); FMS ( 0, 6, 3, 7, 4, "Intel Atom (unknown type) (Bay Trail-M C0 / Bay Trail-T B2/B3)"); FMSQ( 0, 6, 3, 7, 8, da, "Intel Atom Z3700 (Bay Trail C0)"); // MRG* 2019-08-31, ILPMDF* 20190514 provides stepping. FMSQ( 0, 6, 3, 7, 8, dC, "Intel Celeron N2800 / N2900 (Bay Trail C0)"); // MRG* 2019-08-31, ILPMDF* 20190514 provides stepping. FMSQ( 0, 6, 3, 7, 8, dP, "Intel Pentium N3500 (Bay Trail C0)"); // MRG* 2019-08-31, ILPMDF* 20190514 provides stepping. FMS ( 0, 6, 3, 7, 8, "Intel Atom (unknown type) (Bay Trail C0)"); // MRG* 2019-08-31, ILPMDF* 20190514 provides stepping. FMSQ( 0, 6, 3, 7, 9, da, "Intel Atom E3800 (Bay Trail-I D0)"); FMSQ( 0, 6, 3, 7, 9, dC, "Intel Celeron N2800 / N2900 (Bay Trail-M/D D0/D1)"); // only MRG* 2018-03-06 FMSQ( 0, 6, 3, 7, 9, dP, "Intel Pentium J1800 / J1900 (Bay Trail-M/D D0/D1)"); // only MRG* 2018-03-06 FMS ( 0, 6, 3, 7, 9, "Intel Atom (unknown type) (Bay Trail D0)"); FM ( 0, 6, 3, 7, "Intel Atom (unknown type) (Bay Trail-M / Bay Trail-T / Bay Trail-I)"); // Intel docs (326766, 326770, 326774, 329376). // How to differentiate Gladden from Ivy Bridge here? FMSQ( 0, 6, 3,10, 9, Mc, "Intel Mobile Core i*-3000 (Ivy Bridge E1/L1) / Pentium 900/1000/2000/2100 (P0)"); FMSQ( 0, 6, 3,10, 9, dc, "Intel Core i*-3000 (Ivy Bridge E1/N0/L1)"); FMSQ( 0, 6, 3,10, 9, sX, "Intel Xeon E3-1100 v2 / E3-1200 v2 (Ivy Bridge E1/N0/L1)"); FMSQ( 0, 6, 3,10, 9, dC, "Intel Celeron 1000 / G1600 (Ivy Bridge P0)"); // only MRG 2019-08-31 FMSQ( 0, 6, 3,10, 9, dP, "Intel Pentium G1600/G2000/G2100 / Pentium B900C (Ivy Bridge P0)"); FMS ( 0, 6, 3,10, 9, "Intel Core (unknown type) (Ivy Bridge E1/N0/L1/P0)"); FMQ ( 0, 6, 3,10, Mc, "Intel Mobile Core i*-3000 (Ivy Bridge) / Pentium 900/1000/2000/2100"); FMQ ( 0, 6, 3,10, dc, "Intel Core i*-3000 (Ivy Bridge)"); FMQ ( 0, 6, 3,10, sX, "Intel Xeon E3-1100 v2 / E3-1200 v2 (Ivy Bridge)"); FMQ ( 0, 6, 3,10, dC, "Intel Celeron 1000 / G1600 (Ivy Bridge)"); // only MRG 2019-08-31 FMQ ( 0, 6, 3,10, dP, "Intel Pentium G1600/G2000/G2100 / Pentium B900C (Ivy Bridge)"); FM ( 0, 6, 3,10, "Intel Core (unknown type) (Ivy Bridge)"); // Intel docs (328899, 328903, 328908) omit the stepping numbers for (0,6),(3,12) C0 & D0. // MRG* 2018-03-06 mentions (0,6),(3,12),3, but doesn't specify which stepping name it is. // Coreboot* identifies the steppings. FMSQ( 0, 6, 3,12, 1, sX, "Intel Xeon E3-1200 v3 (Haswell A0)"); FMSQ( 0, 6, 3,12, 1, Mc, "Intel Mobile Core i*-4000U (Mobile M) (Haswell A0)"); FMSQ( 0, 6, 3,12, 1, dc, "Intel Core i*-4000 / Mobile Core i*-4000 (Haswell A0)"); FMSQ( 0, 6, 3,12, 1, MC, "Intel Mobile Celeron 2900U (Mobile M) (Haswell A0)"); FMSQ( 0, 6, 3,12, 1, dC, "Intel Celeron G1800 / G2000 (Haswell A0)"); // G2000 only from MRG* 2019-08-31 FMSQ( 0, 6, 3,12, 1, MP, "Intel Mobile Pentium 3500U / 3600U / 3500Y (Mobile M) (Haswell A0)"); FMSQ( 0, 6, 3,12, 1, dP, "Intel Pentium G3000 (Haswell A0)"); FMS ( 0, 6, 3,12, 1, "Intel Core (unknown type) (Haswell A0)"); FMSQ( 0, 6, 3,12, 2, sX, "Intel Xeon E3-1200 v3 (Haswell B0)"); FMSQ( 0, 6, 3,12, 2, Mc, "Intel Mobile Core i*-4000U (Mobile M) (Haswell B0)"); FMSQ( 0, 6, 3,12, 2, dc, "Intel Core i*-4000 / Mobile Core i*-4000 (Haswell B0)"); FMSQ( 0, 6, 3,12, 2, MC, "Intel Mobile Celeron 2900U (Mobile M) (Haswell B0)"); FMSQ( 0, 6, 3,12, 2, dC, "Intel Celeron G1800 / G2000 (Haswell B0)"); // G2000 only from MRG* 2019-08-31 FMSQ( 0, 6, 3,12, 2, MP, "Intel Mobile Pentium 3500U / 3600U / 3500Y (Mobile M) (Haswell B0)"); FMSQ( 0, 6, 3,12, 2, dP, "Intel Pentium G3000 (Haswell B0)"); FMS ( 0, 6, 3,12, 2, "Intel Core (unknown type) (Haswell B0)"); FMSQ( 0, 6, 3,12, 3, sX, "Intel Xeon E3-1200 v3 (Haswell C0)"); FMSQ( 0, 6, 3,12, 3, Mc, "Intel Mobile Core i*-4000U (Mobile M) (Haswell C0)"); FMSQ( 0, 6, 3,12, 3, dc, "Intel Core i*-4000 / Mobile Core i*-4000 (Haswell C0)"); FMSQ( 0, 6, 3,12, 3, MC, "Intel Mobile Celeron 2900U (Mobile M) (Haswell C0)"); FMSQ( 0, 6, 3,12, 3, dC, "Intel Celeron G1800 / G2000 (Haswell C0)"); // G2000 only from MRG* 2019-08-31 FMSQ( 0, 6, 3,12, 3, MP, "Intel Mobile Pentium 3500U / 3600U / 3500Y (Mobile M) (Haswell C0)"); FMSQ( 0, 6, 3,12, 3, dP, "Intel Pentium G3000 (Haswell C0)"); FMS ( 0, 6, 3,12, 3, "Intel Core (unknown type) (Haswell C0)"); FMQ ( 0, 6, 3,12, sX, "Intel Xeon E3-1200 v3 (Haswell)"); FMQ ( 0, 6, 3,12, Mc, "Intel Mobile Core i*-4000U (Mobile M) (Haswell)"); FMQ ( 0, 6, 3,12, dc, "Intel Core i*-4000 / Mobile Core i*-4000 (Haswell)"); FMQ ( 0, 6, 3,12, MC, "Intel Mobile Celeron 2900U (Mobile M) (Haswell)"); FMQ ( 0, 6, 3,12, dC, "Intel Celeron G1800 / G2000 (Haswell)"); // G2000 only from MRG* 2019-08-31 FMQ ( 0, 6, 3,12, MP, "Intel Mobile Pentium 3500U / 3600U / 3500Y (Mobile M) (Haswell)"); FMQ ( 0, 6, 3,12, dP, "Intel Pentium G3000 (Haswell)"); FM ( 0, 6, 3,12, "Intel Core (unknown type) (Haswell)"); // Intel docs (330836) omit the stepping numbers for (0,6),(3,13) E0 & F0. // MRG* 2019-08-31 mentions stepping 4, but doesn't specify which stepping name it is. // Coreboot* identifies the steppings. FMSQ( 0, 6, 3,13, 2, dc, "Intel Core i*-5000 (Broadwell-U C0) / Core M (Broadwell-Y C0)"); FMSQ( 0, 6, 3,13, 2, MC, "Intel Mobile Celeron 3000 (Broadwell-U C0)"); FMSQ( 0, 6, 3,13, 2, dC, "Intel Celeron 3000 (Broadwell-U C0)"); FMSQ( 0, 6, 3,13, 2, dP, "Intel Pentium 3700U / 3800U / 3200U (Broadwell-U C0)"); // only MRG* 2018-03-06, 2019-08-31 FMS ( 0, 6, 3,13, 2, "Intel Core (unknown type) (Broadwell-U/Y C0)"); FMSQ( 0, 6, 3,13, 3, dc, "Intel Core i*-5000 (Broadwell-U D0) / Core M (Broadwell-Y D0)"); FMSQ( 0, 6, 3,13, 3, MC, "Intel Mobile Celeron 3000 (Broadwell-U D0)"); FMSQ( 0, 6, 3,13, 3, dC, "Intel Celeron 3000 (Broadwell-U D0)"); FMSQ( 0, 6, 3,13, 3, dP, "Intel Pentium 3700U / 3800U / 3200U (Broadwell-U D0)"); // only MRG* 2018-03-06, 2019-08-31 FMS ( 0, 6, 3,13, 3, "Intel Core (unknown type) (Broadwell-U/Y D0)"); FMSQ( 0, 6, 3,13, 4, dc, "Intel Core i*-5000 (Broadwell-U E0) / Core M (Broadwell-Y E0)"); FMSQ( 0, 6, 3,13, 4, MC, "Intel Mobile Celeron 3000 (Broadwell-U E0)"); FMSQ( 0, 6, 3,13, 4, dC, "Intel Celeron 3000 (Broadwell-U E0)"); FMSQ( 0, 6, 3,13, 4, dP, "Intel Pentium 3700U / 3800U / 3200U (Broadwell-U E0)"); // only MRG* 2018-03-06, 2019-08-31 FMS ( 0, 6, 3,13, 4, "Intel Core (unknown type) (Broadwell-U/Y E0)"); FMQ ( 0, 6, 3,13, dc, "Intel Core i*-5000 (Broadwell-U) / Core M (Broadwell-Y)"); FMQ ( 0, 6, 3,13, MC, "Intel Mobile Celeron 3000 (Broadwell-U)"); FMQ ( 0, 6, 3,13, dC, "Intel Celeron 3000 (Broadwell-U)"); FMQ ( 0, 6, 3,13, dP, "Intel Pentium 3700U / 3800U / 3200U (Broadwell-U)"); // only MRG* 2018-03-06, 2019-08-31 FM ( 0, 6, 3,13, "Intel Core (unknown type) (Broadwell-U/Y)"); // Intel docs (329189, 329368, 329597). FMSQ( 0, 6, 3,14, 4, sX, "Intel Xeon E5-1600/E5-2600 v2 (Ivy Bridge-EP C1/M1/S1)"); FMSQ( 0, 6, 3,14, 4, dc, "Intel Core i*-4000 (Ivy Bridge-E S1)"); FMS ( 0, 6, 3,14, 4, "Intel Core (unknown type) (Ivy Bridge-EP C1/M1/S1)"); FMSQ( 0, 6, 3,14, 7, sX, "Intel Xeon E5-4600 / E7-2800 / E7-4800 / E7-8800 v2 (Ivy Bridge-EX D1)"); // E5-4600 names from MRG* 2018-03-06, 2019-08-31 FMS ( 0, 6, 3,14, 7, "Intel Xeon (unknown type) (Ivy Bridge-EX D1)"); FMQ ( 0, 6, 3,14, sX, "Intel Xeon E5-1600 / E5-2600 v2 (Ivy Bridge-EP) / Xeon E5-4600 / E7-2800 / E7-4800 / E7-8800 (Ivy Bridge-EX)"); FMQ ( 0, 6, 3,14, dc, "Intel Core i9-4000 (Ivy Bridge-E)"); FM ( 0, 6, 3,14, "Intel Core (unknown type) (Ivy Bridge-E / Ivy Bridge-EP / Ivy Bridge-EX)"); // Intel docs (330785, 330841, 332317). FMSQ( 0, 6, 3,15, 2, dc, "Intel Core i7-5000 Extreme Edition (Haswell-E R2)"); FMSQ( 0, 6, 3,15, 2, sX, "Intel Xeon E5-x600 v3 (Haswell-EP C1/M1/R2)"); FMS ( 0, 6, 3,15, 2, "Intel (unknown type) (Haswell C1/M1/R2)"); FMS ( 0, 6, 3,15, 4, "Intel Xeon E7-4800 / E7-8800 v3 (Haswell-EP E0)"); FM ( 0, 6, 3,15, "Intel Core (unknown type) (Haswell R2 / Haswell-EP)"); // Intel docs (328903) omit the stepping numbers for (0,6),(4,5) C0 & D0. // MRG* 2019-08-31 mentions stepping 1, but doesn't specify which stepping name it is. // Coreboot* identifies the 0 stepping as B0, but not what the 1 stepping is. FMSQ( 0, 6, 4, 5, 0, dc, "Intel Core i*-4000U (Haswell-ULT B0)"); // no docs, but example from Brice Goglin FMSQ( 0, 6, 4, 5, 0, Mc, "Intel Mobile Core i*-4000Y (Mobile U/Y) (Haswell-ULT B0)"); FMSQ( 0, 6, 4, 5, 0, MP, "Intel Mobile Pentium 3500U / 3600U / 3500Y (Mobile U/Y) (Haswell-ULT B0)"); FMSQ( 0, 6, 4, 5, 0, MC, "Intel Mobile Celeron 2900U (Mobile U/Y) (Haswell-ULT B0)"); FMS ( 0, 6, 4, 5, 0, "Intel Core (unknown type) (Haswell-ULT B0)"); FMSQ( 0, 6, 4, 5, 1, dc, "Intel Core i*-4000U (Haswell-ULT C0/D0)"); // no docs, but example from Brice Goglin FMSQ( 0, 6, 4, 5, 1, Mc, "Intel Mobile Core i*-4000Y (Mobile U/Y) (Haswell-ULT C0/D0)"); FMSQ( 0, 6, 4, 5, 1, MP, "Intel Mobile Pentium 3500U / 3600U / 3500Y (Mobile U/Y) (Haswell-ULT C0/D0)"); FMSQ( 0, 6, 4, 5, 1, MC, "Intel Mobile Celeron 2900U (Mobile U/Y) (Haswell-ULT C0/D0)"); FMS ( 0, 6, 4, 5, 1, "Intel Core (unknown type) (Haswell-ULT C0/D0)"); // ILPMDF* 20190514 FMQ ( 0, 6, 4, 5, dc, "Intel Core i*-4000U (Haswell-ULT)"); // no docs, but example from Brice Goglin FMQ ( 0, 6, 4, 5, Mc, "Intel Mobile Core i*-4000Y (Mobile U/Y) (Haswell-ULT)"); FMQ ( 0, 6, 4, 5, MP, "Intel Mobile Pentium 3500U / 3600U / 3500Y (Mobile U/Y) (Haswell-ULT)"); FMQ ( 0, 6, 4, 5, MC, "Intel Mobile Celeron 2900U (Mobile U/Y) (Haswell-ULT)"); FM ( 0, 6, 4, 5, "Intel Core (unknown type) (Haswell-ULT)"); // Intel docs (328899,328903) omit the stepping numbers for (0,6),(4,6) C0 & D0. // MRG* mentions (0,6),(4,6),1, but doesn't specify which stepping name it is. // An instlatx64 sample claims stepping 1 is C1. // ILPMDF* 20190514 claims stepping 1 is C0. FMSQ( 0, 6, 4, 6, 1, Mc, "Intel Mobile Core i*-4000Y (Mobile H) (Crystal Well C0)"); FMSQ( 0, 6, 4, 6, 1, dc, "Intel Core i*-4000 / Mobile Core i*-4000 (Desktop R) (Crystal Well C0)"); FMSQ( 0, 6, 4, 6, 1, MP, "Intel Mobile Pentium 3500U / 3600U / 3500Y (Mobile H) (Crystal Well C0)"); FMSQ( 0, 6, 4, 6, 1, dC, "Intel Celeron G1800 (Desktop R) (Crystal Well C0)"); FMSQ( 0, 6, 4, 6, 1, MC, "Intel Mobile Celeron 2900U (Mobile H) (Crystal Well C0)"); FMSQ( 0, 6, 4, 6, 1, dP, "Intel Pentium G3000 (Desktop R) (Crystal Well C0)"); FMS ( 0, 6, 4, 6, 1, "Intel Core (unknown type) (Crystal Well C1)"); FMQ ( 0, 6, 4, 6, Mc, "Intel Mobile Core i*-4000Y (Mobile H) (Crystal Well)"); FMQ ( 0, 6, 4, 6, dc, "Intel Core i*-4000 / Mobile Core i*-4000 (Desktop R) (Crystal Well)"); FMQ ( 0, 6, 4, 6, MP, "Intel Mobile Pentium 3500U / 3600U / 3500Y (Mobile H) (Crystal Well)"); FMQ ( 0, 6, 4, 6, dC, "Intel Celeron G1800 (Desktop R) (Crystal Well)"); FMQ ( 0, 6, 4, 6, MC, "Intel Mobile Celeron 2900U (Mobile H) (Crystal Well)"); FMQ ( 0, 6, 4, 6, dP, "Intel Pentium G3000 (Desktop R) (Crystal Well)"); FM ( 0, 6, 4, 6, "Intel Core (unknown type) (Crystal Well)"); // So far, all these (0,6),(4,7) processors are stepping G0, but the // Intel docs (332381, 332382) omit the stepping number for G0. // MRG* 2018-03-06 describes Broadwell H 43e. // ILPMDF* 20190514 mentions Broadwell E0. FMSQ( 0, 6, 4, 7, 1, dc, "Intel Core i*-5000 (Broadwell E0/G0)"); FMSQ( 0, 6, 4, 7, 1, Mc, "Intel Mobile Core i7-5000 (Broadwell E0/G0)"); FMSQ( 0, 6, 4, 7, 1, sX, "Intel Xeon E3-1200 v4 (Broadwell E0/G0)"); FMS ( 0, 6, 4, 7, 1, "Intel (unknown type) (Broadwell-H E0/G0)"); FMQ ( 0, 6, 4, 7, dc, "Intel Core i7-5000 (Broadwell)"); FMQ ( 0, 6, 4, 7, Mc, "Intel Mobile Core i7-5000 (Broadwell)"); FMQ ( 0, 6, 4, 7, sX, "Intel Xeon E3-1200 v4 (Broadwell)"); FM ( 0, 6, 4, 7, "Intel Core (unknown type) (Broadwell)"); // no spec update; only MSR_CPUID_table* so far // MRG* 2018-03-06 mentions steppings 8 and 9, but without names for either. FM ( 0, 6, 4,10, "Intel Atom Z3400 (Merrifield)"); // Intel docs (332095). FMSQ( 0, 6, 4,12, 3, dC, "Intel Celeron N3000 / J3000 (Braswell C0)"); FMSQ( 0, 6, 4,12, 3, dP, "Intel Pentium N3000 / J3000 (Braswell C0)"); FMSQ( 0, 6, 4,12, 3, da, "Intel Atom x5-E8000 / x*-Z8000 (Cherry Trail C0)"); // no spec update; only MRG* 2018-03-06, 2019-08-31 FMS ( 0, 6, 4,12, 3, "Intel Atom (unknown type) (Braswell/Cherry Trail C0)"); FMSQ( 0, 6, 4,12, 4, dC, "Intel Celeron N3000 / J3000 (Braswell D1)"); FMSQ( 0, 6, 4,12, 4, dP, "Intel Pentium N3000 / J3000 (Braswell D1)"); FMSQ( 0, 6, 4,12, 4, da, "Intel Atom x5-E8000 / x*-Z8000 (Cherry Trail D1)"); // no spec update; only MRG* 2018-03-06, 2019-08-31 FMS ( 0, 6, 4,12, 4, "Intel Atom (unknown type) (Braswell/Cherry Trail D1)"); FMQ ( 0, 6, 4,12, dC, "Intel Celeron N3000 / J3000 (Braswell)"); FMQ ( 0, 6, 4,12, dP, "Intel Pentium N3000 / J3000 (Braswell)"); FMQ ( 0, 6, 4,12, da, "Intel Atom x5-E8000 / x*-Z8000 (Cherry Trail)"); // no spec update; only MRG* 2018-03-06, 2019-08-31 FM ( 0, 6, 4,12, "Intel Atom (unknown type) (Braswell/Cherry Trail)"); // Intel docs (329460, 330061). FMS ( 0, 6, 4,13, 0, "Intel Atom C2000 (Avoton A0/A1)"); FMS ( 0, 6, 4,13, 8, "Intel Atom C2000 (Avoton/Rangeley B0/C0)"); FM ( 0, 6, 4,13, "Intel Atom C2000 (Avoton)"); // Intel docs (332689) omit the stepping numbers for (0,6),(4,14) D1 & K1. // MRG* 2018-03-06 mentions (0,6),(4,14),3, but doesn't specify which // stepping name it is. // Coreboot* identifies the 2 (C0) & 3 (D0) steppings, neither of which is // mentioned in (332689). // Coreboot* identifies stepping 8 as (Kaby Lake G0). Perhaps they were just // early engineering samples of Kaby Lake. // ILPMDF* 20190514 pairs stepping 3 with both D0/K1 names. FMSQ( 0, 6, 4,14, 2, dc, "Intel Core i*-6000U / m*-6Y00 (Skylake C0)"); FMSQ( 0, 6, 4,14, 2, dP, "Intel Pentium 4405U / Pentium 4405Y (Skylake C0)"); FMSQ( 0, 6, 4,14, 2, dC, "Intel Celeron 3800U / 39000U (Skylake C0)"); FMSQ( 0, 6, 4,14, 2, sX, "Intel Xeon E3-1500m (Skylake C0)"); // no spec update; only MSR_CPUID_table* so far FMS ( 0, 6, 4,14, 2, "Intel Core (unknown type) (Skylake C0)"); FMSQ( 0, 6, 4,14, 3, dc, "Intel Core i*-6000U / m*-6Y00 (Skylake D0)"); FMSQ( 0, 6, 4,14, 3, dP, "Intel Pentium 4405U / Pentium 4405Y (Skylake D0)"); FMSQ( 0, 6, 4,14, 3, dC, "Intel Celeron 3800U / 39000U (Skylake D0)"); FMSQ( 0, 6, 4,14, 3, sX, "Intel Xeon E3-1500m (Skylake D0)"); // no spec update; only MSR_CPUID_table* so far FMS ( 0, 6, 4,14, 3, "Intel Core (unknown type) (Skylake D0)"); FMS ( 0, 6, 4,14, 8, "Intel Core (unknown type) (Kaby Lake G0)"); // Coreboot* FMQ ( 0, 6, 4,14, dc, "Intel Core i*-6000U / m*-6Y00 (Skylake)"); FMQ ( 0, 6, 4,14, dP, "Intel Pentium 4405U / Pentium 4405Y (Skylake)"); FMQ ( 0, 6, 4,14, dC, "Intel Celeron 3800U / 39000U (Skylake)"); FMQ ( 0, 6, 4,14, sX, "Intel Xeon E3-1500m (Skylake)"); // no spec update; only MSR_CPUID_table* so far FM ( 0, 6, 4,14, "Intel Core (unknown type) (Skylake)"); // Intel docs (333811, 334165) omit the stepping numbers for (0,6),(4,15) // B0, M0 & R0, but (334208) provide some. // ILPMDF* 20190514 mentions all 3 names for stepping 1, but it's unclear // which stepping name applies to which product. FMSQ( 0, 6, 4,15, 1, dc, "Intel Core i7-6800K / i7-6900K / i7-6900X (Broadwell-E R0)"); FMQ ( 0, 6, 4,15, dc, "Intel Core i7-6800K / i7-6900K / i7-6900X (Broadwell-E)"); FMSQ( 0, 6, 4,15, 1, sX, "Intel Xeon E5-1600 / E5-2600 / E5-4600 v4 (Broadwell-E) / E7-4800 / E7-8800 v4 (Broadwell-EX B0)"); FMQ ( 0, 6, 4,15, sX, "Intel Xeon E5-1600 / E5-2600 / E5-4600 v4 (Broadwell-E) / E7-4800 / E7-8800 v4 (Broadwell-EX)"); FM ( 0, 6, 4,15, "Intel Core (unknown type) (Broadwell-E / Broadwell-EX)"); // Intel docs (335901) omit almost all details for the Core versions of // (0,6),(5,5). // Other Intel docs provide some: // 336065: Xeon Scalable steppings 2 & 4, // 338848: Xeon Scalable (2nd gen) stepping 7 // 338854: Xeon D-2000 stepping 2 // 634897: Xeon Scalable (3rd gen) steppings 10 & 11 // MRG* 2019-11-13 mentions stepping 3, but doesn't mention stepping name. // geekbench.com has an "Intel Xeon Gold 6230" example of a stepping 5, but // no stepping name. // Intel's "Retpoline: A Branch Target Injection Mitigation" mentions // steppings 11 & 12, but no stepping names (or even // Skylake/Cascade Lake/Cooper Lake differentiation). FMSQ( 0, 6, 5, 5, 2, sS, "Intel Xeon Scalable Bronze/Silver/Gold/Platinum (Skylake B0/L0)"); FMSQ( 0, 6, 5, 5, 2, sX, "Intel Xeon W 2000 / D-2100 (Skylake B0/L0)"); FMSQ( 0, 6, 5, 5, 3, sS, "Intel Xeon Scalable Bronze/Silver/Gold/Platinum (Skylake B1)"); // ILPMDF* 2019112 FMSQ( 0, 6, 5, 5, 4, sS, "Intel Xeon Scalable Bronze/Silver/Gold/Platinum (Skylake H0/M0/U0)"); FMSQ( 0, 6, 5, 5, 4, sX, "Intel Xeon W 2000 / D-2100 (Skylake H0/M0/U0)"); // D-2100 from MRG* 2018-03-06 FMSQ( 0, 6, 5, 5, 4, dc, "Intel Core i9-7000X (Skylake-X H0/M0/U0)"); // only from MRG* 2018-03-06 FMSQ( 0, 6, 5, 5, 4, iM, "Montage Jintide Gen1"); // undocumented; only instlatx64 example FMSQ( 0, 6, 5, 5, 5, sS, "Intel Xeon Scalable (2nd Gen) Bronze/Silver/Gold/Platinum (Cascade Lake A0)"); // ILPMDF* 20210608 FMSQ( 0, 6, 5, 5, 6, sS, "Intel Xeon Scalable (2nd Gen) Bronze/Silver/Gold/Platinum (Cascade Lake B0)"); // ILPMDF* 20191112, example from Greg Stewart FMSQ( 0, 6, 5, 5, 6, sX, "Intel Xeon W 2000 (Cascade Lake B0)"); // no docs, but example from Greg Stewart FMSQ( 0, 6, 5, 5, 7, dc, "Intel Core i*-10000X (Cascade Lake-X B1/L1/R1)"); // no docs, but instlatx64 example FMSQ( 0, 6, 5, 5, 7, sS, "Intel Xeon Scalable (2nd Gen) Bronze/Silver/Gold/Platinum (Cascade Lake B1/L1/R1)"); FMSQ( 0, 6, 5, 5, 7, sX, "Intel Xeon W 2000 (Cascade Lake-W B1/L1/R1)"); FMSQ( 0, 6, 5, 5, 10, sS, "Intel Xeon Scalable (3rd Gen) Bronze/Silver/Gold/Platinum (Cooper Lake A0)"); FMS ( 0, 6, 5, 5, 10, "Intel (unknown type) (Cooper Lake A0)"); FMSQ( 0, 6, 5, 5, 11, sS, "Intel Xeon Scalable (3rd Gen) Bronze/Silver/Gold/Platinum (Cooper Lake A1)"); FMS ( 0, 6, 5, 5, 11, "Intel (unknown type) (Cooper Lake A1)"); FMQ ( 0, 6, 5, 5, sS, "Intel Xeon Scalable Bronze/Silver/Gold/Platinum (Skylake / Cascade Lake)"); FMQ ( 0, 6, 5, 5, sX, "Intel Xeon W 2000 / D-2100 (Skylake / Cascade Lake)"); FMQ ( 0, 6, 5, 5, dc, "Intel Core i*-6000X / i*-7000X (Skylake-X) / i*-10000X (Cascade Lake-X)"); FM ( 0, 6, 5, 5, "Intel Core (unknown type) (Skylake / Skylake-X / Cascade Lake / Cascade Lake-X)"); // Intel docs (332054). FMS ( 0, 6, 5, 6, 1, "Intel Xeon D-1500 (Broadwell-DE U0)"); FMS ( 0, 6, 5, 6, 2, "Intel Xeon D-1500 (Broadwell-DE V1)"); FMS ( 0, 6, 5, 6, 3, "Intel Xeon D-1500 (Broadwell-DE V2/V3)"); // V3 from MRG* 2018-03-06 FMS ( 0, 6, 5, 6, 4, "Intel Xeon D-1500 (Broadwell-DE Y0)"); // SSG* suggests that FMS (0,6),(5,6),5 may also include some Xeon D-16xx // (Hewitt Lake) instances, but I've seen none, and am not sure how to // distinguish. FMS ( 0, 6, 5, 6, 5, "Intel Xeon D-1500N (Broadwell-DE A1)"); FM ( 0, 6, 5, 6, "Intel Xeon (unknown type) (Broadwell-DE)"); // Intel docs (334646) omit the stepping number for B0. But as of Jan 2020, // it is the only stepping, and all examples seen have stepping number 1. FMS ( 0, 6, 5, 7, 1, "Intel Xeon Phi x200 (Knights Landing B0)"); FM ( 0, 6, 5, 7, "Intel Xeon Phi x200 (Knights Landing)"); FM ( 0, 6, 5,10, "Intel Atom Z3500 (Moorefield)"); // no spec update; only MSR_CPUID_table* & instlatx64 example so far // Intel docs (334820) & MRG* 2018-03-06 // Coreboot* provides stepping 8 (A0). FMS ( 0, 6, 5,12, 2, "Intel Atom T5000 (Apollo Lake)"); // no spec update; only MRG* 2018-03-06 FMS ( 0, 6, 5,12, 8, "Intel Atom (unknown type) (Apollo Lake A0)"); FMSQ( 0, 6, 5,12, 9, dP, "Intel Pentium N4000 / J4000 (Apollo Lake B0/B1/D0)"); FMSQ( 0, 6, 5,12, 9, dC, "Intel Celeron N3000 / J3000 (Apollo Lake B0/B1/D0)"); FMSQ( 0, 6, 5,12, 9, da, "Intel Atom x*-E3900 / x*-A3900 (Apollo Lake B0/B1/D0)"); // A3900 only from MRG* 2019-08-31 FMS ( 0, 6, 5,12, 9, "Intel Atom (unknown type) (Apollo Lake B0/B1/D0)"); FMSQ( 0, 6, 5,12, 10, da, "Intel Atom x*-E3900 (Apollo Lake E0)"); FMS ( 0, 6, 5,12, 10, "Intel Atom (unknown type) (Apollo Lake E0)"); FM ( 0, 6, 5,12, "Intel Atom (unknown type) (Apollo Lake)"); // no spec update for Atom; only MSR_CPUID_table* so far // No spec update; only MSR_CPUID_table* so far (and instlatx64 example) // MRG* 2018-03-06 mentions (0,6),(5,13),1 stepping, but doesn't mention stepping name. FM ( 0, 6, 5,13, "Intel Atom x3-C3000 (SoFIA)"); // Intel docs (332689,333133) omit the stepping numbers for (0,6),(5,14) // R0 & S0. // MRG* 2018-03-06 mentions (0,6),(5,14),3, but doesn't specify which // stepping name it is. // Coreboot* identifies the 1 (Q0) & 3 (R0) steppings, but not the S0 // stepping. // Coreboot* identifies stepping 8 as (Kaby Lake-H A0). Perhaps they were just // early engineering samples of Kaby Lake. // ILPMDF* 20190514 mentions stepping 3 as Skylake-H/S steppings N0/R0. // ILPMDF* 20191115 mentions stepping 3 as Skylake-H/S/E3 steppings N0/R0/S0. FMSQ( 0, 6, 5,14, 1, dc, "Intel Core i*-6000 (Skylake-H Q0)"); FMSQ( 0, 6, 5,14, 1, dP, "Intel Pentium G4000 (Skylake-H Q0)"); FMSQ( 0, 6, 5,14, 1, dC, "Intel Celeron G3900 (Skylake-H Q0)"); FMSQ( 0, 6, 5,14, 1, sX, "Intel Xeon E3-1200 / E3-1500 v5 (Skylake-H Q0)"); // E3-1500 only from MRG 2019-08-31 FMS ( 0, 6, 5,14, 1, "Intel Core (unknown type) (Skylake-H Q0)"); FMSQ( 0, 6, 5,14, 3, dc, "Intel Core i*-6000 (Skylake-H/S/E3 R0/N0/S0)"); FMSQ( 0, 6, 5,14, 3, dP, "Intel Pentium G4000 (Skylake-H/S/E3 R0/N0/S0)"); FMSQ( 0, 6, 5,14, 3, dC, "Intel Celeron G3900 (Skylake-H/S/E3 R0/N0/S0)"); FMSQ( 0, 6, 5,14, 3, sX, "Intel Xeon E3-1200 / E3-1500 v5 (Skylake-H/S/E3 R0/N0/S0)"); // E3-1500 only from MRG 2019-08-31 FMS ( 0, 6, 5,14, 3, "Intel Core (unknown type) (Skylake-H/S/E3 R0/N0/S0)"); FMS ( 0, 6, 5,14, 8, "Intel Core (unknown type) (Kaby Lake-H A0)"); // Coreboot* FMQ ( 0, 6, 5,14, dc, "Intel Core i*-6000 (Skylake-H)"); FMQ ( 0, 6, 5,14, dP, "Intel Pentium G4000 (Skylake-H)"); FMQ ( 0, 6, 5,14, dC, "Intel Celeron G3900 (Skylake-H)"); FMQ ( 0, 6, 5,14, sX, "Intel Xeon E3-1200 / E3-1500 v5 (Skylake-H)"); // E3-1500 only from MRG 2019-08-31 FM ( 0, 6, 5,14, "Intel Core (unknown type) (Skylake-H)"); // Intel docs (336345). FMS ( 0, 6, 5,15, 0, "Intel Atom C3000 (Denverton A0/A1)"); FMS ( 0, 6, 5,15, 1, "Intel Atom C3000 (Denverton B0/B1)"); FM ( 0, 6, 5,15, "Intel Atom C3000 (Denverton)"); FM ( 0, 6, 6, 5, "Intel XMM 7272 (SoFIA)"); // no spec update; only MRG* 2018-03-06, 2019-08-31 // no spec update; only MSR_CPUID_table* & instlatx64 example so far // Coreboot* provides the steppings. FMS ( 0, 6, 6, 6, 0, "Intel Core (Cannon Lake A0)"); FMS ( 0, 6, 6, 6, 1, "Intel Core (Cannon Lake B0)"); FMS ( 0, 6, 6, 6, 2, "Intel Core (Cannon Lake C0)"); FMS ( 0, 6, 6, 6, 3, "Intel Core (Cannon Lake D0)"); FM ( 0, 6, 6, 6, "Intel Core (Cannon Lake)"); FM ( 0, 6, 6, 7, "Intel Core (Cannon Lake)"); // DPTF* FMSQ( 0, 6, 6,10, 5, sS, "Intel Xeon Scalable (3rd Gen) Bronze/Silver/Gold/Platinum (Ice Lake-SP C0)"); // ILPMDF* 20210608 FMS ( 0, 6, 6,10, 5, "Intel Xeon (unknown type) (Ice Lake-SP C0)"); // ILPMDF* 20210608 FMSQ( 0, 6, 6,10, 6, sS, "Intel Xeon Scalable (3rd Gen) Bronze/Silver/Gold/Platinum (Ice Lake-SP D2/M1)"); FMS ( 0, 6, 6,10, 6, "Intel Xeon (unknown type) (Ice Lake-SP D2/M1)"); FMQ ( 0, 6, 6,10, sS, "Intel Xeon Scalable (3rd Gen) Bronze/Silver/Gold/Platinum (Ice Lake-SP)"); FM ( 0, 6, 6,10, "Intel Xeon (unknown type) (Ice Lake-SP)"); // Intel docs (714071) claim stepping 1 is U1/U2. // ILPMDF* 20221108 claims ICL-D (Ice Lake Xeon D), and says B0 stepping. // DPTF* claims this is Meteor Lake S FMSQ( 0, 6, 6,12, 1, sX, "Intel Xeon D-1700/2700 (Ice Lake-D U1/U2)"); FMS ( 0, 6, 6,12, 1, "Intel (unknown type) (Ice Lake-D U1/U2)"); FMQ ( 0, 6, 6,12, sX, "Intel Xeon D-1700/2700 (Ice Lake-D)"); FM ( 0, 6, 6,12, "Intel (unknown type) (Ice Lake-D)"); // No spec update; only MRG* 2018-03-06, 2019-08-31. It is some sort of Atom, // but no idea which uarch or core. FM ( 0, 6, 6,14, "Intel Puma 7 (Cougar Mountain)"); // No spec update; only instlatx64 example. FM ( 0, 6, 7, 5, "Intel Spreadtrum SC9853I-IA"); // Intel docs (336562). // MRG* 2019-11-13 mentions stepping 8, but doesn't mention stepping name. // Coreboot* provides steppings 0 (A0) & 8 (R0). FMSQ( 0, 6, 7,10, 0, dP, "Intel Pentium Silver N5000 / J5000 (Gemini Lake A0)"); FMSQ( 0, 6, 7,10, 0, dC, "Intel Celeron N4000 / J4000 (Gemini Lake A0)"); FMS ( 0, 6, 7,10, 0, "Intel (unknown type) (Gemini Lake A0)"); FMSQ( 0, 6, 7,10, 1, dP, "Intel Pentium Silver N5000 / J5000 (Gemini Lake B0)"); FMSQ( 0, 6, 7,10, 1, dC, "Intel Celeron N4000 / J4000 (Gemini Lake B0)"); FMS ( 0, 6, 7,10, 1, "Intel (unknown type) (Gemini Lake B0)"); FMSQ( 0, 6, 7,10, 8, dP, "Intel Pentium Silver N5000 / J5000 (Gemini Lake R0)"); FMSQ( 0, 6, 7,10, 8, dC, "Intel Celeron N4000 / J4000 (Gemini Lake R0)"); FMS ( 0, 6, 7,10, 8, "Intel (unknown type) (Gemini Lake R0)"); FMQ ( 0, 6, 7,10, dP, "Intel Pentium Silver N5000 / J5000 (Gemini Lake)"); FMQ ( 0, 6, 7,10, dC, "Intel Celeron N4000 / J4000 (Gemini Lake)"); FM ( 0, 6, 7,10, "Intel (unknown type) (Gemini Lake)"); FM ( 0, 6, 7,13, "Intel Core i*-10000 (Ice Lake)"); // no spec update; only MSR_CPUID_table* so far // Intel docs (341079) provide inconsistent information about stepping // numbers for (0,6),(7,14), and it contradicts actual samples, so I'm // ignoring it. // Currently there are no Ice Lake CPUs for Xeon/Pentium/Celeron. // Coreboot* provides steppings 0 (A0) & 1 (B0), but not for stepping 5. // ILPMDF* 2019112 claims that stepping 5 is D1. FMS ( 0, 6, 7,14, 0, "Intel Core i*-10000 (Ice Lake-U/Y A0)"); FMS ( 0, 6, 7,14, 1, "Intel Core i*-10000 (Ice Lake-U/Y B0)"); FMS ( 0, 6, 7,14, 5, "Intel Core i*-10000 (Ice Lake-U/Y D1)"); FM ( 0, 6, 7,14, "Intel Core i*-10000 (Ice Lake-U/Y)"); // no spec update; only MSR_CPUID_table* so far // MRG* 2018-03-06 mentions stepping 0, but doesn't specify which stepping name it is. FM ( 0, 6, 8, 5, "Intel Xeon Phi (Knights Mill)"); // no spec update; only MSR_CPUID_table* & SSG* so far. // SSG* provides the 4,5,7 steppings. FMS ( 0, 6, 8, 6, 4, "Intel Atom P5900 (Snow Ridge B0)"); FMS ( 0, 6, 8, 6, 5, "Intel Atom P5900 (Snow Ridge B1)"); FMS ( 0, 6, 8, 6, 7, "Intel Atom P5300 / P5700 (Snow Ridge) / C5000 (Parker Ridge)"); FM ( 0, 6, 8, 6, "Intel Atom (Snow Ridge/Parker Ridge)"); // No spec update; LX* // ILPMDF* 20201110 names stepping 1 as B2/B3. // SSG* 2022 also mentions it, but does so ambiguously. FMSQ( 0, 6, 8,10, 1, Ha, "Intel Core i*-L1000 E-core (Lakefield B2/B3)"); // instlatx64 sample FMSQ( 0, 6, 8,10, 1, Hc, "Intel Core i*-L1000 P-core (Lakefield B2/B3)"); // instlatx64 sample FMS ( 0, 6, 8,10, 1, "Intel Core i*-L1000 (Lakefield B2/B3)"); FMQ ( 0, 6, 8,10, Ha, "Intel Core i*-L1000 E-core (Lakefield)"); FMQ ( 0, 6, 8,10, Hc, "Intel Core i*-L1000 P-core (Lakefield)"); FM ( 0, 6, 8,10, "Intel Core i*-L1000 (Lakefield)"); // Intel docs (631123) mention steppings 1 & 2, but provide no names. // ILPMDF* 20201110 names stepping 1 as B1. // ILPMDF* 20210608 names stepping 2 as C0. FMS ( 0, 6, 8,12, 0, "Intel Core (Tiger Lake-U A0)"); FMSQ( 0, 6, 8,12, 1, dC, "Intel Celeron 6000 (Tiger Lake-U B0/B1)"); FMSQ( 0, 6, 8,12, 1, dP, "Intel Pentium Gold 7505 (Tiger Lake-U B0/B1)"); FMSQ( 0, 6, 8,12, 1, dc, "Intel Core i*-11000 / i*-1100G* (Tiger Lake-U B0/B1)"); FMS ( 0, 6, 8,12, 1, "Intel (unknown type) (Tiger Lake-U B0/B1)"); FMSQ( 0, 6, 8,12, 2, dc, "Intel Core i*-11000 / i*-1100G* (Tiger Lake-U C0)"); FMS ( 0, 6, 8,12, 2, "Intel (unknown type) (Tiger Lake-U C0)"); FMQ ( 0, 6, 8,12, dC, "Intel Celeron (Tiger Lake-U)"); FMQ ( 0, 6, 8,12, dP, "Intel Pentium (Tiger Lake-U)"); FMQ ( 0, 6, 8,12, dc, "Intel Core (Tiger Lake-U)"); FM ( 0, 6, 8,12, "Intel (unknown type) (Tiger Lake-U)"); // no spec update; only MSR_CPUID_table* and SSG* so far. SSG* provides H suffix. // Coreboot* provides stepping name. FMS ( 0, 6, 8,13, 0, "Intel Core (Tiger Lake-H P0)"); // LX* FMS ( 0, 6, 8,13, 1, "Intel Core (Tiger Lake-H R0)"); FM ( 0, 6, 8,13, "Intel Core (Tiger Lake-H)"); // Intel docs (334663) omit the stepping numbers for (0,6),(8,14) // H0, J1 & Y0, but (338025, 615213) provide some. // Coreboot* provides the 9 (H0) & 10 (Y0) stepping, but not J1. // ILPMDF* 20191115 mentions stepping 9 related to a KBL-U23e J1 stepping, // but I have no means of identifying a KBL-U23e. FMSQ( 0, 6, 8,14, 9, UC, "Intel Celeron 3x65U (Kaby Lake H0)"); // MRG* 2019-08-31 pinned down stepping FMSQ( 0, 6, 8,14, 9, UP, "Intel Celeron 4415U (Kaby Lake H0)"); // MRG* 2019-08-31 pinned down stepping FMSQ( 0, 6, 8,14, 9, YC, "Intel Celeron 3x65Y (Kaby Lake H0)"); // MRG* 2019-08-31 pinned down stepping FMSQ( 0, 6, 8,14, 9, YP, "Intel Pentium / Celeron 4400Y (Kaby Lake H0)"); // MRG* 2019-08-31 pinned down stepping FMSQ( 0, 6, 8,14, 9, Y8, "Intel i*-8000Y / m*-8000Y (Amber Lake-Y H0)"); // no spec update; only MRG* 2019-08-31 & instlatx64 examples FMSQ( 0, 6, 8,14, 9, LY, "Intel Core i*-7000Y (Kaby Lake H0)"); // no spec update; only MRG* 2019-08-31 & instlatx64 examples FMSQ( 0, 6, 8,14, 9, dc, "Intel Core i*-7000U (Kaby Lake H0)"); // no docs on stepping; MRG* 2018-03-06, 2019-08-31 FMSQ( 0, 6, 8,14, 10, dc, "Intel Core i*-8000U (Kaby Lake Y0 / Coffee Lake D0)"); // no docs on stepping; MRG* 2018-04-02, ILPMDF* 20190312 FMSQ( 0, 6, 8,14, 11, LU, "Intel Core i*-8000U (Whiskey Lake-U W0)"); FMSQ( 0, 6, 8,14, 11, LY, "Intel Core i*-8000Y (Amber Lake-Y W0)"); FMSQ( 0, 6, 8,14, 11, UC, "Intel Celeron 4205U (Whiskey Lake-U W0)"); FMSQ( 0, 6, 8,14, 11, UP, "Intel Pentium 5405U (Whiskey Lake-U W0)"); FMS ( 0, 6, 8,14, 11, "Intel Core (unknown type) (Whiskey Lake-U W0 / Amber Lake-Y W0)"); FMSQ( 0, 6, 8,14, 12, UX, "Intel Core i*-10000U (Comet Lake-U V1)"); FMSQ( 0, 6, 8,14, 12, LU, "Intel Core i*-8000U (Whiskey Lake-U V0)"); FMSQ( 0, 6, 8,14, 12, LY, "Intel Core i*-8000Y / m*-8000Y / i*-10000Y (Amber Lake-Y V0)"); // m*-8000Y & i*-10000Y from MRG* 2019-11-13 FMSQ( 0, 6, 8,14, 12, dP, "Intel Pentium 6000U (Comet Lake-U V1)"); // MRG* 2019-08-31 pinned down stepping FMSQ( 0, 6, 8,14, 12, dC, "Intel Celeron 5000U (Comet Lake-U V1)"); // MRG* 2019-08-31 pinned down stepping FMS ( 0, 6, 8,14, 12, "Intel (unknown type) (Whiskey Lake-U V0 / Comet Lake-U V1)"); FMS ( 0, 6, 8,14, 13, "Intel (unknown type) (Whiskey Lake-U V0)"); // ILPMDF* 20190312 FM ( 0, 6, 8,14, "Intel Core (unknown type) (Kaby Lake / Amber Lake-Y / Whiskey Lake-U / Comet Lake-U)"); // MSR_CPUID_table*, LX* // coreboot*, based on confidential Sapphire Rapids External Design // Specification doc (612246), provides steppings D & E0. // Intel docs (772415) say stepping 8 = E5/E4/B3/S3/S2. // ILPMDF* 20230214 provides steppings E2, E3, E4, E5. // ILPMDF* 20230214 mentions that stepping 8 also is Sapphire Rapids HBM // ILPMDF* 20230512 mentions that steppings 7 & 8 also are steppings S2 & S3. // (Xeon Max) B3. Maybe describe that better if I can distinguish them. // instlatx64 provides a Xeon W sample, but I've seen no spec update for it. Assuming they could be any stepping. FMSQ( 0, 6, 8,15, 3, sS, "Intel Xeon Scalable (4th Gen) Bronze/Silver/Gold/Platinum (Sapphire Rapids D)"); FMSQ( 0, 6, 8,15, 3, sX, "Intel Xeon W 2400/3400 (Sapphire Rapids D)"); FMS ( 0, 6, 8,15, 3, "Intel Xeon (unknown type) (Sapphire Rapids D)"); FMSQ( 0, 6, 8,15, 4, sS, "Intel Xeon Scalable (4th Gen) Bronze/Silver/Gold/Platinum (Sapphire Rapids E0)"); FMSQ( 0, 6, 8,15, 4, sX, "Intel Xeon W 2400/3400 (Sapphire Rapids E0)"); FMS ( 0, 6, 8,15, 4, "Intel Xeon (unknown type) (Sapphire Rapids E0)"); FMSQ( 0, 6, 8,15, 5, sS, "Intel Xeon Scalable (4th Gen) Bronze/Silver/Gold/Platinum (Sapphire Rapids E2)"); FMSQ( 0, 6, 8,15, 5, sX, "Intel Xeon W 2400/3400 (Sapphire Rapids E2)"); FMS ( 0, 6, 8,15, 5, "Intel Xeon (unknown type) (Sapphire Rapids E2)"); FMSQ( 0, 6, 8,15, 6, sS, "Intel Xeon Scalable (4th Gen) Bronze/Silver/Gold/Platinum (Sapphire Rapids E3)"); FMSQ( 0, 6, 8,15, 6, sX, "Intel Xeon W 2400/3400 (Sapphire Rapids E3)"); FMS ( 0, 6, 8,15, 6, "Intel Xeon (unknown type) (Sapphire Rapids E3)"); FMSQ( 0, 6, 8,15, 7, sS, "Intel Xeon Scalable (4th Gen) Bronze/Silver/Gold/Platinum (Sapphire Rapids E4/S2)"); FMSQ( 0, 6, 8,15, 7, sX, "Intel Xeon W 2400/3400 (Sapphire Rapids E4/S2)"); FMS ( 0, 6, 8,15, 7, "Intel Xeon (unknown type) (Sapphire Rapids E4/S2)"); // Intel doc (793902) describes a (0,6),(8,15),8 Sapphire Rapids LCC U1 // rebranded as Xeon Scalable (5th Gen). I suspect differentiating these // will require looking at the brand string. FMSQ( 0, 6, 8,15, 8, sS, "Intel Xeon Scalable (4th Gen) Bronze/Silver/Gold/Platinum (Sapphire Rapids E5/B3/S3) / Xeon Scalable (5th Gen) Bronze/Silver/Gold/Platinum (Sapphire Rapids U1)"); FMSQ( 0, 6, 8,15, 8, sX, "Intel Xeon W 2400/3400 (Sapphire Rapids E5/B3/S3)"); FMS ( 0, 6, 8,15, 8, "Intel Xeon (unknown type) (Sapphire Rapids E5/B3/S3)"); FMQ ( 0, 6, 8,15, sS, "Intel Xeon Scalable (4th Gen) Bronze/Silver/Gold/Platinum (Sapphire Rapids)"); FMQ ( 0, 6, 8,15, sX, "Intel Xeon W 2400/3400 (Sapphire Rapids)"); FM ( 0, 6, 8,15, "Intel Xeon (unknown type) (Sapphire Rapids)"); FM ( 0, 6, 9, 5, "Intel (unknown type) (Sapphire Rapids)"); // Intel SDE 9.24.0 misc/cpuid/spr/cpuid.def // Intel docs (636674) provides stepping B1 only. // LX*. Coreboot* provides other steppings. FMSQ( 0, 6, 9, 6, 0, dC, "Intel Celeron J6400 / N6400 (Elkhart Lake A0)"); FMSQ( 0, 6, 9, 6, 0, dP, "Intel Pentium J6400 / N6400 (Elkhart Lake A0)"); FMSQ( 0, 6, 9, 6, 0, da, "Intel Atom (Elkhart Lake A0)"); FMS ( 0, 6, 9, 6, 0, "Intel (unknown type) (Elkhart Lake A0)"); FMSQ( 0, 6, 9, 6, 1, dC, "Intel Celeron J6400 / N6400 (Elkhart Lake B0/B1)"); FMSQ( 0, 6, 9, 6, 1, dP, "Intel Pentium J6400 / N6400 (Elkhart Lake B0/B1)"); FMSQ( 0, 6, 9, 6, 1, da, "Intel Atom (Elkhart Lake B0/B1)"); FMS ( 0, 6, 9, 6, 1, "Intel (unknown type) (Elkhart Lake B0/B1)"); FMQ ( 0, 6, 9, 6, dC, "Intel Celeron (Elkhart Lake)"); FMQ ( 0, 6, 9, 6, dP, "Intel Pentium (Elkhart Lake)"); FMQ ( 0, 6, 9, 6, da, "Intel Atom (Elkhart Lake)"); FM ( 0, 6, 9, 6, "Intel (unknown type) (Elkhart Lake)"); // Intel docs (682436) mention Core stepping values 2, 5; but omit stepping names. // Coreboot* provides A0, B0, C0, G0, H0 steppings (notably not 3). // Stepping for 4 is dubious because 682436 says Alder Lake-U, // whereas Coreboot* says Alder Lake-S G0. // instlatx64 sample claims stepping 2 is C0. // ILPMDF* 20220510 (and later) claim steppings 2 & 5 *both* are C0. Cut&paste error? FMSQ( 0, 6, 9, 7, 0, Ha, "Intel Core i*-12000 E-core (Alder Lake-S A0)"); FMSQ( 0, 6, 9, 7, 0, Hc, "Intel Core i*-12000 P-core (Alder Lake-S A0)"); FMSQ( 0, 6, 9, 7, 0, dc, "Intel Core i*-12000 (Alder Lake-S A0)"); FMS ( 0, 6, 9, 7, 0, "Intel (unknown type) (Alder Lake-S A0)"); FMSQ( 0, 6, 9, 7, 1, Ha, "Intel Core i*-12000 E-core (Alder Lake-S B0)"); FMSQ( 0, 6, 9, 7, 1, Hc, "Intel Core i*-12000 P-core (Alder Lake-S B0)"); FMSQ( 0, 6, 9, 7, 1, dc, "Intel Core i*-12000 (Alder Lake-S B0)"); FMS ( 0, 6, 9, 7, 1, "Intel (unknown type) (Alder Lake-S B0)"); FMSQ( 0, 6, 9, 7, 2, Ha, "Intel Core i*-12000 E-core (Alder Lake-S/HX C0)"); FMSQ( 0, 6, 9, 7, 2, Hc, "Intel Core i*-12000 P-core (Alder Lake-S/HX C0)"); FMSQ( 0, 6, 9, 7, 2, dc, "Intel Core i*-12000 (Alder Lake-S/HX C0)"); FMS ( 0, 6, 9, 7, 2, "Intel (unknown type) (Alder Lake-S/HX C0)"); FMSQ( 0, 6, 9, 7, 3, Ha, "Intel Core i*-12000 / i*-1200P E-core (Alder Lake-P/H)"); FMSQ( 0, 6, 9, 7, 3, Hc, "Intel Core i*-12000 / i*-1200P P-core (Alder Lake-P/H)"); FMSQ( 0, 6, 9, 7, 3, dc, "Intel Core i*-12000 / i*-1200P (Alder Lake-P/H)"); FMS ( 0, 6, 9, 7, 3, "Intel (unknown type) (Alder Lake-P/H)"); FMSQ( 0, 6, 9, 7, 4, Ha, "Intel Core i*-1200U E-core (Alder Lake-U G0)"); FMSQ( 0, 6, 9, 7, 4, Hc, "Intel Core i*-1200U P-core (Alder Lake-U G0)"); FMSQ( 0, 6, 9, 7, 4, dc, "Intel Core i*-1200U (Alder Lake-U G0)"); FMS ( 0, 6, 9, 7, 4, "Intel (unknown type) (Alder Lake-U G0)"); FMSQ( 0, 6, 9, 7, 5, Ha, "Intel Core i*-12000 E-core (Alder Lake-S H0)"); FMSQ( 0, 6, 9, 7, 5, Hc, "Intel Core i*-12000 P-core (Alder Lake-S H0)"); FMSQ( 0, 6, 9, 7, 5, dc, "Intel Core i*-12000 (Alder Lake-S H0)"); FMSQ( 0, 6, 9, 7, 5, dP, "Intel Pentium Gold G7400 (Alder Lake-S H0)"); FMS ( 0, 6, 9, 7, 5, "Intel (unknown type) (Alder Lake-S H0)"); FMQ ( 0, 6, 9, 7, Ha, "Intel Core i*-12000 E-core (Alder Lake-S/P/H/U)"); FMQ ( 0, 6, 9, 7, Hc, "Intel Core i*-12000 P-core (Alder Lake-S/P/H/U)"); FMQ ( 0, 6, 9, 7, dc, "Intel Core i*-12000 (Alder Lake-S/P/H/U)"); FMQ ( 0, 6, 9, 7, dP, "Intel Pentium Gold G7400 (Alder Lake-S)"); // no docs on Pentium Gold version; instlatx64 sample FM ( 0, 6, 9, 7, "Intel (unknown type) (Alder Lake-S/P/H/U)"); // Intel docs (682436) mention Core stepping values 3, 4; but omit stepping names. // MSR_CPUID_table*, Coreboot*. Coreboot* provides steppings. // ILPMDF* 20220510 (and later) claim steppings 3 & 4 *both* are stepping L0. Cut&paste error? FMSQ( 0, 6, 9,10, 0, Ha, "Intel Core i*-12000 E-core (Alder Lake J0)"); FMSQ( 0, 6, 9,10, 0, Hc, "Intel Core i*-12000 P-core (Alder Lake J0)"); FMSQ( 0, 6, 9,10, 0, dc, "Intel Core i*-12000 (Alder Lake J0)"); FMS ( 0, 6, 9,10, 0, "Intel (unknown type) (Alder Lake J0)"); FMSQ( 0, 6, 9,10, 1, Ha, "Intel Core i*-12000 E-core (Alder Lake Q0)"); FMSQ( 0, 6, 9,10, 1, Hc, "Intel Core i*-12000 P-core (Alder Lake Q0)"); FMSQ( 0, 6, 9,10, 1, dc, "Intel Core i*-12000 (Alder Lake Q0)"); FMS ( 0, 6, 9,10, 1, "Intel (unknown type) (Alder Lake Q0)"); FMSQ( 0, 6, 9,10, 2, Ha, "Intel Core i*-12000 E-core (Alder Lake K0)"); FMSQ( 0, 6, 9,10, 2, Hc, "Intel Core i*-12000 P-core (Alder Lake K0)"); FMSQ( 0, 6, 9,10, 2, dc, "Intel Core i*-12000 (Alder Lake K0)"); FMS ( 0, 6, 9,10, 2, "Intel (unknown type) (Alder Lake K0)"); FMSQ( 0, 6, 9,10, 3, Ha, "Intel Core i*-12000 E-core (Alder Lake L0)"); FMSQ( 0, 6, 9,10, 3, Hc, "Intel Core i*-12000 P-core (Alder Lake L0)"); FMSQ( 0, 6, 9,10, 3, dc, "Intel Core i*-12000 (Alder Lake L0)"); FMS ( 0, 6, 9,10, 3, "Intel (unknown type) (Alder Lake L0)"); FMSQ( 0, 6, 9,10, 4, da, "Intel Atom C1100 (Arizona Beach A0/R0)"); FMSQ( 0, 6, 9,10, 4, Pa, "Intel Pentium Gold 8500 E-core (Alder Lake R0)"); // no docs on Pentium Gold version; only instlatx64 sample FMSQ( 0, 6, 9,10, 4, Pc, "Intel Pentium Gold 8500 P-core (Alder Lake R0)"); // no docs on Pentium Gold version; only instlatx64 sample FMSQ( 0, 6, 9,10, 4, dP, "Intel Pentium Gold 8500 (Alder Lake R0)"); // no docs on Pentium Gold version; only instlatx64 sample FMSQ( 0, 6, 9,10, 4, Ha, "Intel Core i*-12000 E-core (Alder Lake R0)"); FMSQ( 0, 6, 9,10, 4, Hc, "Intel Core i*-12000 P-core (Alder Lake R0)"); FMSQ( 0, 6, 9,10, 4, dc, "Intel Core i*-12000 (Alder Lake R0)"); FMS ( 0, 6, 9,10, 4, "Intel (unknown type) (Alder Lake R0 / Arizona Beach A0/R0)"); FMQ ( 0, 6, 9,10, da, "Intel Atom C1100 (Arizona Beach)"); FMQ ( 0, 6, 9,10, Pa, "Intel Pentium Gold 8500 E-core (Alder Lake)"); FMQ ( 0, 6, 9,10, Pc, "Intel Pentium Gold 8500 P-core (Alder Lake)"); FMQ ( 0, 6, 9,10, dP, "Intel Pentium Gold 8500 (Alder Lake)"); FMQ ( 0, 6, 9,10, Ha, "Intel Core i*-12000 E-core (Alder Lake)"); FMQ ( 0, 6, 9,10, Hc, "Intel Core i*-12000 P-core (Alder Lake)"); FMQ ( 0, 6, 9,10, dc, "Intel Core i*-12000 (Alder Lake)"); FM ( 0, 6, 9,10, "Intel (unknown type) (Alder Lake / Arizona Beach)"); // Intel docs (634542). // LX*. Coreboot* provides stepping name. FMSQ( 0, 6, 9,12, 0, dC, "Intel Celeron N4500 / N5100 (Jasper Lake A0/A1)"); FMSQ( 0, 6, 9,12, 0, dP, "Intel Pentium N6000 (Jasper Lake A0/A1)"); FMS ( 0, 6, 9,12, 0, "Intel (unknown type) (Jasper Lake A0/A1)"); FMQ ( 0, 6, 9,12, dC, "Intel Celeron N4500 / N5100 (Jasper Lake)"); FMQ ( 0, 6, 9,12, dP, "Intel Pentium N6000 (Jasper Lake)"); FM ( 0, 6, 9,12, "Intel (unknown type) (Jasper Lake)"); FM ( 0, 6, 9,13, "Intel NNP I-1000 (Spring Hill)"); // LX* // Intel docs (334663, 335718, 336466, 338014) omit the stepping numbers for // (0,6),(9,14) B0, but (337346) provides some. // Coreboot* provides the 9 (B0) stepping. // WARNING: If adding new steppings here, also update decode_uarch_intel. FMSQ( 0, 6, 9,14, 9, LG, "Intel Core i*-8700 (Kaby Lake-H B0)"); // no docs on stepping; only MRG* 2018-03-06, 2019-08-31 FMSQ( 0, 6, 9,14, 9, dc, "Intel Core i*-7700 (Kaby Lake-H B0)"); // no docs on stepping; only MRG* 2018-03-06 & instlatx64 examplesc FMSQ( 0, 6, 9,14, 9, sX, "Intel Xeon E3-1200 v6 (Kaby Lake-H B0)"); // no docs on stepping; only MRG* 2018-03-06 FMSQ( 0, 6, 9,14, 9, dC, "Intel Celeron G3930 (Kaby Lake-H B0)"); // MRG* 2020-01-27 pinned down stepping FMSQ( 0, 6, 9,14, 10, LU, "Intel Core i*-8000 U Line (Coffee Lake D0)"); FMSQ( 0, 6, 9,14, 10, dP, "Intel Pentium Gold G5000 (Coffee Lake U0)"); // no docs; only Andrey Rahmatullin sample FMSQ( 0, 6, 9,14, 10, dc, "Intel Core i*-8000 S/H Line (Coffee Lake U0)"); FMSQ( 0, 6, 9,14, 10, sX, "Intel Xeon E-2100 (Coffee Lake U0)"); // MRG* 2019-08-31 FMSQ( 0, 6, 9,14, 11, dc, "Intel Core i*-8000 S Line (Coffee Lake B0)"); FMSQ( 0, 6, 9,14, 11, dC, "Intel Celeron G4900 (Coffee Lake B0)"); // no spec update; MRG* 2020-01-27 FMSQ( 0, 6, 9,14, 11, dP, "Intel Pentium Gold G5000 (Coffee Lake B0)"); // MRG* 2020-01-27 pinned down stepping FMSQ( 0, 6, 9,14, 12, dc, "Intel Core i*-9000 S Line (Coffee Lake P0)"); FMSQ( 0, 6, 9,14, 13, d1, "Intel CC150 (Coffee Lake R0)"); // no docs; only instlatx64 example FMSQ( 0, 6, 9,14, 13, dc, "Intel Core i*-9000 H Line (Coffee Lake R0)"); FMSQ( 0, 6, 9,14, 13, sX, "Intel Xeon E-2200 (Coffee Lake R0)"); // no docs on stepping; only MRG 2019-11-13 FM ( 0, 6, 9,14, "Intel (unknown type) (Kaby Lake / Coffee Lake)"); FM ( 0, 6, 9,15, "Intel (unknown type) (Ice Lake)"); // undocumented, but (engr?) sample via instlatx64 from Komachi_ENSAKA // LX*. Coreboot* provides more detail & steppings // (615213) mentions the (0,6),(10,5),2 and (0,6),(10,5),5 steppings, but // does not provide their names. // en.wikichip.org provides more details on stepping names. FMSQ( 0, 6, 10, 5, 0, dC, "Intel Celeron 5000 (Comet Lake-H/S G0)"); FMSQ( 0, 6, 10, 5, 0, dP, "Intel Pentium Gold G6400 / G6500 (Comet Lake-H/S G0)"); FMSQ( 0, 6, 10, 5, 0, dc, "Intel Core i*-10000 (Comet Lake-H/S G0)"); FMSQ( 0, 6, 10, 5, 0, sX, "Intel Xeon W-1200 (Comet Lake-H/S G0)"); FMS ( 0, 6, 10, 5, 0, "Intel (unknown type) (Comet Lake-H/S G0)"); FMSQ( 0, 6, 10, 5, 1, dC, "Intel Celeron 5000 (Comet Lake-H/S P0)"); FMSQ( 0, 6, 10, 5, 1, dP, "Intel Pentium Gold G6400 / G6500 (Comet Lake-H/S P0)"); FMSQ( 0, 6, 10, 5, 1, dc, "Intel Core i*-10000 (Comet Lake-H/S P0)"); FMSQ( 0, 6, 10, 5, 1, sX, "Intel Xeon W-1200 (Comet Lake-H/S P0)"); FMS ( 0, 6, 10, 5, 1, "Intel (unknown type) (Comet Lake-H/S P0)"); FMSQ( 0, 6, 10, 5, 2, dC, "Intel Celeron 5000 (Comet Lake-H/S R1)"); FMSQ( 0, 6, 10, 5, 2, dP, "Intel Pentium Gold G6400 / G6500 (Comet Lake-H/S R1)"); FMSQ( 0, 6, 10, 5, 2, dc, "Intel Core i*-10000 (Comet Lake-H/S R1)"); FMSQ( 0, 6, 10, 5, 2, sX, "Intel Xeon W-1200 (Comet Lake-H/S R1)"); FMS ( 0, 6, 10, 5, 2, "Intel (unknown type) (Comet Lake-H/S R1)"); FMSQ( 0, 6, 10, 5, 3, dC, "Intel Celeron 5000 (Comet Lake-H/S G1)"); FMSQ( 0, 6, 10, 5, 3, dP, "Intel Pentium Gold G6400 / G6500 (Comet Lake-H/S G1)"); FMSQ( 0, 6, 10, 5, 3, dc, "Intel Core i*-10000 (Comet Lake-H/S G1)"); FMSQ( 0, 6, 10, 5, 3, sX, "Intel Xeon W-1200 (Comet Lake-H/S G1)"); FMS ( 0, 6, 10, 5, 3, "Intel (unknown type) (Comet Lake-H/S G1)"); FMSQ( 0, 6, 10, 5, 4, dC, "Intel Celeron 5000 (Comet Lake-H/S P1)"); FMSQ( 0, 6, 10, 5, 4, dP, "Intel Pentium Gold G6400 / G6500 (Comet Lake-H/S P1)"); FMSQ( 0, 6, 10, 5, 4, dc, "Intel Core i*-10000 (Comet Lake-H/S P1)"); FMSQ( 0, 6, 10, 5, 4, sX, "Intel Xeon W-1200 (Comet Lake-H/S P1)"); FMS ( 0, 6, 10, 5, 4, "Intel (unknown type) (Comet Lake-H/S P1)"); FMSQ( 0, 6, 10, 5, 5, dC, "Intel Celeron 5000 (Comet Lake-H/S Q0)"); FMSQ( 0, 6, 10, 5, 5, dP, "Intel Pentium Gold G6400 / G6500 (Comet Lake-H/S Q0)"); FMSQ( 0, 6, 10, 5, 5, dc, "Intel Core i*-10000 (Comet Lake-H/S Q0)"); FMSQ( 0, 6, 10, 5, 5, sX, "Intel Xeon W-1200 (Comet Lake-H/S Q0)"); FMS ( 0, 6, 10, 5, 5, "Intel (unknown type) (Comet Lake-H/S Q0)"); FMQ ( 0, 6, 10, 5, dC, "Intel Celeron 5000 (Comet Lake-H/S)"); FMQ ( 0, 6, 10, 5, dP, "Intel Pentium Gold G6400 / G6500 (Comet Lake-H/S)"); FMQ ( 0, 6, 10, 5, dc, "Intel Core i*-10000 (Comet Lake-H/S)"); FMQ ( 0, 6, 10, 5, sX, "Intel Xeon W-1200 (Comet Lake-H/S)"); FM ( 0, 6, 10, 5, "Intel (unknown type) (Comet Lake-H/S)"); // (615213) provides steppings. // MRG* 2019-11-13 & instlatx64 example // Coreboot* provides steppings. // ILPMDF* confirms steppings A0 & K1. FMS ( 0, 6, 10, 6, 0, "Intel Core i*-10000 (Comet Lake-U A0)"); FMS ( 0, 6, 10, 6, 1, "Intel Core i*-10000 (Comet Lake-U K0/K1/S0)"); FMS ( 0, 6, 10, 6, 2, "Intel Core i*-10000 (Comet Lake-H R1)"); FMS ( 0, 6, 10, 6, 3, "Intel Core i*-10000 (Comet Lake-S G1)"); FMS ( 0, 6, 10, 6, 5, "Intel Core i*-10000 (Comet Lake-S Q0)"); FM ( 0, 6, 10, 6, "Intel Core i*-10000 (Comet Lake)"); // Intel docs (709192). // Stepping 1 is the only stepping, and Errata Summary Table says B0. FMSQ( 0, 6, 10, 7, 1, dc, "Intel Core i*-11000 (Rocket Lake B0)"); FMSQ( 0, 6, 10, 7, 1, sX, "Intel Xeon E-1300 / E-2300G (Rocket Lake B0)"); FMS ( 0, 6, 10, 7, 1, "Intel (unknown type) (Rocket Lake B0)"); FMQ ( 0, 6, 10, 7, dc, "Intel Core i*-11000 (Rocket Lake)"); FMQ ( 0, 6, 10, 7, sX, "Intel Xeon E-1300 / E-2300G (Rocket Lake)"); FM ( 0, 6, 10, 7, "Intel (unknown type) (Rocket Lake)"); FM ( 0, 6, 10, 8, "Intel (unknown type) (Rocket Lake)"); // MSR_CPUID_table* FMS ( 0, 6, 10,10, 0, "Intel (unknown type) (Meteor Lake-M A0)"); // DPTF*; undocumented, but (engr?) sample via instlatx64 from Komachi_ENSAKA; Coreboot* provides steppings. FMS ( 0, 6, 10,10, 1, "Intel (unknown type) (Meteor Lake-M A0)"); // DPTF*; undocumented, but (engr?) sample via instlatx64 from Komachi_ENSAKA; Coreboot* provides steppings. FMS ( 0, 6, 10,10, 2, "Intel (unknown type) (Meteor Lake-M B0)"); // DPTF*; Coreboot* provides steppings FMSQ( 0, 6, 10,10, 4, dU, "Intel (Core Ultra 1xxH) (Meteor Lake-M C0)"); // 792044 Core Ultra (100) datasheet FMS ( 0, 6, 10,10, 4, "Intel (unknown type) (Meteor Lake-M C0)"); // DPTF*; ILPMDF* 20240312 & Coreboot* provide steppings FMQ ( 0, 6, 10,10, dU, "Intel (Core Ultra 1xxH) (Meteor Lake-M)"); // instlatx64* sample FM ( 0, 6, 10,10, "Intel (unknown type) (Meteor Lake-M)"); // MSR_CPUID_table*; DPTF*, LX* (but -L); (engr?) sample via instlatx64 from Komachi_ENSAKA FM ( 0, 6, 10,11, "Intel (unknown type) (Meteor Lake-N)"); // DPTF* FM ( 0, 6, 10,12, "Intel (unknown type) (Meteor Lake-S)"); // MSR_CPUID_table*; LX*; (engr?) sample via instlatx64 from Komachi_ENSAKA FM ( 0, 6, 10,13, "Intel (unknown type) (Granite Rapids)"); // MSR_CPUID_table*; (engr?) sample via instlatx64 from Komachi_ENSAKA FM ( 0, 6, 10,14, "Intel (unknown type) (Granite Rapids)"); // MSR_CPUID_table* FMSQ( 0, 6, 10,15, 3, sX, "Intel Xeon 6 6700E-Series (Sierra Forest C0)"); // stepping from ILPMDF* 2025-02-11 FMS ( 0, 6, 10,15, 3, "Intel (unknown type) (Sierra Forest C0)"); // stepping from ILPMDF* 2025-02-11 FMQ ( 0, 6, 10,15, sX, "Intel Xeon 6 (Sierra Forest)"); // MSR_CPUID_table*; sample from CCRT FM ( 0, 6, 10,15, "Intel (unknown type) (Sierra Forest)"); // MSR_CPUID_table*; sample from CCRT & (engr?) sample via instlatx64 from Komachi_ENSAKA // Intel doc 834774 FMSQ( 0, 6, 11, 5, 0, dU, "Intel Core Ultra 2xxS (Arrow Lake-U A1)"); FMS ( 0, 6, 11, 5, 0, "Intel (unknown type) (Arrow Lake-U A1)"); FMQ ( 0, 6, 11, 5, dU, "Intel Core Ultra 2xxS (Arrow Lake-U)"); FM ( 0, 6, 11, 5, "Intel (unknown type) (Arrow Lake-U)"); // Grand Ridge: Atom P6900 name from: // https://www.intel.com/content/www/us/en/security-center/advisory/intel-sa-01194.html // SSG* mentions stepping 4, but with no name: FM ( 0, 6, 11, 6, "Intel Atom P6900 (Grand Ridge)"); // MSR_CPUID_table* // Intel doc 740518 provides steppings 1 & 2, but without names // Intel doc 743844 provides steppings 1 & 2, with names! FMSQ( 0, 6, 11, 7, 0, Ha, "Intel Core i*-13000 / i*-14000 E-core (Raptor Lake-S/HX A0)"); // Coreboot* FMSQ( 0, 6, 11, 7, 0, Hc, "Intel Core i*-13000 / i*-14000 P-core (Raptor Lake-S/HX A0)"); // Coreboot* FMSQ( 0, 6, 11, 7, 0, dc, "Intel Core i*-13000 / i*-14000 (Raptor Lake-S/HX A0)"); // Coreboot* FMS ( 0, 6, 11, 7, 0, "Intel (unknown type) (Raptor Lake-S/HX A0)"); // Coreboot* FMSQ( 0, 6, 10, 7, 1, sX, "Intel Xeon E-2400 / 6300 (Raptor Lake-E B0)"); FMSQ( 0, 6, 11, 7, 1, Ha, "Intel Core i*-13000 / i*-14000 E-core (Raptor Lake-S/HX B0)"); FMSQ( 0, 6, 11, 7, 1, Hc, "Intel Core i*-13000 / i*-14000 P-core (Raptor Lake-S/HX B0)"); FMSQ( 0, 6, 11, 7, 1, dc, "Intel Core i*-13000 / i*-14000 (Raptor Lake-S/HX B0)"); FMS ( 0, 6, 11, 7, 1, "Intel (unknown type) (Raptor Lake-S/HX B0)"); FMQ ( 0, 6, 10, 7, sX, "Intel Xeon E-2400 / 6300 (Raptor Lake-E)"); FMQ ( 0, 6, 11, 7, Ha, "Intel Core i*-13000 / i*-14000 E-core (Raptor Lake-S/HX)"); FMQ ( 0, 6, 11, 7, Hc, "Intel Core i*-13000 / i*-14000 P-core (Raptor Lake-S/HX)"); FMQ ( 0, 6, 11, 7, dc, "Intel Core i*-13000 / i*-14000 (Raptor Lake-S/HX)"); FM ( 0, 6, 11, 7, "Intel (unknown type) (Raptor Lake-S/HX)"); // Intel doc 740518 provides steppings 2 & 3, but without names // Intel doc 743844 provides steppings 2 & 3, with names! // ILPMDF* 20230214 contradicts it, saying 2=Q0, but it's prone to cut&paste // errors, so adhering to the official docs. FMSQ( 0, 6, 11,10, 2, Ha, "Intel Core i*-13000 E-core (Raptor Lake-H/U/P J0)"); FMSQ( 0, 6, 11,10, 2, Hc, "Intel Core i*-13000 P-core (Raptor Lake-H/U/P J0)"); FMSQ( 0, 6, 11,10, 2, dc, "Intel Core i*-13000 (Raptor Lake-H/U/P J0)"); FMS ( 0, 6, 11,10, 2, "Intel (unknown type) (Raptor Lake-H/U/P J0)"); FMSQ( 0, 6, 11,10, 3, Ha, "Intel Core i*-13000 E-core (Raptor Lake-P Q0)"); FMSQ( 0, 6, 11,10, 3, Hc, "Intel Core i*-13000 P-core (Raptor Lake-P Q0)"); FMSQ( 0, 6, 11,10, 3, dc, "Intel Core i*-13000 (Raptor Lake-P Q0)"); FMS ( 0, 6, 11,10, 3, "Intel (unknown type) (Raptor Lake-P Q0)"); FM ( 0, 6, 11,10, "Intel (unknown type) (Raptor Lake-P)"); FM ( 0, 6, 11,12, "Intel (unknown type) (Lunar Lake)"); // Intel SDE 9.24.0 misc/cpuid/lnl/cpuid.def // Intel doc 829568 FMSQ( 0, 6, 11,13, 0, dU, "Intel Core Ultra 2xxV (Lunar Lake A0)"); FMS ( 0, 6, 11,13, 0, "Intel (unknown type) (Lunar Lake A0)"); FMSQ( 0, 6, 11,13, 1, dU, "Intel Core Ultra 2xxV (Lunar Lake B0)"); FMS ( 0, 6, 11,13, 1, "Intel (unknown type) (Lunar Lake B0)"); FMQ ( 0, 6, 11,13, dU, "Intel Core Ultra 2xxV (Lunar Lake)"); FM ( 0, 6, 11,13, "Intel (unknown type) (Lunar Lake)"); // Intel doc 764616 // ILPMDF* 20231114 claims this covers stepping N0 as well as A0. // ILPMDF* 20240910 claims that this now also covers Twin Lake N0. // Is Twin Lake (Intel N250) distinguishable from // Alder Lake-N (Intel N50-N200) only via branding? // Does it also apply to any i3-N300 & Atom x7000E CPUs? FMSQ( 0, 6, 11,14, 0, da, "Intel Atom x7000E (Alder Lake-N A0/N0)"); // ILPMDF* 20230512 FMSQ( 0, 6, 11,14, 0, Ia, "Intel Core i*-N300 N-Series E-core (Alder Lake-N A0/N0)"); FMSQ( 0, 6, 11,14, 0, Ic, "Intel Core i*-N300 N-Series P-core (Alder Lake-N A0/N0)"); // possibly no P-cores ever for this model FMSQ( 0, 6, 11,14, 0, Ha, "Intel N-Series E-core (Alder Lake-N A0/N0 / Twin Lake N0)"); FMSQ( 0, 6, 11,14, 0, Hc, "Intel N-Series P-core (Alder Lake-N A0/N0 / Twin Lake N0)"); // possibly no P-cores ever for these model FMS ( 0, 6, 11,14, 0, "Intel N-Series / Atom x7000E (Alder Lake-N A0/N0 / Twin Lake N0)"); FMQ ( 0, 6, 11,14, da, "Intel Atom x7000E (Alder Lake-N)"); // ILPMDF* 20230512 FMQ ( 0, 6, 11,14, Ia, "Intel Core i*-N300 N-Series E-core (Alder Lake-N)"); FMQ ( 0, 6, 11,14, Ic, "Intel Core i*-N300 N-Series P-core (Alder Lake-N)"); // possibly no P-cores ever for this model FMQ ( 0, 6, 11,14, Ha, "Intel N-Series E-core (Alder Lake-N / Twin Lake)"); FMQ ( 0, 6, 11,14, Hc, "Intel N-Series P-core (Alder Lake-N / Twin Lake)"); // possibly no P-cores ever for this model FM ( 0, 6, 11,14, "Intel N-Series / Atom x7000E (Alder Lake-N / Twin Lake)"); // Intel doc 740518 provides steppings 2 & 5, but without names // Intel doc 743844 provides steppings 2 & 5, with names: C0 & H0. // ILPMDF* 20231114 confirms steppings C0 & H0. FMSQ( 0, 6, 11,15, 2, Ha, "Intel Core i*-13000 E-core (Raptor Lake-S/HX C0)"); FMSQ( 0, 6, 11,15, 2, Hc, "Intel Core i*-13000 P-core (Raptor Lake-S/HX C0)"); FMSQ( 0, 6, 11,15, 2, dc, "Intel Core i*-13000 (Raptor Lake-S/HX C0)"); FMS ( 0, 6, 11,15, 2, "Intel (unknown type) (Raptor Lake-S/HX C0)"); FMSQ( 0, 6, 11,15, 5, Ha, "Intel Core i*-13000 E-core (Raptor Lake-S/HX/P H0)"); FMSQ( 0, 6, 11,15, 5, Hc, "Intel Core i*-13000 P-core (Raptor Lake-S/HX/P H0)"); FMSQ( 0, 6, 11,15, 5, dc, "Intel Core i*-13000 (Raptor Lake-S/HX/P H0)"); FMS ( 0, 6, 11,15, 5, "Intel (unknown type) (Raptor Lake-S/HX/P H0)"); FMQ ( 0, 6, 11,15, Ha, "Intel Core i*-13000 E-core (Raptor Lake-S/HX/P)"); FMQ ( 0, 6, 11,15, Hc, "Intel Core i*-13000 P-core (Raptor Lake-S/HX/P)"); FMQ ( 0, 6, 11,15, dc, "Intel Core i*-13000 (Raptor Lake-S/HX/P)"); FM ( 0, 6, 11,15, "Intel (unknown type) (Raptor Lake-S/HX/P)"); // Intel doc 834774 FMSQ( 0, 6, 12, 5, 2, dU, "Intel Core Ultra 2xxS (Arrow Lake-H A1)"); FMS ( 0, 6, 12, 5, 2, "Intel (unknown type) (Arrow Lake-H A1)"); FMQ ( 0, 6, 12, 5, dU, "Intel Core Ultra 2xxS (Arrow Lake-H)"); FM ( 0, 6, 12, 5, "Intel (unknown type) (Arrow Lake)"); // Intel doc 834774 FMSQ( 0, 6, 12, 6, 2, dU, "Intel Core Ultra 2xxS (Arrow Lake-S A0/B0)"); FMS ( 0, 6, 12, 6, 2, "Intel (unknown type) (Arrow Lake-S A0/B0)"); FMQ ( 0, 6, 12, 6, dU, "Intel Core Ultra 2xxS (Arrow Lake-S)"); FM ( 0, 6, 12, 6, "Intel (unknown type) (Arrow Lake-S)"); FM ( 0, 6, 12,12, "Intel (unknown type) (Panther Lake)"); // MSR_CPUID_table*, LX* // Intel docs (793902) provides stepping A1/R1. // ILPMDF* 20240312 provides stepping A0. FMSQ( 0, 6, 12,15, 1, sS, "Intel Xeon Scalable (5th Gen) Bronze/Silver/Gold/Platinum (Emerald Rapids A0)"); FMS ( 0, 6, 12,15, 1, "Intel Xeon (unknown type) (Emerald Rapids A0)"); FMSQ( 0, 6, 12,15, 2, sS, "Intel Xeon Scalable (5th Gen) Bronze/Silver/Gold/Platinum (Emerald Rapids A1/R1)"); FMS ( 0, 6, 12,15, 2, "Intel Xeon (unknown type) (Emerald Rapids A1/R1)"); FMQ ( 0, 6, 12,15, sS, "Intel Xeon Scalable (5th Gen) Bronze/Silver/Gold/Platinum (Emerald Rapids)"); FM ( 0, 6, 12,15, "Intel Xeon (unknown type) (Emerald Rapids)"); FM ( 0, 6, 13,13, "Intel (unknown type) (Clearwater Forest)"); // MSR_CPUID_table* FQ ( 0, 6, sX, "Intel Xeon (unknown model)"); FQ ( 0, 6, se, "Intel Xeon (unknown model)"); FQ ( 0, 6, MC, "Intel Mobile Celeron (unknown model)"); FQ ( 0, 6, dC, "Intel Celeron (unknown model)"); FQ ( 0, 6, Xc, "Intel Core Extreme (unknown model)"); FQ ( 0, 6, Mc, "Intel Mobile Core (unknown model)"); FQ ( 0, 6, dc, "Intel Core (unknown model)"); FQ ( 0, 6, MP, "Intel Mobile Pentium (unknown model)"); FQ ( 0, 6, dP, "Intel Pentium (unknown model)"); F ( 0, 6, "Intel (unknown model)"); // Intel docs (249720). FMS ( 0, 7, 0, 0, 6, "Intel Itanium (Merced C0)"); FMS ( 0, 7, 0, 0, 7, "Intel Itanium (Merced C1)"); FMS ( 0, 7, 0, 0, 8, "Intel Itanium (Merced C2)"); F ( 0, 7, "Intel Itanium (unknown model)"); FM ( 0,11, 0, 0, "Intel Xeon Phi x100 Coprocessor (Knights Ferry)"); // found only on en.wikichip.org // Intel docs (328205). FMS ( 0,11, 0, 1, 1, "Intel Xeon Phi x100 Coprocessor (Knights Corner B0)"); FMS ( 0,11, 0, 1, 3, "Intel Xeon Phi x100 Coprocessor (Knights Corner B1)"); FMS ( 0,11, 0, 1, 4, "Intel Xeon Phi x100 Coprocessor (Knights Corner C0)"); FM ( 0,11, 0, 1, "Intel Xeon Phi x100 Coprocessor (Knights Corner)"); // Intel docs (249199, 249678). FMS ( 0,15, 0, 0, 7, "Intel Pentium 4 (Willamette B2)"); FMSQ( 0,15, 0, 0, 10, dP, "Intel Pentium 4 (Willamette C1)"); FMSQ( 0,15, 0, 0, 10, sX, "Intel Xeon (Foster C1)"); FMS ( 0,15, 0, 0, 10, "Intel Pentium 4 (unknown type) 4 (Willamette/Foster C1)"); FMQ ( 0,15, 0, 0, dP, "Intel Pentium 4 (Willamette)"); FMQ ( 0,15, 0, 0, sX, "Intel Xeon (Foster)"); FM ( 0,15, 0, 0, "Intel Pentium 4 (unknown type) (Willamette/Foster)"); // Intel docs (249199, 249678, 290741, 290749). FMS ( 0,15, 0, 1, 1, "Intel Xeon MP (Foster C0)"); FMSQ( 0,15, 0, 1, 2, dP, "Intel Pentium 4 (Willamette D0)"); FMSQ( 0,15, 0, 1, 2, sX, "Intel Xeon (Foster D0)"); FMS ( 0,15, 0, 1, 2, "Intel Pentium 4 (unknown type) (Willamette/Foster D0)"); FMSQ( 0,15, 0, 1, 3, dP, "Intel Pentium 4(Willamette E0)"); FMSQ( 0,15, 0, 1, 3, dC, "Intel Celeron 478-pin (Willamette E0)"); FMS ( 0,15, 0, 1, 3, "Intel Pentium 4 (unknown type) (Willamette/Foster E0)"); FMQ ( 0,15, 0, 1, dP, "Intel Pentium 4 (Willamette)"); FMQ ( 0,15, 0, 1, sX, "Intel Xeon (Foster)"); FM ( 0,15, 0, 1, "Intel Pentium 4 (unknown type) (Willamette/Foster)"); // Intel docs (249199, 249678, 250721, 251309, 253176, 290741, 290749). FMS ( 0,15, 0, 2, 2, "Intel Xeon MP (Gallatin A0)"); FMSQ( 0,15, 0, 2, 4, sX, "Intel Xeon (Prestonia B0)"); FMSQ( 0,15, 0, 2, 4, MM, "Intel Mobile Pentium 4 Processor-M (Northwood B0)"); FMSQ( 0,15, 0, 2, 4, MC, "Intel Mobile Celeron (Northwood B0)"); FMSQ( 0,15, 0, 2, 4, dP, "Intel Pentium 4 (Northwood B0)"); FMS ( 0,15, 0, 2, 4, "Intel Pentium 4 (unknown type) (Northwood/Prestonia B0)"); FMSQ( 0,15, 0, 2, 5, dP, "Intel Pentium 4 (Northwood B1/M0)"); FMSQ( 0,15, 0, 2, 5, sM, "Intel Xeon MP (Gallatin B1)"); FMSQ( 0,15, 0, 2, 5, sX, "Intel Xeon (Prestonia B1)"); FMS ( 0,15, 0, 2, 5, "Intel Pentium 4 (unknown type) (Northwood/Prestonia/Gallatin B1/M0)"); FMS ( 0,15, 0, 2, 6, "Intel Xeon MP (Gallatin C0)"); FMSQ( 0,15, 0, 2, 7, sX, "Intel Xeon (Prestonia C1)"); FMSQ( 0,15, 0, 2, 7, dC, "Intel Celeron 478-pin (Northwood C1)"); FMSQ( 0,15, 0, 2, 7, MC, "Intel Mobile Celeron (Northwood C1)"); FMSQ( 0,15, 0, 2, 7, MM, "Intel Mobile Pentium 4 Processor-M (Northwood C1)"); FMSQ( 0,15, 0, 2, 7, dP, "Intel Pentium 4 (Northwood C1)"); FMS ( 0,15, 0, 2, 7, "Intel Pentium 4 (unknown type) (Northwood/Prestonia C1)"); FMSQ( 0,15, 0, 2, 9, sX, "Intel Xeon (Prestonia D1)"); FMSQ( 0,15, 0, 2, 9, dC, "Intel Celeron 478-pin (Northwood D1)"); FMSQ( 0,15, 0, 2, 9, MC, "Intel Mobile Celeron (Northwood D1)"); FMSQ( 0,15, 0, 2, 9, MM, "Intel Mobile Pentium 4 Processor-M (Northwood D1)"); FMSQ( 0,15, 0, 2, 9, MP, "Intel Mobile Pentium 4 (Northwood D1)"); FMSQ( 0,15, 0, 2, 9, dP, "Intel Pentium 4 (Northwood D1)"); FMS ( 0,15, 0, 2, 9, "Intel Pentium 4 (unknown type) (Northwood/Prestonia D1)"); FMQ ( 0,15, 0, 2, dP, "Intel Pentium 4 (Northwood)"); FMQ ( 0,15, 0, 2, sM, "Intel Xeon MP (Gallatin)"); FMQ ( 0,15, 0, 2, sX, "Intel Xeon (Prestonia)"); FM ( 0,15, 0, 2, "Intel Pentium 4 (unknown type) (Northwood/Prestonia/Gallatin)"); // Intel docs (302352, 302402, 302403, 302441). FMSQ( 0,15, 0, 3, 3, dP, "Intel Pentium 4 (Prescott C0)"); FMSQ( 0,15, 0, 3, 3, dC, "Intel Celeron D (Prescott C0)"); FMS ( 0,15, 0, 3, 3, "Intel Pentium 4 (unknown type) (Prescott C0)"); FMSQ( 0,15, 0, 3, 4, sX, "Intel Xeon (Nocona D0)"); FMSQ( 0,15, 0, 3, 4, dC, "Intel Celeron D (Prescott D0)"); FMSQ( 0,15, 0, 3, 4, MP, "Intel Mobile Pentium 4 (Prescott D0)"); FMSQ( 0,15, 0, 3, 4, dP, "Intel Pentium 4 (Prescott D0)"); FMS ( 0,15, 0, 3, 4, "Intel Pentium 4 (unknown type) (Prescott/Nocona D0)"); FMQ ( 0,15, 0, 3, sX, "Intel Xeon (Nocona)"); FMQ( 0,15, 0, 3, dC, "Intel Celeron D (Prescott)"); FMQ ( 0,15, 0, 3, MP, "Intel Mobile Pentium 4 (Prescott)"); FMQ ( 0,15, 0, 3, dP, "Intel Pentium 4 (Prescott)"); FM ( 0,15, 0, 3, "Intel Pentium 4 (unknown type) (Prescott/Nocona)"); // Intel docs (302354, 306752, 306757, 306832, 309159, 309627). FMSQ( 0,15, 0, 4, 1, sP, "Intel Xeon MP (Potomac C0)"); FMSQ( 0,15, 0, 4, 1, sM, "Intel Xeon MP (Cranford A0)"); FMSQ( 0,15, 0, 4, 1, sX, "Intel Xeon (Nocona E0)"); FMSQ( 0,15, 0, 4, 1, dC, "Intel Celeron D (Prescott E0)"); FMSQ( 0,15, 0, 4, 1, MP, "Intel Mobile Pentium 4 (Prescott E0)"); FMSQ( 0,15, 0, 4, 1, dP, "Intel Pentium 4 (Prescott E0)"); FMS ( 0,15, 0, 4, 1, "Intel Pentium 4 (unknown type) (Prescott/Nocona/Cranford/Potomac E0)"); FMSQ( 0,15, 0, 4, 3, sI, "Intel Xeon (Irwindale N0)"); FMSQ( 0,15, 0, 4, 3, sX, "Intel Xeon (Nocona N0)"); FMSQ( 0,15, 0, 4, 3, dP, "Intel Pentium 4 (Prescott N0)"); FMS ( 0,15, 0, 4, 3, "Intel Pentium 4 (unknown type) (Prescott/Nocona/Irwindale N0)"); FMSQ( 0,15, 0, 4, 4, dd, "Intel Pentium D Processor 8x0 (Smithfield A0)"); FMSQ( 0,15, 0, 4, 4, dG, "Intel Pentium Extreme Edition Processor 840 (Smithfield A0)"); FMS ( 0,15, 0, 4, 4, "Intel Pentium D (unknown type) (Smithfield A0)"); FMSQ( 0,15, 0, 4, 7, dd, "Intel Pentium D Processor 8x0 (Smithfield B0)"); FMSQ( 0,15, 0, 4, 7, dG, "Pentium Extreme Edition Processor 840 (Smithfield B0)"); FMS ( 0,15, 0, 4, 7, "Intel Pentium D (unknown type) (Smithfield B0)"); FMSQ( 0,15, 0, 4, 8, s7, "Intel Dual-Core Xeon Processor 7000 (Paxville A0)"); FMSQ( 0,15, 0, 4, 8, sX, "Intel Dual-Core Xeon (Paxville A0)"); FMS ( 0,15, 0, 4, 8, "Intel Dual-Core Xeon (unknown type) (Paxville A0)"); FMSQ( 0,15, 0, 4, 9, sM, "Intel Xeon MP (Cranford B0)"); FMSQ( 0,15, 0, 4, 9, dC, "Intel Celeron D (Prescott G1)"); FMSQ( 0,15, 0, 4, 9, dP, "Intel Pentium 4 (Prescott G1)"); FMS ( 0,15, 0, 4, 9, "Intel Pentium 4 (unknown type) (Prescott/Cranford G1)"); FMSQ( 0,15, 0, 4, 10, sI, "Intel Xeon (Irwindale R0)"); FMSQ( 0,15, 0, 4, 10, sX, "Intel Xeon (Nocona R0)"); FMSQ( 0,15, 0, 4, 10, dP, "Intel Pentium 4 (Prescott R0)"); FMS ( 0,15, 0, 4, 10, "Intel Pentium 4 (unknown type) (Prescott/Nocona/Irwindale R0)"); FMQ ( 0,15, 0, 4, sM, "Intel Xeon MP (Nocona/Potomac)"); FMQ ( 0,15, 0, 4, sX, "Intel Xeon (Nocona/Irwindale)"); FMQ ( 0,15, 0, 4, dC, "Intel Celeron D (Prescott)"); FMQ ( 0,15, 0, 4, MP, "Intel Mobile Pentium 4 (Prescott)"); FMQ ( 0,15, 0, 4, dd, "Intel Pentium D (Smithfield A0)"); FMQ ( 0,15, 0, 4, dP, "Intel Pentium 4 (Prescott) / Pentium Extreme Edition (Smithfield A0)"); FM ( 0,15, 0, 4, "Intel Pentium 4 (unknown type) (Prescott/Nocona/Irwindale/Smithfield/Cranford/Potomac)"); // Intel docs (310307, 310309, 311827, 313065, 314554). FMSQ( 0,15, 0, 6, 2, dd, "Intel Pentium D Processor 9xx (Presler B1)"); FMSQ( 0,15, 0, 6, 2, dP, "Intel Pentium 4 Processor 6x1 (Cedar Mill B1) / Pentium Extreme Edition Processor 955 (Presler B1)"); FMS ( 0,15, 0, 6, 2, "Intel Pentium 4 (unknown type) (Cedar Mill/Presler B1)"); FMSQ( 0,15, 0, 6, 4, dd, "Intel Pentium D Processor 9xx (Presler C1)"); FMSQ( 0,15, 0, 6, 4, dP, "Intel Pentium 4 Processor 6x1 (Cedar Mill C1) / Pentium Extreme Edition Processor 955 (Presler C1)"); FMSQ( 0,15, 0, 6, 4, dC, "Intel Celeron D Processor 34x/35x (Cedar Mill C1)"); FMSQ( 0,15, 0, 6, 4, sX, "Intel Xeon Processor 5000 (Dempsey C1)"); FMS ( 0,15, 0, 6, 4, "Intel Pentium 4 (unknown type) (Cedar Mill/Presler/Dempsey C1)"); FMSQ( 0,15, 0, 6, 5, dC, "Intel Celeron D Processor 36x (Cedar Mill D0)"); FMSQ( 0,15, 0, 6, 5, dd, "Intel Pentium D Processor 9xx (Presler D0)"); FMSQ( 0,15, 0, 6, 5, dP, "Intel Pentium 4 Processor 6x1 (Cedar Mill D0) / Pentium Extreme Edition Processor 955 (Presler D0)"); FMS ( 0,15, 0, 6, 5, "Intel Pentium 4 (unknown type) (Cedar Mill/Presler D0)"); FMS ( 0,15, 0, 6, 8, "Intel Xeon Processor 71x0 (Tulsa B0)"); FMQ ( 0,15, 0, 6, dd, "Intel Pentium D (Presler)"); FMQ ( 0,15, 0, 6, dP, "Intel Pentium 4 (Cedar Mill) / Pentium Extreme Edition (Presler)"); FMQ ( 0,15, 0, 6, dC, "Intel Celeron D (Cedar Mill)"); FMQ ( 0,15, 0, 6, sX, "Intel Xeon (Dempsey / Tulsa)"); FM ( 0,15, 0, 6, "Intel Pentium 4 (unknown type) (Cedar Mill/Presler/Dempsey/Tulsa)"); FQ ( 0,15, sM, "Intel Xeon MP (unknown model)"); FQ ( 0,15, sX, "Intel Xeon (unknown model)"); FQ ( 0,15, MC, "Intel Mobile Celeron (unknown model)"); FQ ( 0,15, MC, "Intel Mobile Pentium 4 (unknown model)"); FQ ( 0,15, MM, "Intel Mobile Pentium 4 Processor-M (unknown model)"); FQ ( 0,15, dC, "Intel Celeron (unknown model)"); FQ ( 0,15, dd, "Intel Pentium D (unknown model)"); FQ ( 0,15, dP, "Intel Pentium 4 (unknown model)"); FQ ( 0,15, dc, "Intel Pentium (unknown model)"); F ( 0,15, "Intel Pentium 4 / Pentium D / Xeon / Xeon MP / Celeron / Celeron D (unknown model)"); // NOTE: Intel spec updates describe CPUID in Itanium Register 3 format: // AAFFMMSSNN // AA = archrev (not reported via CPUID instruction) // FF = family // MM = model // SS = revision/stepping // NN = number (not reported via CPUID instruction) // Intel docs (251141). FMS ( 1,15, 0, 0, 7, "Intel Itanium2 (McKinley B3)"); FM ( 1,15, 0, 0, "Intel Itanium2 (McKinley)"); // Intel docs (251141). FMS ( 1,15, 0, 1, 5, "Intel Itanium2 (Madison/Deerfield/Hondo B1)"); FM ( 1,15, 0, 1, "Intel Itanium2 (Madison/Deerfield/Hondo)"); // Intel docs (251141). FMS ( 1,15, 0, 2, 1, "Intel Itanium2 (Madison 9M/Fanwood A1)"); FMS ( 1,15, 0, 2, 2, "Intel Itanium2 (Madison 9M/Fanwood A2)"); FM ( 1,15, 0, 2, "Intel Itanium2 (Madison)"); F ( 1,15, "Intel Itanium2 (unknown model)"); // Intel docs (251141). FMS ( 2, 0, 0, 0, 5, "Intel Itanium2 Dual-Core Processor 9000 (Montecito/Millington C1), 90nm"); FMS ( 2, 0, 0, 0, 7, "Intel Itanium2 Dual-Core Processor 9000 (Montecito/Millington C2), 90nm"); FM ( 2, 0, 0, 0, "Intel Itanium2 Dual-Core Processor 9000 (Montecito/Millington), 90nm"); // Intel docs (251141). FMS ( 2, 0, 0, 1, 1, "Intel Itanium2 Dual-Core Processor 9100 (Montvale A1), 90nm"); FM ( 2, 0, 0, 1, "Intel Itanium2 Dual-Core Processor 9100 (Montvale), 90nm"); // Intel docs (323169). FMS ( 2, 0, 0, 2, 4, "Intel Itanium2 Processor 9300 (Tukwila E0), 65nm"); FM ( 2, 0, 0, 2, "Intel Itanium2 Processor 9300 (Tukwila), 65nm"); F ( 2, 0, "Intel Itanium2 (unknown model)"); // Intel docs (323169). FMS ( 2, 1, 0, 0, 4, "Intel Itanium2 Processor 9500 (Poulson D0), 32nm"); FMS ( 2, 1, 0, 0, 5, "Intel Itanium2 Processor 9700 (Kittson E0), 22nm"); FM ( 2, 1, 0, 0, "Intel Itanium2 (unknown model) (Poulson/Kittson)"); F ( 2, 1, "Intel Itanium2 (unknown model)"); FM ( 4,15, 0, 0, "Intel (unknown type) (Diamond Rapids)"); // MSR_CPUID_table* (-054, quickly retracted in -055), LX* FM ( 4,15, 0, 1, "Intel (unknown type) (Diamond Rapids)"); // MSR_CPUID_table*, LX* DEFAULT ("unknown"); return result; } #undef ACT #define ACT(str) (result = format_amd_stepping((str), val)) static cstring format_amd_stepping (ccstring format, unsigned int val) { if (Synth_Family(val) >= 8+15) { unsigned int model = BIT_EXTRACT_LE(val, 4, 8); char modelChar = 'A' + (model & 0x7); unsigned int stepping = BIT_EXTRACT_LE(val, 0, 4); static char buffer[1024]; sprintf(buffer, format, modelChar, stepping); return buffer; } else { return format; } } static cstring decode_synth_amd(unsigned int val, const code_stash_t* stash) { cstring result = NULL; START; FM ( 0, 4, 0, 3, "AMD 80486DX2"); FM ( 0, 4, 0, 7, "AMD 80486DX2WB"); FM ( 0, 4, 0, 8, "AMD 80486DX4"); FM ( 0, 4, 0, 9, "AMD 80486DX4WB"); FM ( 0, 4, 0,10, "AMD Elan SC400"); // sandpile.org FM ( 0, 4, 0,14, "AMD 5x86"); FM ( 0, 4, 0,15, "AMD 5xWB"); F ( 0, 4, "AMD 80486 / 5x (unknown model)"); FM ( 0, 5, 0, 0, "AMD SSA5 (PR75, PR90, PR100)"); FM ( 0, 5, 0, 1, "AMD 5k86 (PR120, PR133)"); FM ( 0, 5, 0, 2, "AMD 5k86 (PR166)"); FM ( 0, 5, 0, 3, "AMD 5k86 (PR200)"); FM ( 0, 5, 0, 5, "AMD Geode GX"); FM ( 0, 5, 0, 6, "AMD K6"); FM ( 0, 5, 0, 7, "AMD K6 (Little Foot)"); FMS ( 0, 5, 0, 8, 0, "AMD K6-2 (Chomper A)"); FMS ( 0, 5, 0, 8, 12, "AMD K6-2 (Chomper A)"); FM ( 0, 5, 0, 8, "AMD K6-2 (Chomper)"); FMS ( 0, 5, 0, 9, 1, "AMD K6-III (Sharptooth B)"); FM ( 0, 5, 0, 9, "AMD K6-III (Sharptooth)"); FM ( 0, 5, 0,10, "AMD Geode LX"); FM ( 0, 5, 0,13, "AMD K6-2+, K6-III+"); F ( 0, 5, "AMD 5k86 / K6 / Geode (unknown model)"); FM ( 0, 6, 0, 1, "AMD Athlon (Argon)"); FMS ( 0, 6, 0, 2, 2, "AMD Athlon (K75 / Pluto / Orion A2)"); FM ( 0, 6, 0, 2, "AMD Athlon (K75 / Pluto / Orion)"); FMS ( 0, 6, 0, 3, 0, "AMD Duron / mobile Duron (Spitfire A0)"); FMS ( 0, 6, 0, 3, 1, "AMD Duron / mobile Duron (Spitfire A2)"); FM ( 0, 6, 0, 3, "AMD Duron / mobile Duron (Spitfire)"); FMS ( 0, 6, 0, 4, 2, "AMD Athlon (Thunderbird A4-A7)"); FMS ( 0, 6, 0, 4, 4, "AMD Athlon (Thunderbird A9)"); FM ( 0, 6, 0, 4, "AMD Athlon (Thunderbird)"); FMSQ( 0, 6, 0, 6, 0, sA, "AMD Athlon MP (Palomino A0)"); FMSQ( 0, 6, 0, 6, 0, dA, "AMD Athlon (Palomino A0)"); FMSQ( 0, 6, 0, 6, 0, MA, "AMD mobile Athlon 4 (Palomino A0)"); FMSQ( 0, 6, 0, 6, 0, sD, "AMD Duron MP (Palomino A0)"); FMSQ( 0, 6, 0, 6, 0, MD, "AMD mobile Duron (Palomino A0)"); FMS ( 0, 6, 0, 6, 0, "AMD Athlon (unknown type) (Palomino A0)"); FMSQ( 0, 6, 0, 6, 1, sA, "AMD Athlon MP (Palomino A2)"); FMSQ( 0, 6, 0, 6, 1, dA, "AMD Athlon (Palomino A2)"); FMSQ( 0, 6, 0, 6, 1, MA, "AMD mobile Athlon 4 (Palomino A2)"); FMSQ( 0, 6, 0, 6, 1, sD, "AMD Duron MP (Palomino A2)"); FMSQ( 0, 6, 0, 6, 1, MD, "AMD mobile Duron (Palomino A2)"); FMSQ( 0, 6, 0, 6, 1, dD, "AMD Duron (Palomino A2)"); FMS ( 0, 6, 0, 6, 1, "AMD Athlon (unknown type) (Palomino A2)"); FMSQ( 0, 6, 0, 6, 2, sA, "AMD Athlon MP (Palomino A5)"); FMSQ( 0, 6, 0, 6, 2, dX, "AMD Athlon XP (Palomino A5)"); FMSQ( 0, 6, 0, 6, 2, MA, "AMD mobile Athlon 4 (Palomino A5)"); FMSQ( 0, 6, 0, 6, 2, sD, "AMD Duron MP (Palomino A5)"); FMSQ( 0, 6, 0, 6, 2, MD, "AMD mobile Duron (Palomino A5)"); FMSQ( 0, 6, 0, 6, 2, dD, "AMD Duron (Palomino A5)"); FMS ( 0, 6, 0, 6, 2, "AMD Athlon (unknown type) (Palomino A5)"); FMQ ( 0, 6, 0, 6, MD, "AMD mobile Duron (Palomino)"); FMQ ( 0, 6, 0, 6, dD, "AMD Duron (Palomino)"); FMQ ( 0, 6, 0, 6, MA, "AMD mobile Athlon (Palomino)"); FMQ ( 0, 6, 0, 6, dX, "AMD Athlon XP (Palomino)"); FMQ ( 0, 6, 0, 6, dA, "AMD Athlon (Palomino)"); FM ( 0, 6, 0, 6, "AMD Athlon (unknown type) (Palomino)"); FMSQ( 0, 6, 0, 7, 0, sD, "AMD Duron MP (Morgan A0)"); FMSQ( 0, 6, 0, 7, 0, MD, "AMD mobile Duron (Morgan A0)"); FMSQ( 0, 6, 0, 7, 0, dD, "AMD Duron (Morgan A0)"); FMS ( 0, 6, 0, 7, 0, "AMD Duron (unknown type) (Morgan A0)"); FMSQ( 0, 6, 0, 7, 1, sD, "AMD Duron MP (Morgan A1)"); FMSQ( 0, 6, 0, 7, 1, MD, "AMD mobile Duron (Morgan A1)"); FMSQ( 0, 6, 0, 7, 1, dD, "AMD Duron (Morgan A1)"); FMS ( 0, 6, 0, 7, 1, "AMD Duron (unknown type) (Morgan A1)"); FMQ ( 0, 6, 0, 7, sD, "AMD Duron MP (Morgan)"); FMQ ( 0, 6, 0, 7, MD, "AMD mobile Duron (Morgan)"); FMQ ( 0, 6, 0, 7, dD, "AMD Duron (Morgan)"); FM ( 0, 6, 0, 7, "AMD Duron (unknown type) (Morgan)"); FMSQ( 0, 6, 0, 8, 0, dS, "AMD Sempron (Thoroughbred A0)"); FMSQ( 0, 6, 0, 8, 0, sD, "AMD Duron MP (Applebred A0)"); FMSQ( 0, 6, 0, 8, 0, dD, "AMD Duron (Applebred A0)"); FMSQ( 0, 6, 0, 8, 0, MX, "AMD mobile Athlon XP (Thoroughbred A0)"); FMSQ( 0, 6, 0, 8, 0, sA, "AMD Athlon MP (Thoroughbred A0)"); FMSQ( 0, 6, 0, 8, 0, dX, "AMD Athlon XP (Thoroughbred A0)"); FMSQ( 0, 6, 0, 8, 0, dA, "AMD Athlon (Thoroughbred A0)"); FMS ( 0, 6, 0, 8, 0, "AMD Athlon (unknown type) (Thoroughbred A0)"); FMSQ( 0, 6, 0, 8, 1, MG, "AMD Geode NX (Thoroughbred B0)"); FMSQ( 0, 6, 0, 8, 1, dS, "AMD Sempron (Thoroughbred B0)"); FMSQ( 0, 6, 0, 8, 1, sD, "AMD Duron MP (Applebred B0)"); FMSQ( 0, 6, 0, 8, 1, dD, "AMD Duron (Applebred B0)"); FMSQ( 0, 6, 0, 8, 1, sA, "AMD Athlon MP (Thoroughbred B0)"); FMSQ( 0, 6, 0, 8, 1, dX, "AMD Athlon XP (Thoroughbred B0)"); FMSQ( 0, 6, 0, 8, 1, dA, "AMD Athlon (Thoroughbred B0)"); FMS ( 0, 6, 0, 8, 1, "AMD Athlon (unknown type) (Thoroughbred B0)"); FMQ ( 0, 6, 0, 8, MG, "AMD Geode NX (Thoroughbred)"); FMQ ( 0, 6, 0, 8, dS, "AMD Sempron (Thoroughbred)"); FMQ ( 0, 6, 0, 8, sD, "AMD Duron MP (Thoroughbred)"); FMQ ( 0, 6, 0, 8, dD, "AMD Duron (Thoroughbred)"); FMQ ( 0, 6, 0, 8, MX, "AMD mobile Athlon XP (Thoroughbred)"); FMQ ( 0, 6, 0, 8, sA, "AMD Athlon MP (Thoroughbred)"); FMQ ( 0, 6, 0, 8, dX, "AMD Athlon XP (Thoroughbred)"); FMQ ( 0, 6, 0, 8, dA, "AMD Athlon XP (Thoroughbred)"); FM ( 0, 6, 0, 8, "AMD Athlon (unknown type) (Thoroughbred)"); FMSQ( 0, 6, 0,10, 0, dS, "AMD Sempron (Barton A2)"); FMSQ( 0, 6, 0,10, 0, ML, "AMD mobile Athlon XP-M (LV) (Barton A2)"); FMSQ( 0, 6, 0,10, 0, MX, "AMD mobile Athlon XP-M (Barton A2)"); FMSQ( 0, 6, 0,10, 0, dt, "AMD Athlon XP (Thorton A2)"); FMSQ( 0, 6, 0,10, 0, sA, "AMD Athlon MP (Barton A2)"); FMSQ( 0, 6, 0,10, 0, dX, "AMD Athlon XP (Barton A2)"); FMS ( 0, 6, 0,10, 0, "AMD Athlon (unknown type) (Barton A2)"); FMQ ( 0, 6, 0,10, dS, "AMD Sempron (Barton)"); FMQ ( 0, 6, 0,10, ML, "AMD mobile Athlon XP-M (LV) (Barton)"); FMQ ( 0, 6, 0,10, MX, "AMD mobile Athlon XP-M (Barton)"); FMQ ( 0, 6, 0,10, sA, "AMD Athlon MP (Barton)"); FMQ ( 0, 6, 0,10, dX, "AMD Athlon XP (Barton)"); FM ( 0, 6, 0,10, "AMD Athlon (unknown type) (Barton)"); F ( 0, 6, "AMD Athlon (unknown model)"); F ( 0, 7, "AMD Opteron (unknown model)"); FMS ( 0,15, 0, 4, 0, "AMD Athlon 64 (SledgeHammer SH7-B0)"); FMSQ( 0,15, 0, 4, 8, MX, "AMD mobile Athlon XP-M (SledgeHammer SH7-C0)"); FMSQ( 0,15, 0, 4, 8, MA, "AMD mobile Athlon 64 (SledgeHammer SH7-C0)"); FMSQ( 0,15, 0, 4, 8, dA, "AMD Athlon 64 (SledgeHammer SH7-C0)"); FMS ( 0,15, 0, 4, 8, "AMD Athlon 64 (unknown type) (SledgeHammer SH7-C0)"); FMSQ( 0,15, 0, 4, 10, MX, "AMD mobile Athlon XP-M (SledgeHammer SH7-CG)"); FMSQ( 0,15, 0, 4, 10, MA, "AMD mobile Athlon 64 (SledgeHammer SH7-CG)"); FMSQ( 0,15, 0, 4, 10, dA, "AMD Athlon 64 (SledgeHammer SH7-CG)"); FMS ( 0,15, 0, 4, 10, "AMD Athlon 64 (unknown type) (SledgeHammer SH7-CG)"); FMQ ( 0,15, 0, 4, MX, "AMD mobile Athlon XP-M (SledgeHammer SH7)"); FMQ ( 0,15, 0, 4, MA, "AMD mobile Athlon 64 (SledgeHammer SH7)"); FMQ ( 0,15, 0, 4, dA, "AMD Athlon 64 (SledgeHammer SH7)"); FM ( 0,15, 0, 4, "AMD Athlon 64 (unknown type) (SledgeHammer SH7)"); FMS ( 0,15, 0, 5, 0, "AMD Opteron (DP SledgeHammer SH7-B0)"); FMS ( 0,15, 0, 5, 1, "AMD Opteron (DP SledgeHammer SH7-B3)"); FMSQ( 0,15, 0, 5, 8, sO, "AMD Opteron (DP SledgeHammer SH7-C0)"); FMSQ( 0,15, 0, 5, 8, dF, "AMD Athlon 64 FX (DP SledgeHammer SH7-C0)"); FMS ( 0,15, 0, 5, 8, "AMD Athlon 64 (unknown type) (DP SledgeHammer SH7-C0)"); FMSQ( 0,15, 0, 5, 10, sO, "AMD Opteron (DP SledgeHammer SH7-CG)"); FMSQ( 0,15, 0, 5, 10, dF, "AMD Athlon 64 FX (DP SledgeHammer SH7-CG)"); FMS ( 0,15, 0, 5, 10, "AMD Athlon 64 (unknown type) (DP SledgeHammer SH7-CG)"); FMQ ( 0,15, 0, 5, sO, "AMD Opteron (SledgeHammer SH7)"); FMQ ( 0,15, 0, 5, dF, "AMD Athlon 64 FX (SledgeHammer SH7)"); FM ( 0,15, 0, 5, "AMD Athlon 64 (unknown type) (SledgeHammer SH7) FX"); FMSQ( 0,15, 0, 7, 10, dF, "AMD Athlon 64 FX (DP SledgeHammer SH7-CG)"); FMSQ( 0,15, 0, 7, 10, dA, "AMD Athlon 64 (DP SledgeHammer SH7-CG)"); FMS ( 0,15, 0, 7, 10, "AMD Athlon 64 (unknown type) (DP SledgeHammer SH7-CG)"); FMQ ( 0,15, 0, 7, dF, "AMD Athlon 64 FX (DP SledgeHammer SH7)"); FMQ ( 0,15, 0, 7, dA, "AMD Athlon 64 (DP SledgeHammer SH7)"); FM ( 0,15, 0, 7, "AMD Athlon 64 (unknown type) (DP SledgeHammer SH7)"); FMSQ( 0,15, 0, 8, 2, MS, "AMD mobile Sempron (ClawHammer CH7-CG)"); FMSQ( 0,15, 0, 8, 2, MX, "AMD mobile Athlon XP-M (ClawHammer CH7-CG)"); FMSQ( 0,15, 0, 8, 2, MA, "AMD mobile Athlon 64 (Odessa CH7-CG)"); FMSQ( 0,15, 0, 8, 2, dA, "AMD Athlon 64 (ClawHammer CH7-CG)"); FMS ( 0,15, 0, 8, 2, "AMD Athlon 64 (unknown type) (ClawHammer/Odessa CH7-CG)"); FMQ ( 0,15, 0, 8, MS, "AMD mobile Sempron (Odessa CH7)"); FMQ ( 0,15, 0, 8, MX, "AMD mobile Athlon XP-M (Odessa CH7)"); FMQ ( 0,15, 0, 8, MA, "AMD mobile Athlon 64 (Odessa CH7)"); FMQ ( 0,15, 0, 8, dA, "AMD Athlon 64 (ClawHammer CH7)"); FM ( 0,15, 0, 8, "AMD Athlon 64 (unknown type) (ClawHammer/Odessa CH7)"); FMS ( 0,15, 0,11, 2, "AMD Athlon 64 (ClawHammer CH7-CG)"); FM ( 0,15, 0,11, "AMD Athlon 64 (ClawHammer CH7)"); FMSQ( 0,15, 0,12, 0, MS, "AMD mobile Sempron (Dublin DH7-CG)"); FMSQ( 0,15, 0,12, 0, dS, "AMD Sempron (Paris DH7-CG)"); FMSQ( 0,15, 0,12, 0, MX, "AMD mobile Athlon XP-M (ClawHammer/Odessa DH7-CG)"); FMSQ( 0,15, 0,12, 0, MA, "AMD mobile Athlon 64 (ClawHammer/Odessa DH7-CG)"); FMSQ( 0,15, 0,12, 0, dA, "AMD Athlon 64 (NewCastle DH7-CG)"); FMS ( 0,15, 0,12, 0, "AMD Athlon 64 (unknown type) (ClawHammer/Odessa/NewCastle/Paris/Dublin DH7-CG)"); FMQ ( 0,15, 0,12, MS, "AMD mobile Sempron (Dublin DH7)"); FMQ ( 0,15, 0,12, dS, "AMD Sempron (Paris DH7)"); FMQ ( 0,15, 0,12, MX, "AMD mobile Athlon XP-M (NewCastle DH7)"); FMQ ( 0,15, 0,12, MA, "AMD mobile Athlon 64 (ClawHammer/Odessa DH7)"); FMQ ( 0,15, 0,12, dA, "AMD Athlon 64 (NewCastle DH7)"); FM ( 0,15, 0,12, "AMD Athlon 64 (unknown type) (ClawHammer/Odessa/NewCastle/Paris/Dublin DH7)"); FMSQ( 0,15, 0,14, 0, MS, "AMD mobile Sempron (Dublin DH7-CG)"); FMSQ( 0,15, 0,14, 0, dS, "AMD Sempron (Paris DH7-CG)"); FMSQ( 0,15, 0,14, 0, MX, "AMD mobile Athlon XP-M (ClawHammer/Odessa DH7-CG)"); FMSQ( 0,15, 0,14, 0, MA, "AMD mobile Athlon 64 (ClawHammer/Odessa DH7-CG)"); FMSQ( 0,15, 0,14, 0, dA, "AMD Athlon 64 (NewCastle DH7-CG)"); FMS ( 0,15, 0,14, 0, "AMD Athlon 64 (unknown type) (ClawHammer/Odessa/NewCastle/Paris/Dublin DH7-CG)"); FMQ ( 0,15, 0,14, dS, "AMD Sempron (Paris DH7)"); FMQ ( 0,15, 0,14, MS, "AMD mobile Sempron (Dublin DH7)"); FMQ ( 0,15, 0,14, MX, "AMD mobile Athlon XP-M (ClawHammer/Odessa DH7)"); FMQ ( 0,15, 0,14, MA, "AMD mobile Athlon 64 (ClawHammer/Odessa DH7)"); FMQ ( 0,15, 0,14, dA, "AMD Athlon 64 (NewCastle DH7)"); FM ( 0,15, 0,14, "AMD Athlon 64 (unknown type) (ClawHammer/Odessa/NewCastle/Paris/Dublin DH7)"); FMSQ( 0,15, 0,15, 0, dS, "AMD Sempron (Paris DH7-CG)"); FMSQ( 0,15, 0,15, 0, MA, "AMD mobile Athlon 64 (ClawHammer/Odessa DH7-CG)"); FMSQ( 0,15, 0,15, 0, dA, "AMD Athlon 64 (NewCastle DH7-CG)"); FMS ( 0,15, 0,15, 0, "AMD Athlon 64 (unknown type) (ClawHammer/Odessa/NewCastle/Paris DH7-CG)"); FMQ ( 0,15, 0,15, dS, "AMD Sempron (Paris DH7)"); FMQ ( 0,15, 0,15, MA, "AMD mobile Athlon 64 (ClawHammer/Odessa DH7)"); FMQ ( 0,15, 0,15, dA, "AMD Athlon 64 (NewCastle DH7)"); FM ( 0,15, 0,15, "AMD Athlon 64 (unknown type) (ClawHammer/Odessa/NewCastle/Paris DH7)"); FMSQ( 0,15, 1, 4, 0, MX, "AMD mobile Athlon XP-M (Oakville SH7-D0)"); FMSQ( 0,15, 1, 4, 0, MA, "AMD mobile Athlon 64 (Oakville SH7-D0)"); FMSQ( 0,15, 1, 4, 0, dA, "AMD Athlon 64 (Winchester SH7-D0)"); FMS ( 0,15, 1, 4, 0, "AMD Athlon 64 (unknown type) (Winchester/Oakville SH7-D0)"); FMQ ( 0,15, 1, 4, MX, "AMD mobile Athlon XP-M (Oakville SH7)"); FMQ ( 0,15, 1, 4, MA, "AMD mobile Athlon 64 (Oakville SH7)"); FMQ ( 0,15, 1, 4, dA, "AMD Athlon 64 (Winchester SH7)"); FM ( 0,15, 1, 4, "AMD Athlon 64 (unknown type) (Winchester/Oakville SH7)"); FMSQ( 0,15, 1, 5, 0, sO, "AMD Opteron (Winchester SH7-D0)"); FMSQ( 0,15, 1, 5, 0, dF, "AMD Athlon 64 FX (Winchester SH7-D0)"); FMS ( 0,15, 1, 5, 0, "AMD Athlon 64 (unknown type) (Winchester SH7-D0)"); FMQ ( 0,15, 1, 5, sO, "AMD Opteron (Winchester SH7)"); FMQ ( 0,15, 1, 5, dF, "AMD Athlon 64 FX (Winchester SH7)"); FM ( 0,15, 1, 5, "AMD Athlon 64 (unknown type) (Winchester SH7)"); FMSQ( 0,15, 1, 7, 0, dF, "AMD Athlon 64 FX (Winchester SH7-D0)"); FMSQ( 0,15, 1, 7, 0, dA, "AMD Athlon 64 (Winchester SH7-D0)"); FMS ( 0,15, 1, 7, 0, "AMD Athlon 64 (unknown type) (Winchester SH7-D0)"); FMQ ( 0,15, 1, 7, dF, "AMD Athlon 64 FX (Winchester SH7)"); FMQ ( 0,15, 1, 7, dA, "AMD Athlon 64 (Winchester SH7)"); FM ( 0,15, 1, 7, "AMD Athlon 64 (unknown type) (Winchester SH7)"); FMSQ( 0,15, 1, 8, 0, MS, "AMD mobile Sempron (Georgetown/Sonora CH-D0)"); FMSQ( 0,15, 1, 8, 0, MX, "AMD mobile Athlon XP-M (Oakville CH-D0)"); FMSQ( 0,15, 1, 8, 0, MA, "AMD mobile Athlon 64 (Oakville CH-D0)"); FMSQ( 0,15, 1, 8, 0, dA, "AMD Athlon 64 (Winchester CH-D0)"); FMS ( 0,15, 1, 8, 0, "AMD Athlon 64 (unknown type) (Winchester/Oakville/Georgetown/Sonora CH-D0)"); FMQ ( 0,15, 1, 8, MS, "AMD mobile Sempron (Georgetown/Sonora CH)"); FMQ ( 0,15, 1, 8, MX, "AMD mobile Athlon XP-M (Oakville CH)"); FMQ ( 0,15, 1, 8, MA, "AMD mobile Athlon 64 (Oakville CH)"); FMQ ( 0,15, 1, 8, dA, "AMD Athlon 64 (Winchester CH)"); FM ( 0,15, 1, 8, "AMD Athlon 64 (unknown type) (Winchester/Oakville/Georgetown/Sonora CH)"); FMS ( 0,15, 1,11, 0, "AMD Athlon 64 (Winchester CH-D0)"); FM ( 0,15, 1,11, "AMD Athlon 64 (Winchester CH)"); FMSQ( 0,15, 1,12, 0, MS, "AMD mobile Sempron (Georgetown/Sonora DH8-D0)"); FMSQ( 0,15, 1,12, 0, dS, "AMD Sempron (Palermo DH8-D0)"); FMSQ( 0,15, 1,12, 0, MX, "AMD Athlon XP-M (Winchester DH8-D0)"); FMSQ( 0,15, 1,12, 0, MA, "AMD mobile Athlon 64 (Oakville DH8-D0)"); FMSQ( 0,15, 1,12, 0, dA, "AMD Athlon 64 (Winchester DH8-D0)"); FMS ( 0,15, 1,12, 0, "AMD Athlon 64 (unknown type) (Winchester/Oakville/Georgetown/Sonora/Palermo DH8-D0)"); FMQ ( 0,15, 1,12, MS, "AMD mobile Sempron (Georgetown/Sonora DH8)"); FMQ ( 0,15, 1,12, dS, "AMD Sempron (Palermo DH8)"); FMQ ( 0,15, 1,12, MX, "AMD Athlon XP-M (Winchester DH8)"); FMQ ( 0,15, 1,12, MA, "AMD mobile Athlon 64 (Oakville DH8)"); FMQ ( 0,15, 1,12, dA, "AMD Athlon 64 (Winchester DH8)"); FM ( 0,15, 1,12, "AMD Athlon 64 (Winchester/Oakville/Georgetown/Sonora/Palermo DH8)"); FMSQ( 0,15, 1,15, 0, dS, "AMD Sempron (Palermo DH8-D0)"); FMSQ( 0,15, 1,15, 0, dA, "AMD Athlon 64 (Winchester DH8-D0)"); FMS ( 0,15, 1,15, 0, "AMD Athlon 64 (Winchester DH8-D0) / Sempron (Palermo DH8-D0)"); FMQ ( 0,15, 1,15, dS, "AMD Sempron (Palermo DH8)"); FMQ ( 0,15, 1,15, dA, "AMD Athlon 64 (Winchester DH8)"); FM ( 0,15, 1,15, "AMD Athlon 64 (unknown type) (Winchester/Palermo DH8)"); FMSQ( 0,15, 2, 1, 0, s8, "AMD Dual Core Opteron (Egypt JH-E1)"); FMSQ( 0,15, 2, 1, 0, sO, "AMD Dual Core Opteron (Italy JH-E1)"); FMS ( 0,15, 2, 1, 0, "AMD Dual Core Opteron (Italy/Egypt JH-E1)"); FMSQ( 0,15, 2, 1, 2, s8, "AMD Dual Core Opteron (Egypt JH-E6)"); FMSQ( 0,15, 2, 1, 2, sO, "AMD Dual Core Opteron (Italy JH-E6)"); FMS ( 0,15, 2, 1, 2, "AMD Dual Core Opteron (Italy/Egypt JH-E6)"); FMQ ( 0,15, 2, 1, s8, "AMD Dual Core Opteron (Egypt JH)"); FMQ ( 0,15, 2, 1, sO, "AMD Dual Core Opteron (Italy JH)"); FM ( 0,15, 2, 1, "AMD Dual Core Opteron (Italy/Egypt JH)"); FMSQ( 0,15, 2, 3, 2, DO, "AMD Dual Core Opteron (Denmark JH-E6)"); FMSQ( 0,15, 2, 3, 2, dF, "AMD Athlon 64 FX (Toledo JH-E6)"); FMSQ( 0,15, 2, 3, 2, dm, "AMD Athlon 64 X2 (Manchester JH-E6)"); FMSQ( 0,15, 2, 3, 2, dA, "AMD Athlon 64 X2 (Toledo JH-E6)"); FMS ( 0,15, 2, 3, 2, "AMD Athlon 64 (unknown type) (Toledo/Manchester/Denmark JH-E6)"); FMQ ( 0,15, 2, 3, sO, "AMD Dual Core Opteron (Denmark JH)"); FMQ ( 0,15, 2, 3, dF, "AMD Athlon 64 FX (Toledo JH)"); FMQ ( 0,15, 2, 3, dm, "AMD Athlon 64 X2 (Manchester JH)"); FMQ ( 0,15, 2, 3, dA, "AMD Athlon 64 X2 (Toledo JH)"); FM ( 0,15, 2, 3, "AMD Athlon 64 (unknown type) (Toledo/Manchester/Denmark JH)"); FMSQ( 0,15, 2, 4, 2, MA, "AMD mobile Athlon 64 (Newark SH-E5)"); FMSQ( 0,15, 2, 4, 2, MT, "AMD mobile Turion (Lancaster/Richmond SH-E5)"); FMS ( 0,15, 2, 4, 2, "AMD mobile Athlon 64 (unknown type) (Newark/Lancaster/Richmond SH-E5)"); FMQ ( 0,15, 2, 4, MA, "AMD mobile Athlon 64 (Newark SH)"); FMQ ( 0,15, 2, 4, MT, "AMD mobile Turion (Lancaster/Richmond SH)"); FM ( 0,15, 2, 4, "AMD mobile Athlon 64 (unknown type) (Newark/Lancaster/Richmond SH)"); FMQ ( 0,15, 2, 5, s8, "AMD Opteron (Athens SH-E4)"); FMQ ( 0,15, 2, 5, sO, "AMD Opteron (Troy SH-E4)"); FM ( 0,15, 2, 5, "AMD Opteron (Troy/Athens SH-E4)"); FMSQ( 0,15, 2, 7, 1, sO, "AMD Opteron (Venus SH-E4)"); FMSQ( 0,15, 2, 7, 1, dF, "AMD Athlon 64 FX (San Diego SH-E4)"); FMSQ( 0,15, 2, 7, 1, dA, "AMD Athlon 64 (San Diego SH-E4)"); FMS ( 0,15, 2, 7, 1, "AMD Athlon 64 (unknown type) (Venus/San Diego SH-E4)"); FMQ ( 0,15, 2, 7, sO, "AMD Opteron (San Diego SH)"); FMQ ( 0,15, 2, 7, dF, "AMD Athlon 64 FX (San Diego SH)"); FMQ ( 0,15, 2, 7, dA, "AMD Athlon 64 (San Diego SH)"); FM ( 0,15, 2, 7, "AMD Athlon 64 (unknown type) (San Diego SH)"); FM ( 0,15, 2,11, "AMD Athlon 64 X2 (Manchester BH-E4)"); FMS ( 0,15, 2,12, 0, "AMD Sempron (Palermo DH-E3)"); FMSQ( 0,15, 2,12, 2, MS, "AMD mobile Sempron (Albany/Roma DH-E6)"); FMSQ( 0,15, 2,12, 2, dS, "AMD Sempron (Palermo DH-E6)"); FMSQ( 0,15, 2,12, 2, dA, "AMD Athlon 64 (Venice DH-E6)"); FMS ( 0,15, 2,12, 2, "AMD Athlon 64 (Venice/Palermo/Albany/Roma DH-E6)"); FMQ ( 0,15, 2,12, MS, "AMD mobile Sempron (Albany/Roma DH)"); FMQ ( 0,15, 2,12, dS, "AMD Sempron (Palermo DH)"); FMQ ( 0,15, 2,12, dA, "AMD Athlon 64 (Venice DH)"); FM ( 0,15, 2,12, "AMD Athlon 64 (Venice/Palermo/Albany/Roma DH)"); FMSQ( 0,15, 2,15, 0, dS, "AMD Sempron (Palermo DH-E3)"); FMSQ( 0,15, 2,15, 0, dA, "AMD Athlon 64 (Venice DH-E3)"); FMS ( 0,15, 2,15, 0, "AMD Athlon 64 (Venice/Palermo DH-E3)"); FMSQ( 0,15, 2,15, 2, dS, "AMD Sempron (Palermo DH-E6)"); FMSQ( 0,15, 2,15, 2, dA, "AMD Athlon 64 (Venice DH-E6)"); FMS ( 0,15, 2,15, 2, "AMD Athlon 64 (Venice/Palermo DH-E6)"); FMQ ( 0,15, 2,15, dS, "AMD Sempron (Palermo DH)"); FMQ ( 0,15, 2,15, dA, "AMD Athlon 64 (Venice DH)"); FM ( 0,15, 2,15, "AMD Athlon 64 (Venice/Palermo DH)"); FMS ( 0,15, 4, 1, 2, "AMD Dual-Core Opteron (Santa Rosa JH-F2)"); FMS ( 0,15, 4, 1, 3, "AMD Dual-Core Opteron (Santa Rosa JH-F3)"); FM ( 0,15, 4, 1, "AMD Dual-Core Opteron (Santa Rosa)"); FMSQ( 0,15, 4, 3, 2, DO, "AMD Dual-Core Opteron (Santa Rosa JH-F2)"); FMSQ( 0,15, 4, 3, 2, sO, "AMD Opteron (Santa Rosa JH-F2)"); FMSQ( 0,15, 4, 3, 2, dF, "AMD Athlon 64 FX Dual-Core (Windsor JH-F2)"); FMSQ( 0,15, 4, 3, 2, dA, "AMD Athlon 64 X2 Dual-Core (Windsor JH-F2)"); FMS ( 0,15, 4, 3, 2, "AMD Athlon 64 (unknown type) (Windsor JH-F2)"); FMSQ( 0,15, 4, 3, 3, DO, "AMD Dual-Core Opteron (Santa Rosa JH-F3)"); FMSQ( 0,15, 4, 3, 3, sO, "AMD Opteron (Santa Rosa JH-F3)"); FMSQ( 0,15, 4, 3, 3, dF, "AMD Athlon 64 FX Dual-Core (Windsor JH-F3)"); FMSQ( 0,15, 4, 3, 3, dA, "AMD Athlon 64 X2 Dual-Core (Windsor JH-F3)"); FMS ( 0,15, 4, 3, 3, "AMD Athlon 64 (unknown type) (Windsor/Santa Rosa JH-F3)"); FMQ ( 0,15, 4, 3, DO, "AMD Dual-Core Opteron (Santa Rosa)"); FMQ ( 0,15, 4, 3, sO, "AMD Opteron (Santa Rosa)"); FMQ ( 0,15, 4, 3, dF, "AMD Athlon 64 FX Dual-Core (Windsor)"); FMQ ( 0,15, 4, 3, dA, "AMD Athlon 64 X2 Dual-Core (Windsor)"); FM ( 0,15, 4, 3, "AMD Athlon 64 (unknown type) (Windsor/Santa Rosa)"); FMSQ( 0,15, 4, 8, 2, dA, "AMD Athlon 64 X2 Dual-Core (Windsor BH-F2)"); FMSQ( 0,15, 4, 8, 2, Mt, "AMD Turion 64 X2 (Trinidad BH-F2)"); FMSQ( 0,15, 4, 8, 2, MT, "AMD Turion 64 X2 (Taylor BH-F2)"); FMS ( 0,15, 4, 8, 2, "AMD Athlon 64 (unknown type) (Windsor/Taylor/Trinidad BH-F2)"); FMQ ( 0,15, 4, 8, dA, "AMD Athlon 64 X2 Dual-Core (Windsor)"); FMQ ( 0,15, 4, 8, Mt, "AMD Turion 64 X2 (Trinidad)"); FMQ ( 0,15, 4, 8, MT, "AMD Turion 64 X2 (Taylor)"); FM ( 0,15, 4, 8, "AMD Athlon 64 (unknown type) (Windsor/Taylor/Trinidad)"); FMS ( 0,15, 4,11, 2, "AMD Athlon 64 X2 Dual-Core (Windsor BH-F2)"); FM ( 0,15, 4,11, "AMD Athlon 64 X2 Dual-Core (Windsor)"); FMSQ( 0,15, 4,12, 2, MS, "AMD mobile Sempron (Keene BH-F2)"); FMSQ( 0,15, 4,12, 2, dS, "AMD Sempron (Manila BH-F2)"); FMSQ( 0,15, 4,12, 2, Mt, "AMD Turion (Trinidad BH-F2)"); FMSQ( 0,15, 4,12, 2, MT, "AMD Turion (Taylor BH-F2)"); FMSQ( 0,15, 4,12, 2, dA, "AMD Athlon 64 (Orleans BH-F2)"); FMS ( 0,15, 4,12, 2, "AMD Athlon 64 (unknown type) (Orleans/Manila/Keene/Taylor/Trinidad BH-F2)"); FMQ ( 0,15, 4,12, MS, "AMD mobile Sempron (Keene)"); FMQ ( 0,15, 4,12, dS, "AMD Sempron (Manila)"); FMQ ( 0,15, 4,12, Mt, "AMD Turion (Trinidad)"); FMQ ( 0,15, 4,12, MT, "AMD Turion (Taylor)"); FMQ ( 0,15, 4,12, dA, "AMD Athlon 64 (Orleans)"); FM ( 0,15, 4,12, "AMD Athlon 64 (unknown type) (Orleans/Manila/Keene/Taylor/Trinidad)"); FMSQ( 0,15, 4,15, 2, MS, "AMD mobile Sempron (Keene DH-F2)"); FMSQ( 0,15, 4,15, 2, dS, "AMD Sempron (Manila DH-F2)"); FMSQ( 0,15, 4,15, 2, dA, "AMD Athlon 64 (Orleans DH-F2)"); FMS ( 0,15, 4,15, 2, "AMD Athlon 64 (unknown type) (Orleans/Manila/Keene DH-F2)"); FMQ ( 0,15, 4,15, MS, "AMD mobile Sempron (Keene)"); FMQ ( 0,15, 4,15, dS, "AMD Sempron (Manila)"); FMQ ( 0,15, 4,15, dA, "AMD Athlon 64 (Orleans)"); FM ( 0,15, 4,15, "AMD Athlon 64 (unknown type) (Orleans/Manila/Keene)"); FMS ( 0,15, 5,13, 3, "AMD Opteron (Santa Rosa JH-F3)"); FM ( 0,15, 5,13, "AMD Opteron (Santa Rosa)"); FMSQ( 0,15, 5,15, 2, MS, "AMD mobile Sempron (Keene DH-F2)"); FMSQ( 0,15, 5,15, 2, dS, "AMD Sempron (Manila DH-F2)"); FMSQ( 0,15, 5,15, 2, dA, "AMD Athlon 64 (Orleans DH-F2)"); FMS ( 0,15, 5,15, 2, "AMD Athlon 64 (unknown type) (Orleans/Manila/Keene DH-F2)"); FMS ( 0,15, 5,15, 3, "AMD Athlon 64 (Orleans DH-F3)"); FMQ ( 0,15, 5,15, MS, "AMD mobile Sempron (Keene)"); FMQ ( 0,15, 5,15, dS, "AMD Sempron (Manila)"); FMQ ( 0,15, 5,15, dA, "AMD Athlon 64 (Orleans)"); FM ( 0,15, 5,15, "AMD Athlon 64 (unknown type) (Orleans/Manila/Keene)"); FM ( 0,15, 5,15, "AMD Athlon 64 (Orleans)"); FMS ( 0,15, 6, 8, 1, "AMD Turion 64 X2 (Tyler BH-G1)"); FMSQ( 0,15, 6, 8, 2, MT, "AMD Turion 64 X2 (Tyler BH-G2)"); FMSQ( 0,15, 6, 8, 2, dS, "AMD Sempron Dual-Core (Tyler BH-G2)"); FMS ( 0,15, 6, 8, 2, "AMD Turion 64 (unknown type) (Tyler BH-G2)"); FMQ ( 0,15, 6, 8, MT, "AMD Turion 64 X2 (Tyler)"); FMQ ( 0,15, 6, 8, dS, "AMD Sempron Dual-Core (Tyler)"); FM ( 0,15, 6, 8, "AMD Turion 64 (unknown type) (Tyler)"); FMSQ( 0,15, 6,11, 1, dS, "AMD Sempron Dual-Core (Sparta BH-G1)"); FMSQ( 0,15, 6,11, 1, dA, "AMD Athlon 64 X2 Dual-Core (Brisbane BH-G1)"); FMS ( 0,15, 6,11, 1, "AMD Athlon 64 (unknown type) (Brisbane/Sparta BH-G1)"); FMSQ( 0,15, 6,11, 2, dA, "AMD Athlon 64 X2 Dual-Core (Brisbane BH-G2)"); FMSQ( 0,15, 6,11, 2, Mn, "AMD Turion Neo X2 Dual-Core (Huron BH-G2)"); FMSQ( 0,15, 6,11, 2, MN, "AMD Athlon Neo X2 (Huron BH-G2)"); FMS ( 0,15, 6,11, 2, "AMD Athlon 64 (unknown type) (Brisbane/Huron BH-G2)"); FMQ ( 0,15, 6,11, dS, "AMD Sempron Dual-Core (Sparta)"); FMQ ( 0,15, 6,11, Mn, "AMD Turion Neo X2 Dual-Core (Huron)"); FMQ ( 0,15, 6,11, MN, "AMD Athlon Neo X2 (Huron)"); FMQ ( 0,15, 6,11, dA, "AMD Athlon 64 X2 Dual-Core (Brisbane)"); FM ( 0,15, 6,11, "AMD Athlon 64 (unknown type) (Brisbane/Sparta/Huron)"); FMSQ( 0,15, 6,12, 2, MS, "AMD mobile Sempron (Sherman DH-G2)"); FMSQ( 0,15, 6,12, 2, dS, "AMD Sempron (Sparta DH-G2)"); FMSQ( 0,15, 6,12, 2, dA, "AMD Athlon 64 (Lima DH-G2)"); FMS ( 0,15, 6,12, 2, "AMD Athlon 64 (unknown type) (Lima/Sparta/Sherman DH-G2)"); FMQ ( 0,15, 6,12, MS, "AMD mobile Sempron (Sherman)"); FMQ ( 0,15, 6,12, dS, "AMD Sempron (Sparta)"); FMQ ( 0,15, 6,12, dA, "AMD Athlon 64 (Lima)"); FM ( 0,15, 6,12, "AMD Athlon 64 (unknown type) (Lima/Sparta/Sherman)"); FMSQ( 0,15, 6,15, 2, MS, "AMD mobile Sempron (Sherman DH-G2)"); FMSQ( 0,15, 6,15, 2, dS, "AMD Sempron (Sparta DH-G2)"); FMSQ( 0,15, 6,15, 2, MN, "AMD Athlon Neo (Huron DH-G2)"); FMS ( 0,15, 6,15, 2, "AMD Athlon Neo (unknown type) (Huron/Sparta/Sherman DH-G2)"); FMQ ( 0,15, 6,15, MS, "AMD mobile Sempron (Sherman)"); FMQ ( 0,15, 6,15, dS, "AMD Sempron (Sparta)"); FMQ ( 0,15, 6,15, MN, "AMD Athlon Neo (Huron)"); FM ( 0,15, 6,15, "AMD Athlon Neo (unknown type) (Huron/Sparta/Sherman)"); FMSQ( 0,15, 7,12, 2, MS, "AMD mobile Sempron (Sherman DH-G2)"); FMSQ( 0,15, 7,12, 2, dS, "AMD Sempron (Sparta DH-G2)"); FMSQ( 0,15, 7,12, 2, dA, "AMD Athlon (Lima DH-G2)"); FMS ( 0,15, 7,12, 2, "AMD Athlon (unknown type) (Lima/Sparta/Sherman DH-G2)"); FMQ ( 0,15, 7,12, MS, "AMD mobile Sempron (Sherman)"); FMQ ( 0,15, 7,12, dS, "AMD Sempron (Sparta)"); FMQ ( 0,15, 7,12, dA, "AMD Athlon (Lima)"); FM ( 0,15, 7,12, "AMD Athlon (unknown type) (Lima/Sparta/Sherman)"); FMSQ( 0,15, 7,15, 1, MS, "AMD mobile Sempron (Sherman DH-G1)"); FMSQ( 0,15, 7,15, 1, dS, "AMD Sempron (Sparta DH-G1)"); FMSQ( 0,15, 7,15, 1, dA, "AMD Athlon 64 (Lima DH-G1)"); FMS ( 0,15, 7,15, 1, "AMD Athlon 64 (unknown type) (Lima/Sparta/Sherman DH-G1)"); FMSQ( 0,15, 7,15, 2, MS, "AMD mobile Sempron (Sherman DH-G2)"); FMSQ( 0,15, 7,15, 2, dS, "AMD Sempron (Sparta DH-G2)"); FMSQ( 0,15, 7,15, 2, MN, "AMD Athlon Neo (Huron DH-G2)"); FMSQ( 0,15, 7,15, 2, dA, "AMD Athlon 64 (Lima DH-G2)"); FMS ( 0,15, 7,15, 2, "AMD Athlon 64 (unknown type) (Lima/Sparta/Sherman/Huron DH-G2)"); FMQ ( 0,15, 7,15, MS, "AMD mobile Sempron (Sherman)"); FMQ ( 0,15, 7,15, dS, "AMD Sempron (Sparta)"); FMQ ( 0,15, 7,15, MN, "AMD Athlon Neo (Huron)"); FMQ ( 0,15, 7,15, dA, "AMD Athlon 64 (Lima)"); FM ( 0,15, 7,15, "AMD Athlon 64 (unknown type) (Lima/Sparta/Sherman/Huron)"); FMS ( 0,15, 12, 1, 3, "AMD Athlon 64 FX Dual-Core (Windsor JH-F3)"); FM ( 0,15, 12, 1, "AMD Athlon 64 FX Dual-Core (Windsor)"); F ( 0,15, "AMD (unknown model)"); FMS ( 1,15, 0, 0, 0, "AMD (unknown type) (Barcelona DR-A0)"); // sandpile.org FMS ( 1,15, 0, 0, 1, "AMD (unknown type) (Barcelona DR-A1)"); // sandpile.org FMS ( 1,15, 0, 0, 2, "AMD (unknown type) (Barcelona DR-A2)"); // sandpile.org FMS ( 1,15, 0, 2, 0, "AMD (unknown type) (Barcelona DR-B0)"); // sandpile.org FMSQ( 1,15, 0, 2, 1, sO, "AMD Quad-Core Opteron (Barcelona DR-B1)"); FMS ( 1,15, 0, 2, 1, "AMD (unknown type) (Barcelona DR-B1)"); FMSQ( 1,15, 0, 2, 2, EO, "AMD Embedded Opteron (Barcelona DR-B2)"); FMSQ( 1,15, 0, 2, 2, sO, "AMD Quad-Core Opteron (Barcelona DR-B2)"); FMSQ( 1,15, 0, 2, 2, Tp, "AMD Phenom Triple-Core (Toliman DR-B2)"); FMSQ( 1,15, 0, 2, 2, Qp, "AMD Phenom Quad-Core (Agena DR-B2)"); FMS ( 1,15, 0, 2, 2, "AMD (unknown type) (Barcelona/Toliman/Agena DR-B2)"); FMSQ( 1,15, 0, 2, 3, EO, "AMD Embedded Opteron (Barcelona DR-B3)"); FMSQ( 1,15, 0, 2, 3, sO, "AMD Quad-Core Opteron (Barcelona DR-B3)"); FMSQ( 1,15, 0, 2, 3, Tp, "AMD Phenom Triple-Core (Toliman DR-B3)"); FMSQ( 1,15, 0, 2, 3, Qp, "AMD Phenom Quad-Core (Agena DR-B3)"); FMSQ( 1,15, 0, 2, 3, dA, "AMD Athlon Dual-Core (Kuma DR-B3)"); FMS ( 1,15, 0, 2, 3, "AMD (unknown type) (Barcelona/Toliman/Agena/Kuma DR-B3)"); FMS ( 1,15, 0, 2, 10, "AMD Quad-Core Opteron (Barcelona DR-BA)"); FMQ ( 1,15, 0, 2, EO, "AMD Embedded Opteron (Barcelona)"); FMQ ( 1,15, 0, 2, sO, "AMD Quad-Core Opteron (Barcelona)"); FMQ ( 1,15, 0, 2, Tp, "AMD Phenom Triple-Core (Toliman)"); FMQ ( 1,15, 0, 2, Qp, "AMD Phenom Quad-Core (Agena)"); FMQ ( 1,15, 0, 2, dA, "AMD Athlon Dual-Core (Kuma)"); FM ( 1,15, 0, 2, "AMD (unknown type) (Barcelona/Toliman/Agena/Kuma)"); FMS ( 1,15, 0, 4, 0, "AMD Athlon (unknown type) (Regor/Propus/Shanghai/Callisto/Heka/Deneb RB-C0)"); // sandpile.org FMS ( 1,15, 0, 4, 1, "AMD Athlon (unknown type) (Regor/Propus/Shanghai/Callisto/Heka/Deneb RB-C1)"); // sandpile.org FMSQ( 1,15, 0, 4, 2, EO, "AMD Embedded Opteron (Shanghai RB-C2)"); FMSQ( 1,15, 0, 4, 2, sO, "AMD Quad-Core Opteron (Shanghai RB-C2)"); FMSQ( 1,15, 0, 4, 2, dr, "AMD Athlon Dual-Core (Propus RB-C2)"); FMSQ( 1,15, 0, 4, 2, dA, "AMD Athlon Dual-Core (Regor RB-C2)"); FMSQ( 1,15, 0, 4, 2, Dp, "AMD Phenom II X2 (Callisto RB-C2)"); FMSQ( 1,15, 0, 4, 2, Tp, "AMD Phenom II X3 (Heka RB-C2)"); FMSQ( 1,15, 0, 4, 2, Qp, "AMD Phenom II X4 (Deneb RB-C2)"); FMS ( 1,15, 0, 4, 2, "AMD Athlon (unknown type) (Regor/Propus/Shanghai/Callisto/Heka/Deneb RB-C2)"); FMSQ( 1,15, 0, 4, 3, Dp, "AMD Phenom II X2 (Callisto RB-C3)"); FMSQ( 1,15, 0, 4, 3, Tp, "AMD Phenom II X3 (Heka RB-C3)"); FMSQ( 1,15, 0, 4, 3, Qp, "AMD Phenom II X4 (Deneb RB-C3)"); FMS ( 1,15, 0, 4, 3, "AMD Phenom II (unknown type) (Callisto/Heka/Deneb RB-C3)"); FMQ ( 1,15, 0, 4, EO, "AMD Embedded Opteron (Shanghai)"); FMQ ( 1,15, 0, 4, sO, "AMD Quad-Core Opteron (Shanghai)"); FMQ ( 1,15, 0, 4, dr, "AMD Athlon Dual-Core (Propus)"); FMQ ( 1,15, 0, 4, dA, "AMD Athlon Dual-Core (Regor)"); FMQ ( 1,15, 0, 4, Dp, "AMD Phenom II X2 (Callisto)"); FMQ ( 1,15, 0, 4, Tp, "AMD Phenom II X3 (Heka)"); FMQ ( 1,15, 0, 4, Qp, "AMD Phenom II X4 (Deneb)"); FM ( 1,15, 0, 4, "AMD Athlon (unknown type) (Regor/Propus/Shanghai/Callisto/Heka/Deneb)"); FMS ( 1,15, 0, 5, 0, "AMD Athlon (unknown type) (Regor/Rana/Propus BL-C0)"); // sandpile.org FMS ( 1,15, 0, 5, 1, "AMD Athlon (unknown type) (Regor/Rana/Propus BL-C1)"); // sandpile.org FMSQ( 1,15, 0, 5, 2, DA, "AMD Athlon II X2 (Regor BL-C2)"); FMSQ( 1,15, 0, 5, 2, TA, "AMD Athlon II X3 (Rana BL-C2)"); FMSQ( 1,15, 0, 5, 2, QA, "AMD Athlon II X4 (Propus BL-C2)"); FMS ( 1,15, 0, 5, 2, "AMD Athlon (unknown type) (Regor/Rana/Propus BL-C2)"); FMSQ( 1,15, 0, 5, 3, TA, "AMD Athlon II X3 (Rana BL-C3)"); FMSQ( 1,15, 0, 5, 3, QA, "AMD Athlon II X4 (Propus BL-C3)"); FMSQ( 1,15, 0, 5, 3, Tp, "AMD Phenom II Triple-Core (Heka BL-C3)"); FMSQ( 1,15, 0, 5, 3, Qp, "AMD Phenom II Quad-Core (Deneb BL-C3)"); FMS ( 1,15, 0, 5, 3, "AMD Athlon (unknown type) (Regor/Rana/Propus/Callisto/Heka/Deneb BL-C3)"); FMQ ( 1,15, 0, 5, DA, "AMD Athlon II X2 (Regor)"); FMQ ( 1,15, 0, 5, TA, "AMD Athlon II X3 (Rana)"); FMQ ( 1,15, 0, 5, QA, "AMD Athlon II X4 (Propus)"); FMQ ( 1,15, 0, 5, Tp, "AMD Phenom II Triple-Core (Heka)"); FMQ ( 1,15, 0, 5, Qp, "AMD Phenom II Quad-Core (Deneb)"); FM ( 1,15, 0, 5, "AMD Athlon (unknown type) (Regor/Rana/Propus/Callisto/Heka/Deneb)"); FMS ( 1,15, 0, 6, 0, "AMD Athlon (unknown type) (Regor/Sargas/Caspain DA-C0)"); FMS ( 1,15, 0, 6, 1, "AMD Athlon (unknown type) (Regor/Sargas/Caspain DA-C1)"); FMSQ( 1,15, 0, 6, 2, MS, "AMD Sempron Mobile (Sargas DA-C2)"); FMSQ( 1,15, 0, 6, 2, dS, "AMD Sempron II (Sargas DA-C2)"); FMSQ( 1,15, 0, 6, 2, MT, "AMD Turion II Dual-Core Mobile (Caspian DA-C2)"); FMSQ( 1,15, 0, 6, 2, MA, "AMD Athlon II Dual-Core Mobile (Regor DA-C2)"); FMSQ( 1,15, 0, 6, 2, DA, "AMD Athlon II X2 (Regor DA-C2)"); FMSQ( 1,15, 0, 6, 2, dA, "AMD Athlon II (Sargas DA-C2)"); FMS ( 1,15, 0, 6, 2, "AMD Athlon (unknown type) (Regor/Sargas/Caspain DA-C2)"); FMSQ( 1,15, 0, 6, 3, Ms, "AMD V-Series Mobile (Champlain DA-C3)"); FMSQ( 1,15, 0, 6, 3, DS, "AMD Sempron II X2 (Regor DA-C3)"); FMSQ( 1,15, 0, 6, 3, dS, "AMD Sempron II (Sargas DA-C3)"); FMSQ( 1,15, 0, 6, 3, MT, "AMD Turion II Dual-Core Mobile (Champlain DA-C3)"); FMSQ( 1,15, 0, 6, 3, Mp, "AMD Phenom II Dual-Core Mobile (Champlain DA-C3)"); FMSQ( 1,15, 0, 6, 3, MA, "AMD Athlon II Dual-Core Mobile (Champlain DA-C3)"); FMSQ( 1,15, 0, 6, 3, DA, "AMD Athlon II X2 (Regor DA-C3)"); FMSQ( 1,15, 0, 6, 3, dA, "AMD Athlon II (Sargas DA-C3)"); FMS ( 1,15, 0, 6, 3, "AMD Athlon (unknown type) (Regor/Sargas/Champlain DA-C3)"); FMQ ( 1,15, 0, 6, Ms, "AMD V-Series Mobile (Champlain)"); FMQ ( 1,15, 0, 6, MS, "AMD Sempron Mobile (Sargas)"); FMQ ( 1,15, 0, 6, DS, "AMD Sempron II X2 (Regor)"); FMQ ( 1,15, 0, 6, dS, "AMD Sempron II (Sargas)"); FMQ ( 1,15, 0, 6, MT, "AMD Turion II Dual-Core Mobile (Caspian / Champlain)"); FMQ ( 1,15, 0, 6, Mp, "AMD Phenom II Dual-Core Mobile (Champlain)"); FMQ ( 1,15, 0, 6, MA, "AMD Athlon II Dual-Core Mobile (Regor / Champlain)"); FMQ ( 1,15, 0, 6, DA, "AMD Athlon II X2 (Regor)"); FMQ ( 1,15, 0, 6, dA, "AMD Athlon II (Sargas)"); FM ( 1,15, 0, 6, "AMD Athlon (unknown type) (Regor/Sargas/Caspian/Champlain)"); FMSQ( 1,15, 0, 8, 0, SO, "AMD Six-Core Opteron (Istanbul HY-D0)"); FMSQ( 1,15, 0, 8, 0, sO, "AMD Opteron 4100 (Lisbon HY-D0)"); FMS ( 1,15, 0, 8, 0, "AMD Opteron (unknown type) (Lisbon/Istanbul HY-D0)"); FMS ( 1,15, 0, 8, 1, "AMD Opteron 4100 (Lisbon HY-D1)"); FMQ ( 1,15, 0, 8, SO, "AMD Six-Core Opteron (Istanbul)"); FMQ ( 1,15, 0, 8, sO, "AMD Opteron 4100 (Lisbon)"); FM ( 1,15, 0, 8, "AMD Opteron (unknown type) (Lisbon/Istanbul)"); FMS ( 1,15, 0, 9, 0, "AMD Opteron 6100 (Magny-Cours HY-D0)"); // sandpile.org FMS ( 1,15, 0, 9, 1, "AMD Opteron 6100 (Magny-Cours HY-D1)"); FM ( 1,15, 0, 9, "AMD Opteron 6100 (Magny-Cours)"); FMSQ( 1,15, 0,10, 0, Qp, "AMD Phenom II X4 (Zosma PH-E0)"); FMSQ( 1,15, 0,10, 0, Sp, "AMD Phenom II X6 (Thuban PH-E0)"); FMS ( 1,15, 0,10, 0, "AMD Phenom II (unknown type) (Zosma/Thuban PH-E0)"); FMQ ( 1,15, 0,10, Qp, "AMD Phenom II X4 (Zosma)"); FMQ ( 1,15, 0,10, Sp, "AMD Phenom II X6 (Thuban)"); FM ( 1,15, 0,10, "AMD Phenom II (unknown type) (Zosma/Thuban)"); F ( 1,15, "AMD (unknown model)"); FMSQ( 2,15, 0, 3, 1, MU, "AMD Turion X2 Ultra Dual-Core Mobile (Griffin LG-B1)"); FMSQ( 2,15, 0, 3, 1, MT, "AMD Turion X2 Dual-Core Mobile (Lion LG-B1)"); FMSQ( 2,15, 0, 3, 1, DS, "AMD Sempron X2 Dual-Core (Sable LG-B1)"); FMSQ( 2,15, 0, 3, 1, dS, "AMD Sempron (Sable LG-B1)"); FMSQ( 2,15, 0, 3, 1, DA, "AMD Athlon X2 Dual-Core (Lion LG-B1)"); FMSQ( 2,15, 0, 3, 1, dA, "AMD Athlon (Lion LG-B1)"); FMS ( 2,15, 0, 3, 1, "AMD Athlon (unknown type) (Lion/Sable LG-B1)"); FMQ ( 2,15, 0, 3, MU, "AMD Turion X2 Ultra (Griffin)"); FMQ ( 2,15, 0, 3, MT, "AMD Turion X2 (Lion)"); FMQ ( 2,15, 0, 3, DS, "AMD Sempron X2 Dual-Core (Sable)"); FMQ ( 2,15, 0, 3, dS, "AMD Sempron (Sable)"); FMQ ( 2,15, 0, 3, DA, "AMD Athlon X2 Dual-Core (Lion)"); FMQ ( 2,15, 0, 3, dA, "AMD Athlon (Lion)"); FM ( 2,15, 0, 3, "AMD Athlon (unknown type) (Lion/Sable)"); F ( 2,15, "AMD (unknown model)"); FMS ( 3,15, 0, 0, 0, "AMD Athlon (unknown type) (Llano LN-A0)"); // sandpile.org FMS ( 3,15, 0, 0, 1, "AMD Athlon (unknown type) (Llano LN-A1)"); // sandpile.org FMSQ( 3,15, 0, 1, 0, dS, "AMD Sempron Dual-Core (Llano LN-B0)"); FMSQ( 3,15, 0, 1, 0, dA, "AMD Athlon II Dual-Core (Llano LN-B0)"); FMSQ( 3,15, 0, 1, 0, Sa, "AMD A-Series (Llano LN-B0)"); FMSQ( 3,15, 0, 1, 0, Se, "AMD E2-Series (Llano LN-B0)"); FMS ( 3,15, 0, 1, 0, "AMD Athlon (unknown type) (Llano LN-B0)"); FMQ ( 3,15, 0, 1, dS, "AMD Sempron Dual-Core (Llano)"); FMQ ( 3,15, 0, 1, dA, "AMD Athlon II Dual-Core (Llano)"); FMQ ( 3,15, 0, 1, Sa, "AMD A-Series (Llano)"); FMQ ( 3,15, 0, 1, Se, "AMD E2-Series (Llano)"); FM ( 3,15, 0, 1, "AMD Athlon (unknown type) (Llano)"); FMS ( 3,15, 0, 2, 0, "AMD Athlon (unknown type) (Llano LN-B0)"); // sandpile.org F ( 3,15, "AMD (unknown model) (Llano)"); FMSQ( 5,15, 0, 1, 0, Sc, "AMD C-Series (Ontario ON-B0)"); FMSQ( 5,15, 0, 1, 0, Se, "AMD E-Series (Zacate ON-B0)"); FMSQ( 5,15, 0, 1, 0, Sg, "AMD G-Series (Ontario/Zacate ON-B0)"); FMSQ( 5,15, 0, 1, 0, Sz, "AMD Z-Series (Desna ON-B0)"); FMS ( 5,15, 0, 1, 0, "AMD (unknown type) (Ontario/Zacate/Desna ON-B0)"); FM ( 5,15, 0, 1, "AMD (unknown type) (Ontario/Zacate/Desna)"); FMSQ( 5,15, 0, 2, 0, Sc, "AMD C-Series (Ontario ON-C0)"); FMSQ( 5,15, 0, 2, 0, Se, "AMD E-Series (Zacate ON-C0)"); FMSQ( 5,15, 0, 2, 0, Sg, "AMD G-Series (Ontario/Zacate ON-C0)"); FMSQ( 5,15, 0, 2, 0, Sz, "AMD Z-Series (Desna ON-C0)"); FMS ( 5,15, 0, 2, 0, "AMD (unknown type) (Ontario/Zacate/Desna ON-C0)"); FM ( 5,15, 0, 2, "AMD (unknown type) (Ontario/Zacate/Desna)"); F ( 5,15, "AMD (unknown model)"); FMS ( 6,15, 0, 0, 0, "AMD (unknown type) (Interlagos/Valencia/Zurich/Zambezi OR-A0)"); // sandpile.org FMS ( 6,15, 0, 0, 1, "AMD (unknown type) (Interlagos/Valencia/Zurich/Zambezi OR-A1)"); // sandpile.org FMS ( 6,15, 0, 1, 0, "AMD (unknown type) (Interlagos/Valencia/Zurich/Zambezi OR-B0)"); // sandpile.org FMS ( 6,15, 0, 1, 1, "AMD (unknown type) (Interlagos/Valencia/Zurich/Zambezi OR-B1)"); // sandpile.org FMSQ( 6,15, 0, 1, 2, sO, "AMD Opteron 6200 (Interlagos OR-B2) / Opteron 4200 (Valencia OR-B2) / Opteron 3200 (Zurich OR-B2)"); FMSQ( 6,15, 0, 1, 2, df, "AMD FX-Series (Zambezi OR-B2)"); FMS ( 6,15, 0, 1, 2, "AMD (unknown type) (Interlagos/Valencia/Zurich/Zambezi OR-B2)"); FMQ ( 6,15, 0, 1, sO, "AMD Opteron 6200 (Interlagos) / Opteron 4200 (Valencia) / Opteron 3200 (Zurich)"); FMQ ( 6,15, 0, 1, df, "AMD FX-Series (Zambezi)"); FM ( 6,15, 0, 1, "AMD (unknown type) (Interlagos/Valencia/Zurich/Zambezi)"); FMSQ( 6,15, 0, 2, 0, sO, "AMD Opteron 6300 (Abu Dhabi OR-C0) / Opteron 4300 (Seoul OR-C0) / Opteron 3300 (Delhi OR-C0)"); FMSQ( 6,15, 0, 2, 0, df, "AMD FX-Series (Vishera OR-C0)"); FMS ( 6,15, 0, 2, 0, "AMD (unknown type) (Abu Dhabi/Seoul/Delhi/Vishera OR-C0)"); FMQ ( 6,15, 0, 2, sO, "AMD Opteron 6300 (Abu Dhabi) / Opteron 4300 (Seoul) / Opteron 3300 (Delhi)"); FMQ ( 6,15, 0, 2, df, "AMD FX-Series (Vishera)"); FM ( 6,15, 0, 2, "AMD (unknown type) (Abu Dhabi/Seoul/Delhi/Vishera)"); FMSQ( 6,15, 1, 0, 1, Sa, "AMD A-Series (Trinity TN-A1)"); FMSQ( 6,15, 1, 0, 1, Sr, "AMD R-Series (Trinity TN-A1)"); FMSQ( 6,15, 1, 0, 1, dA, "AMD Athlon Dual-Core / Athlon Quad-Core (Trinity TN-A1)"); FMSQ( 6,15, 1, 0, 1, dS, "AMD Sempron Dual-Core (Trinity TN-A1)"); FMSQ( 6,15, 1, 0, 1, dI, "AMD FirePro (Trinity TN-A1)"); FMS ( 6,15, 1, 0, 1, "AMD (unknown type) (Trinity TN-A1)"); FMQ ( 6,15, 1, 0, Sa, "AMD A-Series (Trinity)"); FMQ ( 6,15, 1, 0, Sr, "AMD R-Series (Trinity)"); FMQ ( 6,15, 1, 0, dA, "AMD Athlon Dual-Core / Athlon Quad-Core (Trinity)"); FMQ ( 6,15, 1, 0, dS, "AMD Sempron Dual-Core (Trinity)"); FMQ ( 6,15, 1, 0, dI, "AMD FirePro (Trinity)"); FM ( 6,15, 1, 0, "AMD (unknown type) (Trinity TN-A1)"); FMSQ( 6,15, 1, 3, 1, Sa, "AMD A-Series (Richland RL-A1)"); FMSQ( 6,15, 1, 3, 1, Sr, "AMD R-Series (Richland RL-A1)"); FMSQ( 6,15, 1, 3, 1, dA, "AMD Athlon Dual-Core / Athlon Quad-Core (Richland RL-A1)"); FMSQ( 6,15, 1, 3, 1, dS, "AMD Sempron Dual-Core (Richland RL-A1)"); FMSQ( 6,15, 1, 3, 1, dI, "AMD FirePro (Richland RL-A1)"); FMS ( 6,15, 1, 3, 1, "AMD (unknown type) (Richland RL-A1)"); FMQ ( 6,15, 1, 3, Sa, "AMD A-Series (Richland)"); FMQ ( 6,15, 1, 3, Sr, "AMD R-Series (Richland)"); FMQ ( 6,15, 1, 3, dA, "AMD Athlon Dual-Core / Athlon Quad-Core (Richland)"); FMQ ( 6,15, 1, 3, dS, "AMD Sempron Dual-Core (Richland)"); FMQ ( 6,15, 1, 3, dI, "AMD FirePro (Richland)"); FM ( 6,15, 1, 3, "AMD (unknown type) (Richland)"); FMS ( 6,15, 3, 0, 0, "AMD (unknown type) (Kaveri KV-A0)"); FMSQ( 6,15, 3, 0, 1, Sa, "AMD Elite Performance A-Series (Kaveri KV-A1)"); FMSQ( 6,15, 3, 0, 1, Mr, "AMD Mobile R-Series (Kaveri KV-A1)"); FMSQ( 6,15, 3, 0, 1, sO, "AMD Opteron X1200 / X2200 (Kaveri KV-A1)"); FMSQ( 6,15, 3, 0, 1, Sr, "AMD R-Series (Bald Eagle KV-A1)"); // undocumented, but instlatx64 example FMS ( 6,15, 3, 0, 1, "AMD (unknown type) (Kaveri KV-A1)"); FMQ ( 6,15, 3, 0, Sa, "AMD Elite Performance A-Series (Kaveri)"); FMQ ( 6,15, 3, 0, Mr, "AMD Mobile R-Series (Kaveri)"); FMQ ( 6,15, 3, 0, sO, "AMD Opteron X1200 / X2200 (Kaveri)"); FM ( 6,15, 3, 0, "AMD (unknown type) (Kaveri)"); FMSQ( 6,15, 3, 8, 1, Sa, "AMD A-Series (Godavari A1)"); // sandpile.org FMS ( 6,15, 3, 8, 1, "AMD (unknown type) (Godavari A1)"); // sandpile.org FMQ ( 6,15, 3, 8, Sa, "AMD A-Series (Godavari)"); FM ( 6,15, 3, 8, "AMD (unknown type) (Godavari)"); FMS ( 6,15, 6, 0, 0, "AMD (unknown type) (Carrizo/Toronto CZ-A0)"); // sandpile.org FMSQ( 6,15, 6, 0, 1, sO, "AMD Opteron (Toronto CZ-A1)"); // undocumented, but instlatx64 sample FMSQ( 6,15, 6, 0, 1, df, "AMD FX-Series (Carrizo CZ-A1)"); // undocumented, but instlatx64 sample FMS ( 6,15, 6, 0, 1, "AMD (unknown type) (Carrizo/Toronto CZ-A1)"); // undocumented, but instlatx64 sample FMQ ( 6,15, 6, 0, sO, "AMD Opteron (Toronto)"); // undocumented, but instlatx64 sample FMQ ( 6,15, 6, 0, df, "AMD FX-Series (Carrizo)"); // undocumented, but instlatx64 sample FM ( 6,15, 6, 0, "AMD (unknown type) (Carrizo/Toronto)"); // undocumented, but instlatx64 sample FMSQ( 6,15, 6, 5, 1, Sa, "AMD A-Series (Carrizo/Bristol Ridge/Stoney Ridge CZ-A1/BR-A1)"); // undocumented, but samples from Alexandros Couloumbis & instlatx64; sandpile.org stepping FMSQ( 6,15, 6, 5, 1, Se, "AMD E-Series (Stoney Ridge CZ-A1/BR-A1)"); // undocumented; sandpile.org stepping FMSQ( 6,15, 6, 5, 1, Sg, "AMD G-Series (Brown Falcon/Prairie Falcon CZ-A1/BR-A1)"); // undocumented; sandpile.org stepping FMSQ( 6,15, 6, 5, 1, Sr, "AMD R-Series (Merlin Falcon CZ-A1/BR-A1)"); // undocumented; sandpile.org stepping FMS ( 6,15, 6, 5, 1, "AMD (unknown type) (Carrizo/Bristol Ridge/Stoney Ridge/Toronto/Brown Falcon/Merlin Falcon/Prairie Falcon CZ-A1/BR-A1)"); // sandpile.org FMQ ( 6,15, 6, 5, Sa, "AMD A-Series (Carrizo/Bristol Ridge/Stoney Ridge)"); // undocumented, but samples from Alexandros Couloumbis & instlatx64 FMQ ( 6,15, 6, 5, Se, "AMD E-Series (Stoney Ridge)"); // undocumented FMQ ( 6,15, 6, 5, Sg, "AMD G-Series (Brown Falcon/Prairie Falcon)"); // undocumented FMQ ( 6,15, 6, 5, Sr, "AMD R-Series (Merlin Falcon)"); // undocumented FM ( 6,15, 6, 5, "AMD (unknown type) (Carrizo/Bristol Ridge/Stoney Ridge/Toronto/Brown Falcon/Merlin Falcon/Prairie Falcon)"); // undocumented, but sample from Alexandros Couloumbis FMSQ( 6,15, 7, 0, 0, Sa, "AMD A-Series (Carrizo/Bristol Ridge/Stoney Ridge ST-A0)"); FMSQ( 6,15, 7, 0, 0, Se, "AMD E-Series (Stoney Ridge ST-A0)"); FMSQ( 6,15, 7, 0, 0, Sg, "AMD G-Series (Brown Falcon/Prairie Falcon ST-A0)"); FMSQ( 6,15, 7, 0, 0, Sr, "AMD R-Series (Merlin Falcon ST-A0)"); FMS ( 6,15, 7, 0, 0, "AMD (unknown type) (Carrizo/Bristol Ridge/Stoney Ridge/Toronto/Brown Falcon/Merlin Falcon/Prairie Falcon ST-A0)"); FMQ ( 6,15, 7, 0, Sa, "AMD A-Series (Carrizo/Bristol Ridge/Stoney Ridge)"); FMQ ( 6,15, 7, 0, Se, "AMD E-Series (Stoney Ridge)"); FMQ ( 6,15, 7, 0, Sg, "AMD G-Series (Brown Falcon/Prairie Falcon)"); FMQ ( 6,15, 7, 0, Sr, "AMD R-Series (Merlin Falcon)"); FM ( 6,15, 7, 0, "AMD (unknown type) (Carrizo/Bristol Ridge/Stoney Ridge/Toronto/Brown Falcon/Merlin Falcon/Prairie Falcon)"); F ( 6,15, "AMD (unknown model)"); FMS ( 7,15, 0, 0, 0, "AMD (unknown type) (Kabini/Temash/Kyoto KB-A0)"); // sandpile.org FMSQ( 7,15, 0, 0, 1, dA, "AMD Athlon (Kabini KB-A1)"); FMSQ( 7,15, 0, 0, 1, Sa, "AMD A-Series (Kabini/Temash KB-A1)"); FMSQ( 7,15, 0, 0, 1, Se, "AMD E-Series (Kabini KB-A1)"); FMSQ( 7,15, 0, 0, 1, Sg, "AMD G-Series (Kabini KB-A1)"); FMSQ( 7,15, 0, 0, 1, sO, "AMD Opteron X1100/X2100 Series (Kyoto KB-A1)"); FMS ( 7,15, 0, 0, 1, "AMD (unknown type) (Kabini/Temash/Kyoto KB-A1)"); FMQ ( 7,15, 0, 0, dA, "AMD Athlon (Kabini)"); FMQ ( 7,15, 0, 0, Sa, "AMD A-Series (Kabini/Temash)"); FMQ ( 7,15, 0, 0, Se, "AMD E-Series (Kabini)"); FMQ ( 7,15, 0, 0, Sg, "AMD G-Series (Kabini)"); FMQ ( 7,15, 0, 0, sO, "AMD Opteron X1100/X2100 Series (Kyoto)"); FM ( 7,15, 0, 0, "AMD (unknown type) (Kabini/Temash/Kyoto)"); FM ( 7,15, 2, 6, "AMD (unknown type) (Cato)"); // undocumented; instlatx64 sample; engr sample? // sandpile.org mentions (7,15),(0,4) Jaguar-esque "BV" cores // (with stepping 1 = A1), but I have no idea of any such code name. // The AMD docs (53072) omit the CPUID entirely. But if this sticks to the // recent AMD pattern, these must be (7,15),(3,0). FMSQ( 7,15, 3, 0, 1, Sa, "AMD A-Series (Beema ML-A1)"); FMSQ( 7,15, 3, 0, 1, Se, "AMD E-Series (Beema ML-A1)"); FMSQ( 7,15, 3, 0, 1, Sg, "AMD G-Series (Steppe Eagle/Crowned Eagle ML-A1)"); // undocumented; instlatx64 sample FMSQ( 7,15, 3, 0, 1, Ta, "AMD A-Series Micro (Mullins ML-A1)"); FMSQ( 7,15, 3, 0, 1, Te, "AMD E-Series Micro (Mullins ML-A1)"); FMS ( 7,15, 3, 0, 1, "AMD (unknown type) (Beema/Mullins ML-A1)"); FMQ ( 7,15, 3, 0, Sa, "AMD A-Series (Beema)"); FMQ ( 7,15, 3, 0, Se, "AMD E-Series (Beema)"); FMQ ( 7,15, 3, 0, Sg, "AMD E-Series (Steppe Eagle/Crowned Eagle)"); FMQ ( 7,15, 3, 0, Ta, "AMD A-Series Micro (Mullins)"); FMQ ( 7,15, 3, 0, Te, "AMD E-Series Micro (Mullins)"); FM ( 7,15, 3, 0, "AMD (unknown type) (Beema/Mullins/Steppe Eagle/Crowned Eagle)"); // sandpile.org mentions (7,15),(6,0) Puma-esque "NL" cores // (with stepping 1 = A1), but I have no idea of any such code name. F ( 7,15, "AMD (unknown model)"); // In Zen-based CPUs, the model uses only the extended model and the // high-order bit of the model. Meanwhile, the stepping name (revision) is // determinable mechanically from the low order 3 bits of the model, // converted to alphabetic characters, 0=A, 1=B, 2=C, etc.; and the stepping // number. This is mentioned in each of individual the Processor Programming // Reference manuals under CPUID_FN00000001_EAX. // PPR 54945 FMmQ( 8,15, 0, 0, EE, "AMD EPYC (1st Gen) (Snowy Owl ZP-%c%u)"); FMmQ( 8,15, 0, 0, sE, "AMD EPYC (1st Gen) (Naples ZP-%c%u)"); FMmQ( 8,15, 0, 0, dH, "AMD Ryzen Threadripper 1000 (Whitehaven %c%u)"); FMmQ( 8,15, 0, 0, dR, "AMD Ryzen 1000 (Summit Ridge ZP-%c%u)"); FMm ( 8,15, 0, 0, "AMD (unknown type) (Summit Ridge/Naples ZP-%c%u)"); FMmQ( 8,15, 0, 8, dH, "AMD Ryzen Threadripper 2000 (Colfax %c%u)"); FMmQ( 8,15, 0, 8, dR, "AMD Ryzen 2000 (Pinnacle Ridge PiR-%c%u)"); FMm ( 8,15, 0, 8, "AMD Ryzen (unknown type) (Pinnacle Ridge PiR-%c%u)"); // PPR 55449 FMmQ( 8,15, 1, 0, dA, "AMD Athlon Pro 200 (Raven Ridge RV-%c%u)"); FMmQ( 8,15, 1, 0, VR, "AMD Ryzen Embedded V1000 (Great Horned Owl RV-%c%u)"); // only instlatx64 example FMmQ( 8,15, 1, 0, RR, "AMD Ryzen Embedded R1000 (Banded Kestrel RV-%c%u)"); // guess based on Great Horned Owl pattern FMmQ( 8,15, 1, 0, AR, "AMD Ryzen 2000 (Raven Ridge RV-%c%u)"); // found only on en.wikichip.org & instlatx64 examples FMm ( 8,15, 1, 0, "AMD Ryzen (unknown type) (Raven Ridge/Great Horned Owl/Banded Kestrel RV-%c%u)"); // found only on en.wikichip.org & instlatx64 examples // PPR 55570, PPR 55449 FMmQ( 8,15, 1, 8, dA, "AMD Athlon Pro 300 (Picasso %c%u)"); FMmQ( 8,15, 1, 8, AR, "AMD Ryzen 3000 (Picasso %c%u)"); FMm ( 8,15, 1, 8, "AMD (unknown type) (Picasso %c%u)"); // PPR 55772 FMmQ( 8,15, 2, 0, dR, "AMD Ryzen 1000 (Dali %c%u)"); FMm ( 8,15, 2, 0, "AMD (unknown type) (Dali %c%u)"); // PPR 56323, PPR 55803 FMmQ( 8,15, 3, 0, dR, "AMD Ryzen Threadripper 3000 (Castle Peak %c%u)"); FMmQ( 8,15, 3, 0, sE, "AMD EPYC (2nd Gen) (Rome %c%u)"); FMm ( 8,15, 3, 0, "AMD (unknown type) (Castle Peak/Rome %c%u)"); FM ( 8,15, 4, 7, "AMD 4700S Desktop Kit (Cardinal)"); // undocumented; instlatx64 sample; engr sample? FM ( 8,15, 5, 0, "AMD DG02SRTBP4MFA (Fenghuang 15FF)"); // internal model, only instlatx64 example // PPR 55922 FMmQ( 8,15, 6, 0, ER, "AMD Ryzen Embedded V2000 (Grey Hawk %c%u)"); // found only on en.wikichip.org FMmQ( 8,15, 6, 0, dR, "AMD Ryzen 4000 (Renoir %c%u)"); FMm ( 8,15, 6, 0, "AMD (unknown type) (Renoir/Grey Hawk %c%u)"); FMm ( 8,15, 6, 8, "AMD Ryzen 5000 (Lucienne %c%u)"); // undocumented, but instlatx64 samples FMm ( 8,15, 7, 0, "AMD Ryzen 3000 (Matisse %c%u)"); // PPR 56176, samples from Steven Noonan FM ( 8,15, 8, 4, "AMD 4800S Desktop Kit (ProjectX)"); // undocumented, but sample via instlatx64 FMm ( 8,15, 9, 0, "AMD Custom APU: Steam Deck (Van Gogh %c%u)"); // undocumented, but samples from instlatx64 FMm ( 8,15, 9, 8, "AMD Custom APU: Magic Leap Demophon (Mero %c%u)"); // undocumented, but (engr?) sample via instlatx64 from @zimogorets FMm ( 8,15, 10, 0, "AMD Ryzen 7000 (Mendocino %c%u)"); // PPR 57243 F ( 8,15, "AMD (unknown model)"); FMm (10,15, 0, 0, "AMD EPYC (3rd Gen) (Milan %c%u)"); // 56683 FMm (10,15, 0, 8, "AMD Ryzen Threadripper 5000 (Chagall %c%u)"); // undocumented, but sample from CCRT FMm (10,15, 1, 0, "AMD EPYC (4th Gen) (Genoa %c%u)"); // PPR 57095, PPR 55901 FMm (10,15, 1, 8, "AMD Ryzen Threadripper 7000 (Storm Peak %c%u)"); // undocumented, but samples from instlatx64 FMm (10,15, 2, 0, "AMD Ryzen 5000 (Vermeer %c%u)"); // PPR 56214 FMm (10,15, 3, 0, "AMD Ryzen (Badami %c%u)"); // undocumented, but (engr?) sample via instlatx64 from @patrickschur_ FMm (10,15, 4, 0, "AMD Ryzen 6000/7000 (Rembrandt %c%u)"); // undocumented, but instlatx64 samples FMm (10,15, 5, 0, "AMD Ryzen 5000 (Cezanne/Barcelo %c%u)"); // PPR 56569 FMm (10,15, 6, 0, "AMD Ryzen 7000 (Raphael %c%u)"); // PPR 56713 FMm (10,15, 7, 0, "AMD Ryzen 7000/8000 (Phoenix/Hawk Point %c%u)"); // PPR 57019, instlatx64 sample of Ryzen 7 8845HS, which AMD also says is Hawk Point FM (10,15, 7,12, "AMD Ryzen (Hawk Point %c%u)"); // sample via instlatx64 from geekbench.com (special case only for model 12?) FMm (10,15, 7, 8, "AMD Ryzen (Phoenix 2 %c%u)"); // Coreboot* FMm (10,15, 8, 0, "AMD Instinct MI300C"); // undocumented, but LKML: https://lkml.org/lkml/2023/7/21/835 from AMD's Yazen Ghannam FMm (10,15, 9, 0, "AMD Instinct MI300A"); // undocumented, but LKML: https://lkml.org/lkml/2023/7/21/835 from AMD's Yazen Ghannam FMm (10,15, 10, 0, "AMD EPYC (4th Gen) (Bergamo/Siena %c%u)"); // PPR 57228 F (10,15, "AMD (unknown model)"); FMm (11,15, 0, 0, "AMD EPYC (5th Gen) (Turin %c%u)"); // PPR 57238 FMm (11,15, 0, 8, "AMD EPYC (5th Gen) (Turin %c%u)"); // PPR 57238 FMm (11,15, 1, 0, "AMD EPYC (5th Gen) (Sorano %c%u)"); // undocumented, but LLVM patch from AMD's Ganesh Gopalasubramanian FMm (11,15, 1, 8, "AMD EPYC (5th Gen) (Sorano %c%u)"); // undocumented, but LLVM patch from AMD's Ganesh Gopalasubramanian // Are all these Strix Point's Ryzen AI 300 CPU's? // I suspect the latter ones are not. FMm (11,15, 2, 0, "AMD Ryzen AI 300 (Strix Point %c%u)"); // undocumented, but LLVM patch from AMD's Ganesh Gopalasubramanian FMm (11,15, 2, 8, "AMD Ryzen AI 300 (Strix Point %c%u)"); // undocumented, but LLVM patch from AMD's Ganesh Gopalasubramanian FMm (11,15, 3, 0, "AMD Ryzen (Strix Point %c%u)"); // undocumented, but LLVM patch from AMD's Ganesh Gopalasubramanian FMm (11,15, 3, 8, "AMD Ryzen (Strix Point %c%u)"); // undocumented, but LLVM patch from AMD's Ganesh Gopalasubramanian FMm (11,15, 4, 0, "AMD Ryzen 9000 (Granite Ridge %c%u)"); // PPR 57896 FMm (11,15, 4, 8, "AMD Ryzen 9000 (Granite Ridge %c%u)"); // undocumented, but LLVM patch from AMD's Ganesh Gopalasubramanian FMm (11,15, 5, 0, "AMD EPYC (unknown type) (Venice %c%u)"); // undocumented, but LLVM patch from AMD's Ganesh Gopalasubramanian FMm (11,15, 5, 8, "AMD EPYC (unknown type) (Venice %c%u)"); // undocumented, but LLVM patch from AMD's Ganesh Gopalasubramanian FMm (11,15, 6, 0, "AMD Ryzen (Krackan Point %c%u)"); // undocumented, but LLVM patch from AMD's Ganesh Gopalasubramanian FMm (11,15, 6, 8, "AMD Ryzen (Krackan Point %c%u)"); // undocumented, but LLVM patch from AMD's Ganesh Gopalasubramanian FMm (11,15, 7, 0, "AMD Ryzen (Strix Halo %c%u)"); // undocumented, but LLVM patch from AMD's Ganesh Gopalasubramanian FMm (11,15, 7, 8, "AMD Ryzen (Strix Halo %c%u)"); // undocumented, but LLVM patch from AMD's Ganesh Gopalasubramanian F (11,15, "AMD (unknown model)"); DEFAULT ("unknown"); const char* brand_pre; const char* brand_post; char proc[96]; decode_amd_model(stash, &brand_pre, &brand_post, proc); if (proc[0] != '\0') { static char buffer[1024+1+96]; sprintf(buffer, "%s %s", result, proc); return buffer; } return result; } #undef ACT #define ACT(str) (result = (str)) static cstring decode_synth_cyrix(unsigned int val, const code_stash_t* stash) { cstring result = NULL; START; FM (0,4, 0,4, "Cyrix MediaGX/GXi"); FM (0,4, 0,9, "Cyrix 5x86"); F (0,4, "Cyrix 5x86 (unknown model)"); FM (0,5, 0,2, "Cyrix M1 6x86"); FM (0,5, 0,3, "Cyrix M1 6x86"); // M1-6 FMQ(0,5, 0,4, cm, "Cyrix MediaGXm"); FM (0,5, 0,4, "NSC Geode GX1/GXLV/GXm"); F (0,5, "Cyrix M1 / MediaGX / NSC Geode (unknown model)"); FM (0,6, 0,0, "Cyrix M2 6x86MX"); FM (0,6, 0,5, "Cyrix M2"); F (0,6, "Cyrix M2 (unknown model)"); DEFAULT ("unknown"); return result; } static cstring decode_synth_via(unsigned int val, const code_stash_t* stash) { cstring result = NULL; START; FM (0, 5, 0, 4, "VIA WinChip (C6)"); FM (0, 5, 0, 8, "VIA WinChip 2 (C6-2)"); FM (0, 5, 0, 9, "VIA WinChip 3 (C6-3)"); FM (0, 6, 0, 6, "VIA C3 (Samuel C5A)"); FMS (0, 6, 0, 7, 0, "VIA C3 (Samuel 2 C5B) / Eden ESP 4000/5000/6000, .15um"); FMS (0, 6, 0, 7, 1, "VIA C3 (Samuel 2 C5B) / Eden ESP 4000/5000/6000, .15um"); FMS (0, 6, 0, 7, 2, "VIA C3 (Samuel 2 C5B) / Eden ESP 4000/5000/6000, .15um"); FMS (0, 6, 0, 7, 3, "VIA C3 (Samuel 2 C5B) / Eden ESP 4000/5000/6000, .15um"); FMS (0, 6, 0, 7, 4, "VIA C3 (Samuel 2 C5B) / Eden ESP 4000/5000/6000, .15um"); FMS (0, 6, 0, 7, 5, "VIA C3 (Samuel 2 C5B) / Eden ESP 4000/5000/6000, .15um"); FMS (0, 6, 0, 7, 6, "VIA C3 (Samuel 2 C5B) / Eden ESP 4000/5000/6000, .15um"); FMS (0, 6, 0, 7, 7, "VIA C3 (Samuel 2 C5B) / Eden ESP 4000/5000/6000, .15um"); FM (0, 6, 0, 7, "VIA C3 (Ezra C5C), .13um"); FM (0, 6, 0, 8, "VIA C3 (Ezra-T C5N)"); FMS (0, 6, 0, 9, 0, "VIA C3 / Eden ESP 7000/8000/10000 (Nehemiah C5XL)"); FMS (0, 6, 0, 9, 1, "VIA C3 / Eden ESP 7000/8000/10000 (Nehemiah C5XL)"); FMS (0, 6, 0, 9, 2, "VIA C3 / Eden ESP 7000/8000/10000 (Nehemiah C5XL)"); FMS (0, 6, 0, 9, 3, "VIA C3 / Eden ESP 7000/8000/10000 (Nehemiah C5XL)"); FMS (0, 6, 0, 9, 4, "VIA C3 / Eden ESP 7000/8000/10000 (Nehemiah C5XL)"); FMS (0, 6, 0, 9, 5, "VIA C3 / Eden ESP 7000/8000/10000 (Nehemiah C5XL)"); FMS (0, 6, 0, 9, 6, "VIA C3 / Eden ESP 7000/8000/10000 (Nehemiah C5XL)"); FMS (0, 6, 0, 9, 7, "VIA C3 / Eden ESP 7000/8000/10000 (Nehemiah C5XL)"); FM (0, 6, 0, 9, "VIA C3 / C3-M / Eden-N (Antaur C5P)"); // VIA unpublished BIOS Guide for C7-D. FM (0, 6, 0,10, "VIA C7 / C7-M / C7-D / Eden (Esther C5J Model A)"); // VIA unpublished BIOS Guide for C7-D. // Brand string can be used to differentiate model D CPUs. FMQ (0, 6, 0,13, vM, "VIA C7-M (Esther C5J Model D)"); FMQ (0, 6, 0,13, vD, "VIA C7-D (Esther C5J Model D)"); FMQ (0, 6, 0,13, v7, "VIA C7 (Esther C5J Model D)"); FMQ (0, 6, 0,13, vE, "VIA Eden (Esther C5J Model D)"); FM (0, 6, 0,13, "VIA (unknown type) (Esther C5J Model D)"); // VIA unpublished BIOS Guide for Nano, Eden (for steppings 3-14, other than // Zhaoxin). // // Steppings 0-2 for Isaiah come from this post by "redray", circa Apr 2013: // https://forum.osdev.org/viewtopic.php?f=1&t=26351 // It presents an excerpt from "VIA Nano Processor X2X4 BIOS Guide 2.47". // // Die size depends on core, but it's unclear which cores are which: // Isaiah = 65nm, 40nm // Isaiah II = 28nm // ZhangJiang (Zhaoxin) = 28nm ? FMS (0, 6, 0,15, 0, "VIA Nano 1000/2000 (Isaiah CNA A0)"); // redray; instlatx64 example FMS (0, 6, 0,15, 1, "VIA Nano 1000/2000 (Isaiah CNA A1)"); // redray; model numbers assumed because of bracketing between 0 & 3 FMS (0, 6, 0,15, 2, "VIA Nano 1000/2000 (Isaiah CNA A2)"); // redray; model numbers assumed because of bracketing between 0 & 3 FMS (0, 6, 0,15, 3, "VIA Nano 1000/2000 (Isaiah CNA A3)"); FMS (0, 6, 0,15, 8, "VIA Nano 3000 (Isaiah CNB A1)"); FMS (0, 6, 0,15, 10, "VIA Nano 3000 (Isaiah CNC A2)"); FMS (0, 6, 0,15, 12, "VIA Nano X2 4000 / QuadCore 4000 (Isaiah CNQ A1)"); FMS (0, 6, 0,15, 13, "VIA Nano X2 4000 / QuadCore 4000 (Isaiah CNQ A2)"); FMSQ(0, 6, 0,15, 14, vZ, "Zhaoxin KaiXian/Kaisheng ZX-C/ZX-C+"); FMS (0, 6, 0,15, 14, "VIA Eden X4 4000 (Isaiah CNR)"); FM (0, 6, 0,15, "VIA Nano / Eden (unknown type) (Isaiah)"); FMQ (0, 6, 1, 9, vZ, "Zhaoxin KaiXian/Kaisheng ZX-C/ZX-C+"); // Google_cpu_features* // Lots of examples with stepping 1, but no indication of the stepping name. FMS (0, 6, 4, 7, 1, "VIA (CHA)"); FM (0, 6, 4, 7, "VIA (CHA)"); F (0, 6, "VIA C3 / C3-M / C7 / C7-M / Eden / Eden ESP 7000/8000/10000 / Nano (unknown model)"); FM (0, 7, 0,11, "Zhaoxin KaiXian KX-5000 / Kaisheng KH-20000"); // geekbench.com example FM (0, 7, 1,11, "Zhaoxin KaiXian KX-5000 / Kaisheng KH-20000"); // Google_cpu_features* FMQ (0, 7, 3,11, vZ, "Zhaoxin KaiXian KX-6000 / Kaisheng KH-30000"); // instlatx64 example with CentaurHauls vendor! FMQ (0, 7, 5,11, vZ, "Zhaoxin Kaisheng KH-40000"); // Google_cpu_features* DEFAULT ("unknown"); return result; } static cstring decode_synth_umc(unsigned int val) { cstring result = NULL; START; FM (0,4, 0,1, "UMC U5D (486DX)"); FMS(0,4, 0,2, 3, "UMC U5S (486SX)"); FM (0,4, 0,2, "UMC U5S (486SX) (unknown stepping)"); DEFAULT ("unknown"); return result; } static cstring decode_synth_nexgen(unsigned int val) { cstring result = NULL; START; FMS(0,5, 0,0, 4, "NexGen P100"); FMS(0,5, 0,0, 6, "NexGen P120 (E2/C0)"); DEFAULT ("unknown"); return result; } static cstring decode_synth_rise(unsigned int val) { cstring result = NULL; START; FM (0,5, 0,0, "Rise mP6 iDragon, .25u"); FM (0,5, 0,2, "Rise mP6 iDragon, .18u"); FM (0,5, 0,8, "Rise mP6 iDragon II, .25u"); FM (0,5, 0,9, "Rise mP6 iDragon II, .18u"); DEFAULT ("unknown"); return result; } static cstring decode_synth_transmeta(unsigned int val, const code_stash_t* stash) { cstring result = NULL; /* TODO: Add code-based detail for Transmeta Crusoe TM5700/TM5900 */ /* TODO: Add code-based detail for Transmeta Efficeon */ START; FMSQ(0, 5, 0,4, 2, t2, "Transmeta Crusoe TM3200"); FMS (0, 5, 0,4, 2, "Transmeta Crusoe TM3x00 (unknown model)"); FMSQ(0, 5, 0,4, 3, t4, "Transmeta Crusoe TM5400"); FMSQ(0, 5, 0,4, 3, t5, "Transmeta Crusoe TM5500 / Crusoe SE TM55E"); FMSQ(0, 5, 0,4, 3, t6, "Transmeta Crusoe TM5600"); FMSQ(0, 5, 0,4, 3, t8, "Transmeta Crusoe TM5800 / Crusoe SE TM58E"); FMS (0, 5, 0,4, 3, "Transmeta Crusoe TM5x00 (unknown model)"); FM (0, 5, 0,4, "Transmeta Crusoe"); F (0, 5, "Transmeta Crusoe (unknown model)"); FM (0,15, 0,2, "Transmeta Efficeon TM8x00"); FM (0,15, 0,3, "Transmeta Efficeon TM8x00"); F (0,15, "Transmeta Efficeon (unknown model)"); DEFAULT ("unknown"); return result; } static cstring decode_synth_sis(unsigned int val) { cstring result = NULL; START; FM (0, 5, 0, 0, "SiS 55x"); DEFAULT ("unknown"); return result; } static cstring decode_synth_nsc(unsigned int val) { cstring result = NULL; START; FM (0, 5, 0, 4, "NSC Geode GX1/GXLV/GXm"); FM (0, 5, 0, 5, "NSC Geode GX2"); FM (0, 5, 0,10, "NSC Geode LX"); // sandpile.org F (0, 5, "NSC Geode (unknown model)"); DEFAULT ("unknown"); return result; } static cstring decode_synth_vortex(unsigned int val) { cstring result = NULL; START; FM (0, 5, 0, 2, "Vortex86DX"); FM (0, 5, 0, 8, "Vortex86MX"); FM (0, 6, 0, 0, "Vortex86EX2"); // undocumented; /proc/cpuinfo seen in wild FM (0, 6, 0, 1, "Vortex86DX3"); // undocumented; only instlatx64 example DEFAULT ("unknown"); return result; } static cstring decode_synth_rdc(unsigned int val) { cstring result = NULL; START; FM (0, 5, 0, 8, "RDC IAD 100"); DEFAULT ("unknown"); return result; } static cstring decode_synth_hygon(unsigned int val) { cstring result = NULL; START; FMS (9,15, 0, 0, 1, "Hygon Dhyana (A1)"); FMS (9,15, 0, 0, 2, "Hygon Dhyana (A2)"); FMS (9,15, 0, 1, 1, "Hygon Dhyana (B1)"); FMS (9,15, 0, 2, 2, "Hygon Dhyana (C2)"); DEFAULT ("unknown"); return result; } static cstring decode_synth_zhaoxin(unsigned int val) { cstring result = NULL; START; FM (0, 7, 1,11, "Zhaoxin KaiXian KX-5000 / Kaisheng KH-20000 (WuDaoKou)"); FM (0, 7, 1,15, "Zhaoxin KaiXian ZX-D (WuDaoKou)"); // geekbench.com example (steppings 12 & 14) FM (0, 7, 3,11, "Zhaoxin KaiXian KX-6000 / Kaisheng KH-30000 (LuJiaZui)"); // /proc/cpuinfo screenshot: KX-6840@3000MHz (stepping 0) DEFAULT ("unknown"); return result; } static cstring decode_x_synth_amd(unsigned int val) { cstring result; START; FM (0, 5, 0, 0, "AMD SSA5 (PR75, PR90, PR100)"); FM (0, 5, 0, 1, "AMD 5k86 (PR120, PR133)"); FM (0, 5, 0, 2, "AMD 5k86 (PR166)"); FM (0, 5, 0, 3, "AMD 5k86 (PR200)"); F (0, 5, "AMD 5k86 (unknown model)"); FM (0, 6, 0, 6, "AMD K6, .30um"); FM (0, 6, 0, 7, "AMD K6 (Little Foot), .25um"); FMS (0, 6, 0, 8, 0, "AMD K6-2 (Chomper A)"); FMS (0, 6, 0, 8, 12, "AMD K6-2 (Chomper A)"); FM (0, 6, 0, 8, "AMD K6-2 (Chomper)"); FMS (0, 6, 0, 9, 1, "AMD K6-III (Sharptooth B)"); FM (0, 6, 0, 9, "AMD K6-III (Sharptooth)"); FM (0, 6, 0,13, "AMD K6-2+, K6-III+"); F (0, 6, "AMD K6 (unknown model)"); FM (0, 7, 0, 1, "AMD Athlon, .25um"); FM (0, 7, 0, 2, "AMD Athlon (K75 / Pluto / Orion), .18um"); FMS (0, 7, 0, 3, 0, "AMD Duron / mobile Duron (Spitfire A0)"); FMS (0, 7, 0, 3, 1, "AMD Duron / mobile Duron (Spitfire A2)"); FM (0, 7, 0, 3, "AMD Duron / mobile Duron (Spitfire)"); FMS (0, 7, 0, 4, 2, "AMD Athlon (Thunderbird A4-A7)"); FMS (0, 7, 0, 4, 4, "AMD Athlon (Thunderbird A9)"); FM (0, 7, 0, 4, "AMD Athlon (Thunderbird)"); FMS (0, 7, 0, 6, 0, "AMD Athlon / Athlon MP mobile Athlon 4 / mobile Duron (Palomino A0)"); FMS (0, 7, 0, 6, 1, "AMD Athlon / Athlon MP / Duron / mobile Athlon / mobile Duron (Palomino A2)"); FMS (0, 7, 0, 6, 2, "AMD Athlon MP / Athlon XP / Duron / Duron MP / mobile Athlon / mobile Duron (Palomino A5)"); FM (0, 7, 0, 6, "AMD Athlon / Athlon MP / Athlon XP / Duron / Duron MP / mobile Athlon / mobile Duron (Palomino)"); FMS (0, 7, 0, 7, 0, "AMD Duron / Duron MP / mobile Duron (Morgan A0)"); FMS (0, 7, 0, 7, 1, "AMD Duron / Duron MP / mobile Duron (Morgan A1)"); FM (0, 7, 0, 7, "AMD Duron / Duron MP / mobile Duron (Morgan)"); FMS (0, 7, 0, 8, 0, "AMD Athlon XP / Athlon MP / Sempron / Duron / Duron MP (Thoroughbred A0)"); FMS (0, 7, 0, 8, 1, "AMD Athlon XP / Athlon MP / Sempron / Duron / Duron MP (Thoroughbred B0)"); FM (0, 7, 0, 8, "AMD Athlon XP / Athlon MP / Sempron / Duron / Duron MP (Thoroughbred)"); FMS (0, 7, 0,10, 0, "AMD Athlon XP / Athlon MP / Sempron / mobile Athlon XP-M / mobile Athlon XP-M (LV) (Barton A2)"); FM (0, 7, 0,10, "AMD Athlon XP / Athlon MP / Sempron / mobile Athlon XP-M / mobile Athlon XP-M (LV) (Barton)"); F (0, 7, "AMD Athlon XP / Athlon MP / Sempron / Duron / Duron MP / mobile Athlon / mobile Athlon XP-M / mobile Athlon XP-M (LV) / mobile Duron (unknown model)"); FALLBACK({ result = append_uarch(decode_synth_amd(val, NULL), val, VENDOR_AMD, NULL); }) return result; } static void print_x_synth_amd(unsigned int val) { ccstring synth = decode_x_synth_amd(val); printf(" (simple synth) = "); if (synth != NULL) { printf("%s", synth); } printf("\n"); } static cstring decode_x_synth_hygon(unsigned int val) { cstring result; START; FALLBACK({ result = append_uarch(decode_synth_hygon(val), val, VENDOR_HYGON, NULL); }) return result; } static void print_x_synth_hygon(unsigned int val) { ccstring synth = decode_x_synth_hygon(val); printf(" (simple synth) = "); if (synth != NULL) { printf("%s", synth); } printf("\n"); } static cstring decode_x_synth_via(unsigned int val) { cstring result; START; FM (0,6, 0,6, "VIA C3 (WinChip C5A)"); FM (0,6, 0,6, "VIA C3 (WinChip C5A)"); FMS(0,6, 0,7, 0, "VIA C3 (WinChip C5B)"); FMS(0,6, 0,7, 1, "VIA C3 (WinChip C5B)"); FMS(0,6, 0,7, 2, "VIA C3 (WinChip C5B)"); FMS(0,6, 0,7, 3, "VIA C3 (WinChip C5B)"); FMS(0,6, 0,7, 4, "VIA C3 (WinChip C5B)"); FMS(0,6, 0,7, 5, "VIA C3 (WinChip C5B)"); FMS(0,6, 0,7, 6, "VIA C3 (WinChip C5B)"); FMS(0,6, 0,7, 7, "VIA C3 (WinChip C5B)"); FM (0,6, 0,7, "VIA C3 (WinChip C5C)"); FM (0,6, 0,8, "VIA C3 (WinChip C5N)"); FM (0,6, 0,9, "VIA C3 (WinChip C5XL)"); F (0,6, "VIA C3 (unknown model)"); DEFAULT ("unknown"); return append_uarch(result, val, VENDOR_VIA, NULL); } static void print_x_synth_via(unsigned int val) { ccstring synth = decode_x_synth_via(val); printf(" (simple synth) = "); if (synth != NULL) { printf("%s", synth); } printf("\n"); } #undef ACT static cstring decode_synth(unsigned int val_eax, vendor_t vendor, const code_stash_t* stash) { cstring synth = NULL; switch (vendor) { case VENDOR_INTEL: synth = decode_synth_intel(val_eax, stash); break; case VENDOR_AMD: synth = decode_synth_amd(val_eax, stash); break; case VENDOR_CYRIX: synth = decode_synth_cyrix(val_eax, stash); break; case VENDOR_VIA: synth = decode_synth_via(val_eax, stash); break; case VENDOR_TRANSMETA: synth = decode_synth_transmeta(val_eax, stash); break; case VENDOR_UMC: synth = decode_synth_umc(val_eax); break; case VENDOR_NEXGEN: synth = decode_synth_nexgen(val_eax); break; case VENDOR_RISE: synth = decode_synth_rise(val_eax); break; case VENDOR_SIS: synth = decode_synth_sis(val_eax); break; case VENDOR_NSC: synth = decode_synth_nsc(val_eax); break; case VENDOR_VORTEX: synth = decode_synth_vortex(val_eax); break; case VENDOR_RDC: synth = decode_synth_rdc(val_eax); break; case VENDOR_HYGON: synth = decode_synth_hygon(val_eax); break; case VENDOR_ZHAOXIN: synth = decode_synth_zhaoxin(val_eax); break; case VENDOR_UNKNOWN: /* DO NOTHING */ break; } return append_uarch(synth, val_eax, vendor, stash); } static void print_synth_simple(unsigned int val_eax, vendor_t vendor) { ccstring synth = decode_synth(val_eax, vendor, NULL); if (synth != NULL) { printf(" (simple synth) = %s\n", synth); } } static void print_synth(const code_stash_t* stash) { ccstring synth = decode_synth(stash->val_1_eax, stash->vendor, stash); if (synth != NULL) { printf(" (synth) = %s\n", synth); } } #define GET_ApicIdCoreIdSize(val_80000008_ecx) \ (BIT_EXTRACT_LE((val_80000008_ecx), 0, 4)) #define GET_LogicalProcessorCount(val_1_ebx) \ (BIT_EXTRACT_LE((val_1_ebx), 16, 24)) #define IS_HTT(val_1_edx) \ (BIT_EXTRACT_LE((val_1_edx), 28, 29)) #define IS_CmpLegacy(val_80000001_ecx) \ (BIT_EXTRACT_LE((val_80000001_ecx), 1, 2)) #define GET_NC_INTEL(val_4_eax) \ (BIT_EXTRACT_LE((val_4_eax), 26, 32)) #define GET_NC_AMD(val_80000008_ecx) \ (BIT_EXTRACT_LE((val_80000008_ecx), 0, 8)) #define GET_X2APIC_PROCESSORS(val_b_ebx) \ (BIT_EXTRACT_LE((val_b_ebx), 0, 16)) #define GET_V2_TOPO_LEVEL(val_1f_ecx) \ (BIT_EXTRACT_LE((val_1f_ecx), 8, 16)) #define GET_V2_TOPO_PROCESSORS(val_1f_ebx) \ (BIT_EXTRACT_LE((val_1f_ebx), 0, 16)) #define GET_CoresPerComputeUnit_AMD(val_8000001e_ebx) \ (BIT_EXTRACT_LE((val_8000001e_ebx), 8, 16)) static void decode_mp_synth(code_stash_t* stash) { switch (stash->vendor) { case VENDOR_INTEL: /* ** Logic derived from information in: ** Detecting Multi-Core Processor Topology in an IA-32 Platform ** by Khang Nguyen and Shihjong Kuo ** and: ** Intel 64 Architecture Processor Topology Enumeration (Whitepaper) ** by Shih Kuo ** Extension to the 0x1f leaf was obvious. */ if (stash->saw_1f) { stash->mp.method = "Intel leaf 0x1f"; unsigned int last_count = 1; unsigned int sub; for (sub = 0; sub < LENGTH(stash->val_1f_ecx); sub++) { unsigned int level = GET_V2_TOPO_LEVEL(stash->val_1f_ecx[sub]); if (level < LENGTH(v2TopoToCotopo)) { unsigned ct = v2TopoToCotopo[level]; if (ct != Invalid) { unsigned int count = GET_V2_TOPO_PROCESSORS(stash->val_1f_ebx[sub]); stash->mp.count[ct] = count / last_count; last_count = count; } } } } else if (stash->saw_b) { unsigned int ht = GET_X2APIC_PROCESSORS(stash->val_b_ebx[0]); unsigned int tc = GET_X2APIC_PROCESSORS(stash->val_b_ebx[1]); stash->mp.method = "Intel leaf 0xb"; if (ht == 0) { ht = 1; } stash->mp.count[Core] = tc / ht; stash->mp.count[Smt] = ht; } else if (stash->saw_4) { unsigned int tc = GET_LogicalProcessorCount(stash->val_1_ebx); unsigned int c; if ((stash->val_4_eax & 0x1f) != 0) { c = GET_NC_INTEL(stash->val_4_eax) + 1; stash->mp.method = "Intel leaf 1/4"; } else { /* Workaround for older 'cpuid -r' dumps with incomplete 4 data */ c = MAX(tc / 2, 1); stash->mp.method = "Intel leaf 1/4 (zero fallback)"; } stash->mp.count[Core] = c; stash->mp.count[Smt] = tc / c; } else { stash->mp.method = "Intel leaf 1"; stash->mp.count[Core] = 1; if (IS_HTT(stash->val_1_edx)) { unsigned int tc = GET_LogicalProcessorCount(stash->val_1_ebx); stash->mp.count[Smt] = (tc >= 2 ? tc : 2); } else { stash->mp.count[Smt] = 1; } } break; case VENDOR_AMD: case VENDOR_HYGON: if (stash->saw_b) { /* ** Logic by analogy to Intel */ unsigned int ht = GET_X2APIC_PROCESSORS(stash->val_b_ebx[0]); unsigned int tc = GET_X2APIC_PROCESSORS(stash->val_b_ebx[1]); stash->mp.method = (stash->vendor == VENDOR_AMD ? "AMD leaf 0xb" : "Hygon leaf 0xb"); if (ht == 0) { ht = 1; } stash->mp.count[Core] = tc / ht; stash->mp.count[Smt] = ht; } else if (IS_HTT(stash->val_1_edx)) { /* ** Logic from: ** AMD CPUID Specification (25481 Rev. 2.16), ** 3. LogicalProcessorCount, CmpLegacy, HTT, and NC ** AMD CPUID Specification (25481 Rev. 2.28), ** 3. Multiple Core Calculation ** ** For Families 10h-16h, the CU (CMT "compute unit") logic was a ** logical extension. ** ** For Families 17h and later, terminology changed to reflect that ** the Family 10h-16h cores had been sharing resources significantly: ** Family 10h-16h => Family 17h ** ---------------------------- ** CU => core ** core => thread ** And leaf 0x8000001e/ebx is used for smt_count, because 1/ebx is ** unreliable. */ unsigned int size = (GET_ApicIdCoreIdSize(stash->val_80000008_ecx) != 0 ? GET_ApicIdCoreIdSize(stash->val_80000008_ecx) : 32); unsigned int mask = RIGHTMASK(size); unsigned int core_count = (GET_NC_AMD(stash->val_80000008_ecx) & mask) + 1; unsigned int total_count = GET_LogicalProcessorCount(stash->val_1_ebx); unsigned int smt_count = total_count / core_count; unsigned int cu_count = 1; if (GET_CoresPerComputeUnit_AMD(stash->val_8000001e_ebx) != 0) { if (Synth_Family(stash->val_80000001_eax) > 0x16) { unsigned int threads_per_core = GET_CoresPerComputeUnit_AMD(stash->val_8000001e_ebx) + 1; smt_count = threads_per_core; core_count /= threads_per_core; } else { unsigned int cores_per_cu = GET_CoresPerComputeUnit_AMD(stash->val_8000001e_ebx) + 1; cu_count = (core_count / cores_per_cu); core_count = cores_per_cu; } } stash->mp.method = (stash->vendor == VENDOR_AMD ? "AMD leaf 1/0x8000008" : "Hygon leaf 1/0x80000008"); stash->mp.count[Core] = core_count; stash->mp.count[Smt] = smt_count; stash->mp.count[Cu] = cu_count; } else { stash->mp.method = (stash->vendor == VENDOR_AMD ? "AMD leaf 1" : "Hygon leaf 1"); stash->mp.count[Core] = 1; stash->mp.count[Smt] = 1; } break; default: if (!IS_HTT(stash->val_1_edx)) { stash->mp.method = "Generic leaf 1 no multi-threading"; stash->mp.count[Core] = 1; stash->mp.count[Smt] = 1; } break; } } static void print_mp_synth(const struct mp* mp) { static ccstring prefix[NumCotopos] = { "hyper-threaded (t", "multi-core (c", "multi-compute-unit (cu", "multi-module (m", "multi-tile (t", "multi-die (d", "multi-die-group (dg", "multi-package (p" }; printf(" (multi-processing synth) = "); if (mp->method == NULL) { printf("?"); } else { boolean first = TRUE; for (unsigned int ct = NumCotopos-1;; ct--) { if (mp->count[ct] > 1) { if (first) { first = FALSE; } else { printf(", "); } printf("%s=%u)", prefix[ct], mp->count[ct]); } if (ct == 0) break; } if (first) { printf("none"); } } printf("\n"); printf(" (multi-processing method) = %s\n", mp->method); } static int bits_needed(unsigned long v) { #ifdef USE_BUILTIN_CLZL return v <= 1 ? 0 : (8 * sizeof(long) - __builtin_clzl(v-1)); #else if (v == 0) return 0; int result; #if defined(__x86_64) && !defined(__ILP32__) asm("movq %[v],%%rax;" "movq $0,%%rcx;" "movl $0,%[result];" "decq %%rax;" "bsr %%ax,%%cx;" "jz 1f;" "incq %%rcx;" "movl %%ecx,%[result];" "1:" : [result] "=rm" (result) : [v] "irm" (v) : "eax", "ecx"); #else asm("movl %[v],%%eax;" "movl $0,%%ecx;" "movl $0,%[result];" "decl %%eax;" "bsr %%ax,%%cx;" "jz 1f;" "incl %%ecx;" "movl %%ecx,%[result];" "1:" : [result] "=rm" (result) : [v] "irm" (v) : "eax", "ecx"); #endif return result; #endif } #define GET_X2APIC_WIDTH(val_b_eax) \ (BIT_EXTRACT_LE((val_b_eax), 0, 5)) #define GET_V2_TOPO_WIDTH(val_1f_eax) \ (BIT_EXTRACT_LE((val_1f_eax), 0, 5)) static void print_apic_synth (code_stash_t* stash) { typedef struct { ccstring abbrev; boolean alwaysShowWidth; boolean alwaysShowId; } CotopoDisplay; static CotopoDisplay dsp[NumCotopos] = { { "SMT", TRUE, TRUE }, { "CORE", TRUE, TRUE }, { "CU", FALSE, FALSE }, { "MOD", FALSE, FALSE }, { "TILE", FALSE, FALSE }, { "DIE", FALSE, FALSE }, { "DIEGRP", FALSE, FALSE }, { "PKG", FALSE, TRUE } }; unsigned int widths[NumCotopos] = { 0, 0, 0, 0, 0, 0, 0, 0 }; unsigned int offsets[NumCotopos] = { 0, 0, 0, 0, 0, 0, 0, 0 }; unsigned int tails[NumCotopos] = { 0, 0, 0, 0, 0, 0, 0, 0 }; switch (stash->vendor) { case VENDOR_INTEL: /* ** Logic derived from information in: ** Detecting Multi-Core Processor Topology in an IA-32 Platform ** by Khang Nguyen and Shihjong Kuo ** and: ** Intel 64 Architecture Processor Topology Enumeration (Whitepaper) ** by Shih Kuo ** Extension to the 0x1f leaf was obvious. */ if (stash->saw_1f) { unsigned int last_width = 0; unsigned int sub; for (sub = 0; sub < LENGTH(stash->val_1f_ecx); sub++) { unsigned int level = GET_V2_TOPO_LEVEL(stash->val_1f_ecx[sub]); unsigned int width = GET_V2_TOPO_WIDTH(stash->val_1f_eax[sub]); if (level < LENGTH(v2TopoToCotopo)) { unsigned ct = v2TopoToCotopo[level]; if (ct != Invalid) { widths[ct] = width - last_width; } } last_width = width; } } else if (stash->saw_b) { widths[Smt] = GET_X2APIC_WIDTH(stash->val_b_eax[0]); widths[Core] = GET_X2APIC_WIDTH(stash->val_b_eax[1]) - widths[Smt]; } else if (stash->saw_4 && (stash->val_4_eax & 0x1f) != 0) { unsigned int core_count = GET_NC_INTEL(stash->val_4_eax) + 1; unsigned int smt_count = (GET_LogicalProcessorCount(stash->val_1_ebx) / core_count); widths[Smt] = bits_needed(smt_count); widths[Core] = bits_needed(core_count); } else { return; } break; case VENDOR_AMD: case VENDOR_HYGON: /* ** Logic deduced by analogy: As Intel's decode_mp_synth code is to AMD's ** decode_mp_synth code, so is Intel's APIC synth code to this. ** ** For Families 10h-16h, the CU (CMT "compute unit") logic was a ** logical extension. ** ** For Families 17h and later, terminology changed to reflect that ** the Family 10h-16h cores had been sharing resources significantly: ** Family 10h-16h => Family 17h ** ---------------------------- ** CU => core ** core => thread ** And leaf 0x8000001e/ebx is used for smt_count, because 1/ebx is ** unreliable. */ if (stash->saw_b) { widths[Smt] = GET_X2APIC_WIDTH(stash->val_b_eax[0]); widths[Core] = GET_X2APIC_WIDTH(stash->val_b_eax[1]) - widths[Smt]; } else if (IS_HTT(stash->val_1_edx) && GET_ApicIdCoreIdSize(stash->val_80000008_ecx) != 0) { unsigned int size = GET_ApicIdCoreIdSize(stash->val_80000008_ecx); unsigned int mask = RIGHTMASK(size); unsigned int core_count = (GET_NC_AMD(stash->val_80000008_ecx) & mask) + 1; unsigned int total_count = GET_LogicalProcessorCount(stash->val_1_ebx); unsigned int smt_count = total_count / core_count; unsigned int cu_count = 1; if (GET_CoresPerComputeUnit_AMD(stash->val_8000001e_ebx) != 0) { if (Synth_Family(stash->val_80000001_eax) > 0x16) { unsigned int threads_per_core = GET_CoresPerComputeUnit_AMD(stash->val_8000001e_ebx) + 1; smt_count = threads_per_core; core_count /= threads_per_core; } else { unsigned int cores_per_cu = GET_CoresPerComputeUnit_AMD(stash->val_8000001e_ebx) + 1; cu_count = (core_count / cores_per_cu); core_count = cores_per_cu; } } widths[Smt] = bits_needed(smt_count); widths[Core] = bits_needed(core_count); widths[Cu] = bits_needed(cu_count); } else { return; } break; default: return; } printf(" (APIC widths synth):"); for (unsigned int ct = NumCotopos-1;; ct--) { if (dsp[ct].alwaysShowWidth || widths[ct] != 0) { printf(" %s_width=%u", dsp[ct].abbrev, widths[ct]); } if (ct == 0) break; } printf("\n"); // Compute the offsets & tails so that the bit fields can be walked in // reverse order, outermost:Pkg to innermost:Smt. { unsigned int offset = 0; for (unsigned int ct = 0; ct < NumCotopos; ct++) { offsets[ct] = offset; tails[ct] = offset + widths[ct]; offset = tails[ct]; } // The highest level (Pkg) always is all of the remaining bits tails[NumCotopos-1] = 32; } unsigned int apic_id; if (stash->saw_8000001e && Synth_Family(stash->val_1_eax) != 0x15) { // The 0x8000001e/eax extended APIC ID appears to have unreliable values // in the Piledriver..Excavator timeframe. apic_id = stash->val_8000001e_eax; } else if (stash->saw_1f) { apic_id = stash->val_1f_edx; } else if (stash->saw_b) { apic_id = stash->val_b_edx; } else { apic_id = BIT_EXTRACT_LE(stash->val_1_ebx, 24, 32); } printf(" (APIC synth):"); for (unsigned int ct = NumCotopos-1;; ct--) { if (dsp[ct].alwaysShowId || widths[ct] != 0) { printf(" %s_ID=%u", dsp[ct].abbrev, BIT_EXTRACT_LE(apic_id, offsets[ct], tails[ct])); } if (ct == 0) break; } printf("\n"); } static void print_instr_synth_intel (code_stash_t* stash) { boolean mwait = (BIT_EXTRACT_LE(stash->val_1_ecx, 3, 4) || BIT_EXTRACT_LE(stash->val_7_1_edx, 23, 24)); printf(" (instruction supported synth):\n"); printf(" MWAIT = %s\n", bools[mwait]); } static void print_instr_synth_amd (code_stash_t* stash) { boolean cmpxchg8b = (BIT_EXTRACT_LE(stash->val_80000001_edx, 8, 9) || BIT_EXTRACT_LE(stash->val_1_edx, 8, 9)); boolean cond = (BIT_EXTRACT_LE(stash->val_80000001_edx, 15, 16) || BIT_EXTRACT_LE(stash->val_1_edx, 15, 16)); boolean prefetch = (BIT_EXTRACT_LE(stash->val_80000001_ecx, 8, 9) || BIT_EXTRACT_LE(stash->val_80000001_edx, 29, 30) || BIT_EXTRACT_LE(stash->val_80000001_edx, 31, 32)); printf(" (instruction supported synth):\n"); printf(" CMPXCHG8B = %s\n", bools[cmpxchg8b]); printf(" conditional move/compare = %s\n", bools[cond]); printf(" PREFETCH/PREFETCHW = %s\n", bools[prefetch]); } static void print_instr_synth (code_stash_t* stash) { switch (stash->vendor) { case VENDOR_INTEL: print_instr_synth_intel(stash); break; case VENDOR_AMD: case VENDOR_HYGON: print_instr_synth_amd(stash); break; default: break; } } static void do_final (const print_opts_t* opts, code_stash_t* stash) { if (!opts->raw) { print_instr_synth(stash); decode_mp_synth(stash); print_mp_synth(&stash->mp); print_apic_synth(stash); decode_override_brand(stash); print_override_brand(stash); decode_brand_id_stash(stash); decode_brand_stash(stash); if (opts->debug) { debug_queries(stash); } print_uarch(stash); print_synth(stash); } } static void print_1_eax(unsigned int value, vendor_t vendor, const print_opts_t* opts) { static ccstring processor[1<<2] = { "primary processor (0)", "Intel OverDrive (1)", "secondary processor (2)" }; static named_item names[] = { { "processor type" , 12, 13, processor }, { "family" , 8, 11, NIL_IMAGES }, { "model" , 4, 7, NIL_IMAGES }, { "stepping id" , 0, 3, NIL_IMAGES }, { "extended family" , 20, 27, NIL_IMAGES }, { "extended model" , 16, 19, NIL_IMAGES }, }; printf(" version information (1/eax):\n"); print_names(value, names, LENGTH(names), /* max_len => */ 15); unsigned int synth_family = Synth_Family(value); unsigned int synth_model = Synth_Model(value); printf(" (family synth) = 0x%x (%u)\n", synth_family, synth_family); printf(" (model synth) = 0x%x (%u)\n", synth_model, synth_model); if (opts->simple) { print_synth_simple(value, vendor); } } #define B(b,...) \ else if ( MaskB(val_ebx) == ShftB(b)) \ ACT(__VA_ARGS__) #define FMB(xf,f,xm,m,b,...) \ else if ( MaskFM(val_eax) == ShftFM(xf,f,xm,m) \ && MaskB(val_ebx) == ShftB(b)) \ ACT(__VA_ARGS__) #define FMSB(xf,f,xm,m,s,b,...) \ else if ( MaskFMS(val_eax) == ShftFMS(xf,f,xm,m,s) \ && MaskB(val_ebx) == ShftB(b)) \ ACT(__VA_ARGS__) #define ACT(str) (printf(str)) static void print_brand(unsigned int val_eax, unsigned int val_ebx) { printf(" brand id = 0x%02x (%u): ", MaskB(val_ebx), MaskB(val_ebx)); START; B ( 1, "Intel Celeron, .18um"); B ( 2, "Intel Pentium III, .18um"); FMSB(0, 6, 0,11, 1, 3, "Intel Celeron, .13um"); B ( 3, "Intel Pentium III Xeon, .18um"); B ( 4, "Intel Pentium III, .13um"); B ( 6, "Mobile Intel Pentium III, .13um"); B ( 7, "Mobile Intel Celeron, .13um"); FMB (0,15, 0, 0, 8, "Intel Pentium 4, .18um"); FMSB(0,15, 0, 1, 0, 8, "Intel Pentium 4, .18um"); FMSB(0,15, 0, 1, 1, 8, "Intel Pentium 4, .18um"); FMSB(0,15, 0, 1, 2, 8, "Intel Pentium 4, .18um"); B ( 8, "Mobile Intel Celeron 4, .13um"); B ( 9, "Intel Pentium 4, .13um"); B ( 10, "Intel Celeron 4, .18um"); FMB (0,15, 0, 0, 11, "Intel Xeon MP, .18um"); FMSB(0,15, 0, 1, 0, 11, "Intel Xeon MP, .18um"); FMSB(0,15, 0, 1, 1, 11, "Intel Xeon MP, .18um"); FMSB(0,15, 0, 1, 2, 11, "Intel Xeon MP, .18um"); B ( 11, "Intel Xeon, .13um"); B ( 12, "Intel Xeon MP, .13um"); FMB (0,15, 0, 0, 14, "Intel Xeon, .18um"); FMSB(0,15, 0, 1, 0, 14, "Intel Xeon, .18um"); FMSB(0,15, 0, 1, 1, 14, "Intel Xeon, .18um"); FMSB(0,15, 0, 1, 2, 14, "Intel Xeon, .18um"); FMB (0,15, 0, 2, 14, "Mobile Intel Pentium 4 Processor-M"); B ( 14, "Mobile Intel Xeon, .13um"); FMB (0,15, 0, 2, 15, "Mobile Intel Pentium 4 Processor-M"); B ( 15, "Mobile Intel Celeron 4"); B ( 17, "Mobile Genuine Intel"); B ( 18, "Intel Celeron M"); B ( 19, "Mobile Intel Celeron"); B ( 20, "Intel Celeron"); B ( 21, "Mobile Genuine Intel"); B ( 22, "Intel Pentium M, .13um"); B ( 23, "Mobile Intel Celeron"); DEFAULT ("unknown"); printf("\n"); } #undef ACT static void print_1_ebx(unsigned int value) { static named_item names[] = { { "process local APIC physical ID" , 24, 31, NIL_IMAGES }, { "maximum IDs for CPUs in pkg" , 16, 23, NIL_IMAGES }, { "CLFLUSH line size" , 8, 15, NIL_IMAGES }, { "brand index" , 0, 7, NIL_IMAGES }, }; printf(" miscellaneous (1/ebx):\n"); print_names(value, names, LENGTH(names), /* max_len => */ 0); } static void print_1_ecx(unsigned int value) { static named_item names[] = { { "PNI/SSE3: Prescott New Instructions" , 0, 0, bools }, { "PCLMULDQ instruction" , 1, 1, bools }, { "DTES64: 64-bit debug store" , 2, 2, bools }, { "MONITOR/MWAIT" , 3, 3, bools }, { "CPL-qualified debug store" , 4, 4, bools }, { "VMX: virtual machine extensions" , 5, 5, bools }, { "SMX: safer mode extensions" , 6, 6, bools }, { "Enhanced Intel SpeedStep Technology" , 7, 7, bools }, { "TM2: thermal monitor 2" , 8, 8, bools }, { "SSSE3 extensions" , 9, 9, bools }, { "context ID: adaptive or shared L1 data" , 10, 10, bools }, { "SDBG: IA32_DEBUG_INTERFACE" , 11, 11, bools }, { "FMA instruction" , 12, 12, bools }, { "CMPXCHG16B instruction" , 13, 13, bools }, { "xTPR disable" , 14, 14, bools }, { "PDCM: perfmon and debug" , 15, 15, bools }, { "PCID: process context identifiers" , 17, 17, bools }, { "DCA: direct cache access" , 18, 18, bools }, { "SSE4.1 extensions" , 19, 19, bools }, { "SSE4.2 extensions" , 20, 20, bools }, { "x2APIC: extended xAPIC support" , 21, 21, bools }, { "MOVBE instruction" , 22, 22, bools }, { "POPCNT instruction" , 23, 23, bools }, { "time stamp counter deadline" , 24, 24, bools }, { "AES instruction" , 25, 25, bools }, { "XSAVE/XSTOR states" , 26, 26, bools }, { "OS-enabled XSAVE/XSTOR" , 27, 27, bools }, { "AVX: advanced vector extensions" , 28, 28, bools }, { "F16C half-precision convert instruction" , 29, 29, bools }, { "RDRAND instruction" , 30, 30, bools }, { "hypervisor guest status" , 31, 31, bools }, }; printf(" feature information (1/ecx):\n"); print_names(value, names, LENGTH(names), /* max_len => */ 0); } static void print_1_edx(unsigned int value) { static named_item names[] = { { "x87 FPU on chip" , 0, 0, bools }, { "VME: virtual-8086 mode enhancement" , 1, 1, bools }, { "DE: debugging extensions" , 2, 2, bools }, { "PSE: page size extensions" , 3, 3, bools }, { "TSC: time stamp counter" , 4, 4, bools }, { "RDMSR and WRMSR support" , 5, 5, bools }, { "PAE: physical address extensions" , 6, 6, bools }, { "MCE: machine check exception" , 7, 7, bools }, { "CMPXCHG8B inst." , 8, 8, bools }, { "APIC on chip" , 9, 9, bools }, { "SYSENTER and SYSEXIT" , 11, 11, bools }, { "MTRR: memory type range registers" , 12, 12, bools }, { "PTE global bit" , 13, 13, bools }, { "MCA: machine check architecture" , 14, 14, bools }, { "CMOV: conditional move/compare instr" , 15, 15, bools }, { "PAT: page attribute table" , 16, 16, bools }, { "PSE-36: page size extension" , 17, 17, bools }, { "PSN: processor serial number" , 18, 18, bools }, { "CLFLUSH instruction" , 19, 19, bools }, { "DS: debug store" , 21, 21, bools }, { "ACPI: thermal monitor and clock ctrl" , 22, 22, bools }, { "MMX Technology" , 23, 23, bools }, { "FXSAVE/FXRSTOR" , 24, 24, bools }, { "SSE extensions" , 25, 25, bools }, { "SSE2 extensions" , 26, 26, bools }, { "SS: self snoop" , 27, 27, bools }, { "hyper-threading / multi-core supported" , 28, 28, bools }, { "TM: therm. monitor" , 29, 29, bools }, { "IA64" , 30, 30, bools }, { "PBE: pending break event" , 31, 31, bools }, }; printf(" feature information (1/edx):\n"); print_names(value, names, LENGTH(names), /* max_len => */ 0); } static void print_2_byte(unsigned char value, vendor_t vendor, unsigned int val_1_eax) { if (value == 0x00) return; printf(" 0x%02x: ", value); #define CONT "\n " if (vendor == VENDOR_CYRIX || vendor == VENDOR_VIA) { switch (value) { case 0x70: printf("TLB: 4K pages, 4-way, 32 entries\n"); return; case 0x74: printf("Cyrix-specific: ?\n"); return; case 0x77: printf("Cyrix-specific: ?\n"); return; case 0x80: printf("L1 cache: 16K, 4-way, 16 byte lines\n"); return; case 0x82: printf("Cyrix-specific: ?\n"); return; case 0x84: printf("L2 cache: 1M, 8-way, 32 byte lines\n"); return; } } switch (value) { case 0x01: printf("instruction TLB: 4K pages, 4-way, 32 entries"); break; case 0x02: printf("instruction TLB: 4M pages, 4-way, 2 entries"); break; case 0x03: printf("data TLB: 4K pages, 4-way, 64 entries"); break; case 0x04: printf("data TLB: 4M pages, 4-way, 8 entries"); break; case 0x05: printf("data TLB: 4M pages, 4-way, 32 entries"); break; case 0x06: printf("L1 instruction cache: 8K, 4-way, 32 byte lines"); break; case 0x08: printf("L1 instruction cache: 16K, 4-way, 32 byte lines"); break; case 0x09: printf("L1 instruction cache: 32K, 4-way, 64-byte lines"); break; case 0x0a: printf("L1 data cache: 8K, 2-way, 32 byte lines"); break; case 0x0b: printf("instruction TLB: 4M pages, 4-way, 4 entries"); break; case 0x0c: printf("L1 data cache: 16K, 4-way, 32 byte lines"); break; case 0x0d: printf("L1 data cache: 16K, 4-way, 64-byte lines"); break; case 0x0e: printf("L1 data cache: 24K, 6-way, 64 byte lines"); break; case 0x10: printf("L1 data cache: 16K, 4-way, 32 byte lines"); break; case 0x15: printf("L1 instruction cache: 16K, 4-way, 32 byte lines"); break; case 0x1d: printf("L2 cache: 128K, 2-way, 64 byte lines"); break; case 0x1a: printf("L2 cache: 96K, 6-way, 64 byte lines"); break; case 0x21: printf("L2 cache: 256K MLC, 8-way, 64 byte lines"); break; case 0x22: printf("L3 cache: 512K, 4-way, 64 byte lines"); break; case 0x23: printf("L3 cache: 1M, 8-way, 64 byte lines"); break; case 0x24: printf("L2 cache: 1M, 16-way, 64 byte lines"); break; case 0x25: printf("L3 cache: 2M, 8-way, 64 byte lines"); break; case 0x29: printf("L3 cache: 4M, 8-way, 64 byte lines"); break; case 0x2c: printf("L1 data cache: 32K, 8-way, 64 byte lines"); break; case 0x30: printf("L1 cache: 32K, 8-way, 64 byte lines"); break; case 0x39: printf("L2 cache: 128K, 4-way, sectored, 64 byte lines"); break; case 0x3a: printf("L2 cache: 192K, 6-way, sectored, 64 byte lines"); break; case 0x3b: printf("L2 cache: 128K, 2-way, sectored, 64 byte lines"); break; case 0x3c: printf("L2 cache: 256K, 4-way, sectored, 64 byte lines"); break; case 0x3d: printf("L2 cache: 384K, 6-way, sectored, 64 byte lines"); break; case 0x3e: printf("L2 cache: 512K, 4-way, sectored, 64 byte lines"); break; case 0x40: if (MaskF(val_1_eax) <= ShftXF(0) + ShftF(6)) { printf("No L2 cache"); } else { printf("No L3 cache"); } break; case 0x41: printf("L2 cache: 128K, 4-way, 32 byte lines"); break; case 0x42: printf("L2 cache: 256K, 4-way, 32 byte lines"); break; case 0x43: printf("L2 cache: 512K, 4-way, 32 byte lines"); break; case 0x44: printf("L2 cache: 1M, 4-way, 32 byte lines"); break; case 0x45: printf("L2 cache: 2M, 4-way, 32 byte lines"); break; case 0x46: printf("L3 cache: 4M, 4-way, 64 byte lines"); break; case 0x47: printf("L3 cache: 8M, 8-way, 64 byte lines"); break; case 0x48: printf("L2 cache: 3M, 12-way, 64 byte lines"); break; case 0x49: if (MaskFM(val_1_eax) == ShftFM(0,15, 0, 6)) { printf("L3 cache: 4M, 16-way, 64 byte lines"); } else { printf("L2 cache: 4M, 16-way, 64 byte lines"); } break; case 0x4a: printf("L3 cache: 6M, 12-way, 64 byte lines"); break; case 0x4b: printf("L3 cache: 8M, 16-way, 64 byte lines"); break; case 0x4c: printf("L3 cache: 12M, 12-way, 64 byte lines"); break; case 0x4d: printf("L3 cache: 16M, 16-way, 64 byte lines"); break; case 0x4e: printf("L2 cache: 6M, 24-way, 64 byte lines"); break; case 0x4f: printf("instruction TLB: 4K pages, 32 entries"); break; case 0x50: printf("instruction TLB: 4K & 2M/4M pages, 64 entries"); break; case 0x51: printf("instruction TLB: 4K & 2M/4M pages, 128 entries"); break; case 0x52: printf("instruction TLB: 4K & 2M/4M pages, 256 entries"); break; case 0x55: printf("instruction TLB: 2M/4M pages, fully, 7 entries"); break; case 0x56: printf("L1 data TLB: 4M pages, 4-way, 16 entries"); break; case 0x57: printf("L1 data TLB: 4K pages, 4-way, 16 entries"); break; case 0x59: printf("data TLB: 4K pages, 16 entries"); break; case 0x5a: printf("data TLB: 2M/4M pages, 4-way, 32 entries"); break; case 0x5b: printf("data TLB: 4K & 4M pages, 64 entries"); break; case 0x5c: printf("data TLB: 4K & 4M pages, 128 entries"); break; case 0x5d: printf("data TLB: 4K & 4M pages, 256 entries"); break; case 0x60: printf("L1 data cache: 16K, 8-way, 64 byte lines"); break; case 0x61: printf("instruction TLB: 4K pages, 48 entries"); break; case 0x63: printf("data TLB: 2M/4M pages, 4-way, 32 entries"); printf(CONT "data TLB: 1G pages, 4-way, 4 entries"); break; case 0x64: printf("data TLB: 4K pages, 4-way, 512 entries"); break; case 0x66: printf("L1 data cache: 8K, 4-way, 64 byte lines"); break; case 0x67: printf("L1 data cache: 16K, 4-way, 64 byte lines"); break; case 0x68: printf("L1 data cache: 32K, 4-way, 64 byte lines"); break; case 0x6a: printf("micro-data TLB: 4K pages, 8-way, 64 entries"); break; case 0x6b: printf("data TLB: 4K pages, 8-way, 256 entries"); break; case 0x6c: printf("data TLB: 2M/4M pages, 8-way, 128 entries"); break; case 0x6d: printf("data TLB: 1G pages, fully, 16 entries"); break; case 0x70: printf("Trace cache: 12K-uop, 8-way"); break; case 0x71: printf("Trace cache: 16K-uop, 8-way"); break; case 0x72: printf("Trace cache: 32K-uop, 8-way"); break; case 0x73: printf("Trace cache: 64K-uop, 8-way"); break; case 0x76: printf("instruction TLB: 2M/4M pages, fully, 8 entries"); break; case 0x77: printf("L1 instruction cache: 16K, 4-way, sectored," " 64 byte lines"); break; case 0x78: printf("L2 cache: 1M, 4-way, 64 byte lines"); break; case 0x79: printf("L2 cache: 128K, 8-way, sectored, 64 byte lines"); break; case 0x7a: printf("L2 cache: 256K, 8-way, sectored, 64 byte lines"); break; case 0x7b: printf("L2 cache: 512K, 8-way, sectored, 64 byte lines"); break; case 0x7c: printf("L2 cache: 1M, 8-way, sectored, 64 byte lines"); break; case 0x7d: printf("L2 cache: 2M, 8-way, 64 byte lines"); break; case 0x7e: printf("L2 cache: 256K, 8-way, sectored, 128 byte lines"); break; case 0x7f: printf("L2 cache: 512K, 2-way, 64 byte lines"); break; case 0x80: printf("L2 cache: 512K, 8-way, 64 byte lines"); break; case 0x81: printf("L2 cache: 128K, 8-way, 32 byte lines"); break; case 0x82: printf("L2 cache: 256K, 8-way, 32 byte lines"); break; case 0x83: printf("L2 cache: 512K, 8-way, 32 byte lines"); break; case 0x84: printf("L2 cache: 1M, 8-way, 32 byte lines"); break; case 0x85: printf("L2 cache: 2M, 8-way, 32 byte lines"); break; case 0x86: printf("L2 cache: 512K, 4-way, 64 byte lines"); break; case 0x87: printf("L2 cache: 1M, 8-way, 64 byte lines"); break; case 0x88: printf("L3 cache: 2M, 4-way, 64 byte lines"); break; case 0x89: printf("L3 cache: 4M, 4-way, 64 byte lines"); break; case 0x8a: printf("L3 cache: 8M, 4-way, 64 byte lines"); break; case 0x8d: printf("L3 cache: 3M, 12-way, 128 byte lines"); break; case 0x90: printf("instruction TLB: 4K-256M, fully, 64 entries"); break; case 0x96: printf("instruction TLB: 4K-256M, fully, 32 entries"); break; case 0x9b: printf("instruction TLB: 4K-256M, fully, 96 entries"); break; case 0xa0: printf("data TLB: 4K pages, fully, 32 entries"); break; case 0xb0: printf("instruction TLB: 4K, 4-way, 128 entries"); break; case 0xb1: printf("instruction TLB: 2M/4M, 4-way, 4/8 entries"); break; case 0xb2: printf("instruction TLB: 4K, 4-way, 64 entries"); break; case 0xb3: printf("data TLB: 4K pages, 4-way, 128 entries"); break; case 0xb4: printf("data TLB: 4K pages, 4-way, 256 entries"); break; case 0xb5: printf("instruction TLB: 4K, 8-way, 64 entries"); break; case 0xb6: printf("instruction TLB: 4K, 8-way, 128 entries"); break; case 0xba: printf("data TLB: 4K pages, 4-way, 64 entries"); break; case 0xc0: printf("data TLB: 4K & 4M pages, 4-way, 8 entries"); break; case 0xc1: printf("L2 TLB: 4K/2M pages, 8-way, 1024 entries"); break; case 0xc2: printf("data TLB: 4K & 2M pages, 4-way, 16 entries"); break; case 0xc3: printf("L2 TLB: 4K/2M pages, 6-way, 1536 entries"); break; case 0xc4: printf("data TLB: 2M/4M pages, 4-way, 32 entries"); break; case 0xca: printf("L2 TLB: 4K pages, 4-way, 512 entries"); break; case 0xd0: printf("L3 cache: 512K, 4-way, 64 byte lines"); break; case 0xd1: printf("L3 cache: 1M, 4-way, 64 byte lines"); break; case 0xd2: printf("L3 cache: 2M, 4-way, 64 byte lines"); break; case 0xd6: printf("L3 cache: 1M, 8-way, 64 byte lines"); break; case 0xd7: printf("L3 cache: 2M, 8-way, 64 byte lines"); break; case 0xd8: printf("L3 cache: 4M, 8-way, 64 byte lines"); break; case 0xdc: printf("L3 cache: 1.5M, 12-way, 64 byte lines"); break; case 0xdd: printf("L3 cache: 3M, 12-way, 64 byte lines"); break; case 0xde: printf("L3 cache: 6M, 12-way, 64 byte lines"); break; case 0xe2: printf("L3 cache: 2M, 16-way, 64 byte lines"); break; case 0xe3: printf("L3 cache: 4M, 16-way, 64 byte lines"); break; case 0xe4: printf("L3 cache: 8M, 16-way, 64 byte lines"); break; case 0xea: printf("L3 cache: 12M, 24-way, 64 byte lines"); break; case 0xeb: printf("L3 cache: 18M, 24-way, 64 byte lines"); break; case 0xec: printf("L3 cache: 24M, 24-way, 64 byte lines"); break; case 0xf0: printf("64 byte prefetching"); break; case 0xf1: printf("128 byte prefetching"); break; case 0xfe: printf("TLB data is in CPUID leaf 0x18"); break; case 0xff: printf("cache data is in CPUID leaf 4"); break; default: printf("unknown"); break; } /* ** WARNING: If you add values here, you probably need to update the code in ** stash_intel_cache, too. */ printf("\n"); #undef CONT } static void print_4_eax(unsigned int value) { static ccstring cache_type[1<<5] = { "no more caches (0)", "data cache (1)", "instruction cache (2)", "unified cache (3)" }; static named_item names[] = { { "cache type" , 0, 4, cache_type }, { "cache level" , 5, 7, NIL_IMAGES }, { "self-initializing cache level" , 8, 8, bools }, { "fully associative cache" , 9, 9, bools }, { "maximum IDs for CPUs sharing cache" , 14, 25, NIL_IMAGES }, { "maximum IDs for cores in pkg" , 26, 31, NIL_IMAGES }, }; print_names(value, names, LENGTH(names), /* max_len => */ 34); } static void print_4_ebx(unsigned int value) { static named_item names[] = { { "system coherency line size" , 0, 11, MINUS1_IMAGES }, { "physical line partitions" , 12, 21, MINUS1_IMAGES }, { "ways of associativity" , 22, 31, MINUS1_IMAGES }, }; print_names(value, names, LENGTH(names), /* max_len => */ 34); } static void print_4_ecx(unsigned int value) { static named_item names[] = { { "number of sets" , 0, 31, MINUS1_IMAGES }, }; print_names(value, names, LENGTH(names), /* max_len => */ 34); } static void print_4_edx(unsigned int value) { static named_item names[] = { { "WBINVD/INVD acts on lower caches" , 0, 0, bools }, { "inclusive to lower caches" , 1, 1, bools }, { "complex cache indexing" , 2, 2, bools }, }; print_names(value, names, LENGTH(names), /* max_len => */ 34); } static void print_4_synth(const unsigned int words[]) { unsigned int ways_assoc = BIT_EXTRACT_LE(words[WORD_EBX], 22, 32) + 1; unsigned int parts = BIT_EXTRACT_LE(words[WORD_EBX], 12, 22) + 1; unsigned int line_size = BIT_EXTRACT_LE(words[WORD_EBX], 0, 12) + 1; unsigned int sets = words[WORD_ECX] + 1; unsigned int size = (ways_assoc * parts * line_size * sets); printf(" (size synth) = %u", size); if (size > 1048576) { if ((size % 1048576) == 0) { printf(" (%u MB)", size / 1048576); } else { printf(" (%3.1f MB)", ((float)size) / 1048576.0); } } else if (size > 1024) { if ((size % 1024) == 0) { printf(" (%u KB)", size / 1024); } else { printf(" (%3.1f KB)", ((float)size) / 1024.0); } } printf("\n"); } static void print_5_eax(unsigned int value) { static named_item names[] = { { "smallest monitor-line size (bytes)" , 0, 15, NIL_IMAGES }, }; print_names(value, names, LENGTH(names), /* max_len => */ 40); } static void print_5_ebx(unsigned int value) { static named_item names[] = { { "largest monitor-line size (bytes)" , 0, 15, NIL_IMAGES }, }; print_names(value, names, LENGTH(names), /* max_len => */ 40); } static void print_5_ecx(unsigned int value) { static named_item names[] = { { "enum of Monitor-MWAIT exts supported" , 0, 0, bools }, { "supports intrs as break-event for MWAIT" , 1, 1, bools }, { "monitorless MWAIT supported" , 5, 5, bools }, }; print_names(value, names, LENGTH(names), /* max_len => */ 40); } static void print_5_edx(unsigned int value) { static named_item names[] = { { "number of C0 sub C-states using MWAIT" , 0, 3, NIL_IMAGES }, { "number of C1 sub C-states using MWAIT" , 4, 7, NIL_IMAGES }, { "number of C2 sub C-states using MWAIT" , 8, 11, NIL_IMAGES }, { "number of C3 sub C-states using MWAIT" , 12, 15, NIL_IMAGES }, { "number of C4 sub C-states using MWAIT" , 16, 19, NIL_IMAGES }, { "number of C5 sub C-states using MWAIT" , 20, 23, NIL_IMAGES }, { "number of C6 sub C-states using MWAIT" , 24, 27, NIL_IMAGES }, { "number of C7 sub C-states using MWAIT" , 28, 31, NIL_IMAGES }, }; print_names(value, names, LENGTH(names), /* max_len => */ 40); } static void print_6_eax(unsigned int value) { static named_item names[] = { { "digital thermometer" , 0, 0, bools }, { "Intel Turbo Boost Technology" , 1, 1, bools }, { "ARAT always running APIC timer" , 2, 2, bools }, { "PLN power limit notification" , 4, 4, bools }, { "ECMD extended clock modulation duty" , 5, 5, bools }, { "PTM package thermal management" , 6, 6, bools }, { "HWP base registers" , 7, 7, bools }, { "HWP notification" , 8, 8, bools }, { "HWP activity window" , 9, 9, bools }, { "HWP energy performance preference" , 10, 10, bools }, { "HWP package level request" , 11, 11, bools }, { "HDC base registers" , 13, 13, bools }, { "Intel Turbo Boost Max Technology 3.0" , 14, 14, bools }, { "HWP capabilities" , 15, 15, bools }, { "HWP PECI override" , 16, 16, bools }, { "flexible HWP" , 17, 17, bools }, { "IA32_HWP_REQUEST MSR fast access mode" , 18, 18, bools }, { "HW_FEEDBACK MSRs supported" , 19, 19, bools }, { "ignoring idle logical processor HWP req" , 20, 20, bools }, { "IA32_HWP_CTL MSR supported" , 22, 22, bools }, { "Thread Director" , 23, 23, bools }, { "IA32_HW_FEEDBACK_THREAD_CONFIG bit 25" , 24, 24, bools }, }; print_names(value, names, LENGTH(names), /* max_len => */ 39); } static void print_6_ebx(unsigned int value) { static named_item names[] = { { "digital thermometer thresholds" , 0, 3, NIL_IMAGES }, }; print_names(value, names, LENGTH(names), /* max_len => */ 39); } static void print_6_ecx(unsigned int value) { static named_item names[] = { { "hardware coordination feedback" , 0, 0, bools }, { "ACNT2 available" , 1, 1, bools }, { "performance-energy bias capability" , 3, 3, bools }, { "number of enh hardware feedback classes" , 8, 15, NIL_IMAGES }, }; print_names(value, names, LENGTH(names), /* max_len => */ 39); } static void print_6_edx(unsigned int value) { static named_item names[] = { { "performance capability reporting" , 0, 0, bools }, { "energy efficiency capability reporting" , 1, 1, bools }, { "size of feedback struct (4KB pages)" , 8, 11, MINUS1_IMAGES }, { "index of CPU's row in feedback struct" , 16, 31, NIL_IMAGES }, }; print_names(value, names, LENGTH(names), /* max_len => */ 39); } static void print_7_0_ebx(unsigned int value) { static named_item names[] = { { "FSGSBASE instructions" , 0, 0, bools }, { "IA32_TSC_ADJUST MSR supported" , 1, 1, bools }, { "SGX: Software Guard Extensions supported", 2, 2, bools }, { "BMI1 instructions" , 3, 3, bools }, { "HLE hardware lock elision" , 4, 4, bools }, { "AVX2: advanced vector extensions 2" , 5, 5, bools }, { "FDP_EXCPTN_ONLY" , 6, 6, bools }, { "SMEP supervisor mode exec protection" , 7, 7, bools }, { "BMI2 instructions" , 8, 8, bools }, { "enhanced REP MOVSB/STOSB" , 9, 9, bools }, { "INVPCID instruction" , 10, 10, bools }, { "RTM: restricted transactional memory" , 11, 11, bools }, { "RDT-CMT/PQoS cache monitoring" , 12, 12, bools }, { "deprecated FPU CS/DS" , 13, 13, bools }, { "MPX: intel memory protection extensions" , 14, 14, bools }, { "RDT-CAT/PQE cache allocation" , 15, 15, bools }, { "AVX512F: AVX-512 foundation instructions", 16, 16, bools }, { "AVX512DQ: double & quadword instructions", 17, 17, bools }, { "RDSEED instruction" , 18, 18, bools }, { "ADX instructions" , 19, 19, bools }, { "SMAP: supervisor mode access prevention" , 20, 20, bools }, { "AVX512IFMA: integer fused multiply add" , 21, 21, bools }, // NOTE: AMD Appendix E.3.6 claims bit 22 is RDPID support, but this // almost certainly is an error. Section 3 RDPID description says it // is 7/0/ecx, as does Table 3-1. And this is consistent with Intel // architectures. { "PCOMMIT instruction" , 22, 22, bools }, { "CLFLUSHOPT instruction" , 23, 23, bools }, { "CLWB instruction" , 24, 24, bools }, { "Intel processor trace" , 25, 25, bools }, { "AVX512PF: prefetch instructions" , 26, 26, bools }, { "AVX512ER: exponent & reciprocal instrs" , 27, 27, bools }, { "AVX512CD: conflict detection instrs" , 28, 28, bools }, { "SHA instructions" , 29, 29, bools }, { "AVX512BW: byte & word instructions" , 30, 30, bools }, { "AVX512VL: vector length" , 31, 31, bools }, }; print_names(value, names, LENGTH(names), /* max_len => */ 40); } static void print_7_0_ecx(unsigned int value) { static named_item names[] = { { "PREFETCHWT1" , 0, 0, bools }, { "AVX512VBMI: vector byte manipulation" , 1, 1, bools }, { "UMIP: user-mode instruction prevention" , 2, 2, bools }, { "PKU protection keys for user-mode" , 3, 3, bools }, { "OSPKE CR4.PKE and RDPKRU/WRPKRU" , 4, 4, bools }, { "WAITPKG instructions" , 5, 5, bools }, { "AVX512_VBMI2: byte VPCOMPRESS, VPEXPAND" , 6, 6, bools }, { "CET_SS: CET shadow stack" , 7, 7, bools }, { "GFNI: Galois Field New Instructions" , 8, 8, bools }, { "VAES instructions" , 9, 9, bools }, { "VPCLMULQDQ instruction" , 10, 10, bools }, { "AVX512_VNNI: neural network instructions", 11, 11, bools }, { "AVX512_BITALG: bit count/shiffle" , 12, 12, bools }, { "TME: Total Memory Encryption" , 13, 13, bools }, { "AVX512: VPOPCNTDQ instruction" , 14, 14, bools }, { "LA57: 57-bit addrs & 5-level paging" , 16, 16, bools }, { "BNDLDX/BNDSTX MAWAU value in 64-bit mode", 17, 21, NIL_IMAGES }, { "RDPID: read processor ID supported" , 22, 22, bools }, { "KL: key locker" , 23, 23, bools }, { "bus lock detection" , 24, 24, bools }, { "CLDEMOTE supports cache line demote" , 25, 25, bools }, { "MOVDIRI instruction" , 27, 27, bools }, { "MOVDIR64B instruction" , 28, 28, bools }, { "ENQCMD instruction" , 29, 29, bools }, { "SGX_LC: SGX launch config supported" , 30, 30, bools }, { "PKS: supervisor protection keys" , 31, 31, bools }, }; print_names(value, names, LENGTH(names), /* max_len => */ 40); } static void print_7_0_edx(unsigned int value) { static named_item names[] = { { "SGX-KEYS: SGX attestation services" , 1, 1, bools }, { "AVX512_4VNNIW: neural network instrs" , 2, 2, bools }, { "AVX512_4FMAPS: multiply acc single prec" , 3, 3, bools }, { "fast short REP MOV" , 4, 4, bools }, { "UINTR: user interrupts" , 5, 5, bools }, { "AVX512_VP2INTERSECT: intersect mask regs", 8, 8, bools }, { "IA32_MCU_OPT_CTRL SRBDS mitigation MSR" , 9, 9, bools }, { "VERW MD_CLEAR microcode support" , 10, 10, bools }, { "RTM transaction always aborts" , 11, 11, bools }, { "IA32_TSX_FORCE_ABORT MSR" , 13, 13, bools }, { "SERIALIZE instruction" , 14, 14, bools }, { "hybrid part" , 15, 15, bools }, { "TSXLDTRK: TSX suspend load addr tracking", 16, 16, bools }, { "PCONFIG instruction" , 18, 18, bools }, { "LBR: architectural last branch records" , 19, 19, bools }, { "CET_IBT: CET indirect branch tracking" , 20, 20, bools }, { "AMX-BF16: tile bfloat16 support" , 22, 22, bools }, { "AVX512_FP16: fp16 support" , 23, 23, bools }, { "AMX-TILE: tile architecture support" , 24, 24, bools }, { "AMX-INT8: tile 8-bit integer support" , 25, 25, bools }, { "IBRS/IBPB: indirect branch restrictions" , 26, 26, bools }, { "STIBP: 1 thr indirect branch predictor" , 27, 27, bools }, { "L1D_FLUSH: IA32_FLUSH_CMD MSR" , 28, 28, bools }, { "IA32_ARCH_CAPABILITIES MSR" , 29, 29, bools }, { "IA32_CORE_CAPABILITIES MSR" , 30, 30, bools }, { "SSBD: speculative store bypass disable" , 31, 31, bools }, }; print_names(value, names, LENGTH(names), /* max_len => */ 40); } static void print_7_1_eax(unsigned int value) { static named_item names[] = { { "SHA512 instructions" , 0, 0, bools }, { "SM3 instructions" , 1, 1, bools }, { "SM4 instructions" , 2, 2, bools }, { "RAO-INT atomic instructions" , 3, 3, bools }, { "AVX-VNNI: AVX VNNI neural network instrs", 4, 4, bools }, { "AVX512_BF16: bfloat16 instructions" , 5, 5, bools }, { "LASS: linear address space separation" , 6, 6, bools }, { "CMPccXADD instructions" , 7, 7, bools }, { "ArchPerfmonExt leaf 0x23 is valid" , 8, 8, bools }, { "fast zero-length REP MOVSB" , 10, 10, bools }, { "fast short REP STOSB" , 11, 11, bools }, { "fast short REP CMPSB, REP SCASB" , 12, 12, bools }, { "FRED transitions & MSRs" , 17, 17, bools }, { "LKGS instruction" , 18, 18, bools }, { "WRMSRNS instruction" , 19, 19, bools }, { "NMI-source reporting" , 20, 20, bools }, { "AMX-FP16: FP16 tile operations" , 21, 21, bools }, { "HRESET: history reset support" , 22, 22, bools }, { "AVX-IFMA: integer fused multiply add" , 23, 23, bools }, { "LAM: linear address masking" , 26, 26, bools }, { "RDMSRLIST, WRMSRLIST instructions" , 27, 27, bools }, { "INVD prevention after BIOS done" , 30, 30, bools }, { "MOVRS instructions" , 31, 31, bools }, }; print_names(value, names, LENGTH(names), /* max_len => */ 40); } static void print_7_1_ebx(unsigned int value) { static named_item names[] = { { "IA32_PPIN & IA32_PPIN_CTL MSRs supported", 0, 0, bools }, { "PBNDKB instruction" , 1, 1, bools }, { "IA32_MISC_ENABLE cannot limit CPUID max" , 3, 3, bools }, }; print_names(value, names, LENGTH(names), /* max_len => */ 40); } static void print_7_1_ecx(unsigned int value) { static named_item names[] = { { "RDMSR/WRMSRNS immediates supported" , 5, 5, bools }, }; print_names(value, names, LENGTH(names), /* max_len => */ 40); } static void print_7_1_edx(unsigned int value) { static named_item names[] = { { "AVX-VNNI-INT8 instructions" , 4, 4, bools }, { "AVX-NE-CONVERT instructions" , 5, 5, bools }, { "AMX-COMPLEX instructions" , 8, 8, bools }, { "AVX-VNNI-INT16 instructions" , 10, 10, bools }, { "user-timer events" , 13, 13, bools }, { "PREFETCHIT0, PREFETCHIT1 instructions" , 14, 14, bools }, { "URDMSR, UWRMSR instructions" , 15, 15, bools }, { "UIRET flexibly updates UIF" , 17, 17, bools }, { "CET_SSS: shadow stacks w/o page faults" , 18, 18, bools }, { "AVX10 instructions" , 19, 19, bools }, { "APX advanced performance extensions" , 21, 21, bools }, { "MWAIT instruction" , 23, 23, bools }, }; print_names(value, names, LENGTH(names), /* max_len => */ 40); } static void print_7_2_edx(unsigned int value) { static named_item names[] = { { "PSFD: fast store forwarding pred disable", 0, 0, bools }, { "IPRED_CTRL: IBP disable" , 1, 1, bools }, { "RRSBA_CTRL: IBP bottomless RSB disable" , 2, 2, bools }, { "DDPD_U: data dep prefetcher disable" , 3, 3, bools }, { "BHI_CTRL: IBP BHB-focused disable" , 4, 4, bools }, { "MCDT_NO: MCDT mitigation not needed" , 5, 5, bools }, { "UC-lock disable" , 6, 6, bools }, { "MONITOR perf unaffected by tbl overflow" , 7, 7, bools }, }; print_names(value, names, LENGTH(names), /* max_len => */ 40); } static void print_a_eax(unsigned int value) { static named_item names[] = { { "version ID" , 0, 7, NIL_IMAGES }, { "number of counters per logical processor", 8, 15, NIL_IMAGES }, { "bit width of counter" , 16, 23, NIL_IMAGES }, { "length of EBX bit vector" , 24, 31, NIL_IMAGES }, }; print_names(value, names, LENGTH(names), /* max_len => */ 40); } static void print_a_ebx(unsigned int value, unsigned int val_eax) { // Bits >= EAX[31:24] are ignored and assumed to be not available value |= ~RIGHTMASK(BIT_EXTRACT_LE(val_eax, 24, 32)); static ccstring notavails[] = { "available", "not available" }; static named_item names[] = { { "core cycle event" , 0, 0, notavails }, { "instruction retired event" , 1, 1, notavails }, { "reference cycles event" , 2, 2, notavails }, { "last-level cache ref event" , 3, 3, notavails }, { "last-level cache miss event" , 4, 4, notavails }, { "branch inst retired event" , 5, 5, notavails }, { "branch mispred retired event" , 6, 6, notavails }, { "topdown slots event" , 7, 7, notavails }, { "topdown backend bound" , 8, 8, notavails }, { "topdown bad speculation" , 9, 9, notavails }, { "topdown frontend bound" , 10, 10, notavails }, { "topdown retiring" , 11, 11, notavails }, { "LBR inserts" , 12, 12, notavails }, }; print_names(value, names, LENGTH(names), /* max_len => */ 40); } static void print_a_ecx(unsigned int value) { unsigned int bit; for (bit = 0; bit < sizeof(value)*8; bit++) { unsigned int field = BIT_EXTRACT_LE(value, bit, bit+1); printf(" fixed counter %2u supported = %s\n", bit, bools[field]); } } static void print_a_edx(unsigned int value) { static named_item names[] = { { "number of contiguous fixed counters" , 0, 4, NIL_IMAGES }, { "bit width of fixed counters" , 5, 12, NIL_IMAGES }, { "anythread deprecation" , 15, 15, bools }, }; print_names(value, names, LENGTH(names), /* max_len => */ 40); } static void print_b_1f_eax(unsigned int value) { static named_item names[] = { { "bit width of level & previous levels" , 0, 4, NIL_IMAGES }, }; print_names(value, names, LENGTH(names), /* max_len => */ 37); } static void print_b_1f_ebx(unsigned int value) { static named_item names[] = { { "number of logical processors at level" , 0, 15, NIL_IMAGES }, }; print_names(value, names, LENGTH(names), /* max_len => */ 37); } static void print_b_1f_ecx(unsigned int value) { // If more levels are added here, be sure to check: // V2_TOPO_NUM // val_1f_{eax,ebx,ecx} (in code_stash_t) // NIL_STASH // v2TopotoCotopo // Cotopo static ccstring level_type[1<<8] = { "invalid (0)", "thread (1)", "core (2)", "module (3)", "tile (4)", "die (5)", "die group (6)" }; static named_item names[] = { { "level number" , 0, 7, NIL_IMAGES }, { "level type" , 8, 15, level_type }, }; print_names(value, names, LENGTH(names), /* max_len => */ 37); } static void print_d_0_eax(unsigned int value) { // State component bitmaps in general are described in 325462: Intel 64 and // IA-32 Architectures Software Developer's Manual Combined Volumes: 1, 2A, // 2B, 2C, 3A, 3B, and 3C, Volume 1: Basic Architecture, section 13.1: // XSAVE-Supported Features and State-Component Bitmaps. This leaf describes // which of the bits are actually supported by the hardware, and is described // better in 13.2: Enumeration of CPU Support for XSAVE Instructions and // XSAVE-Supported Features. // // These align with the supported features[] in print_d_n() for values > 1. // // See also print_12_1_ecx(). static named_item names[] = { { " x87 state" , 0, 0, bools }, { " SSE state" , 1, 1, bools }, { " AVX state" , 2, 2, bools }, { " MPX BNDREGS" , 3, 3, bools }, { " MPX BNDCSR" , 4, 4, bools }, { " AVX-512 opmask" , 5, 5, bools }, { " AVX-512 ZMM_Hi256" , 6, 6, bools }, { " AVX-512 Hi16_ZMM" , 7, 7, bools }, { " PKRU state" , 9, 9, bools }, { " XTILECFG state" , 17, 17, bools }, { " XTILEDATA state" , 18, 18, bools }, }; print_names(value, names, LENGTH(names), /* max_len => */ 39); } static void print_d_0_edx(unsigned int value UNUSED) { // Upper 32 bits of XCR0: Currently all bits reserved. // See also print_12_1_edx(). } static void print_d_1_eax(unsigned int value) { static named_item names[] = { { "XSAVEOPT instruction" , 0, 0, bools }, { "XSAVEC instruction" , 1, 1, bools }, { "XGETBV instruction" , 2, 2, bools }, { "XSAVES/XRSTORS instructions" , 3, 3, bools }, { "XFD: extended feature disable supported" , 4, 4, bools }, }; print_names(value, names, LENGTH(names), /* max_len => */ 39); } static void print_d_1_ecx(unsigned int value) { static named_item names[] = { { " PT state" , 8, 8, bools }, { " PASID state" , 10, 10, bools }, { " CET_U user state" , 11, 11, bools }, { " CET_S supervisor state" , 12, 12, bools }, { " HDC state" , 13, 13, bools }, { " UINTR state" , 14, 14, bools }, { " LBR state" , 15, 15, bools }, { " HWP state" , 16, 16, bools }, }; print_names(value, names, LENGTH(names), /* max_len => */ 39); } static void print_d_n_ecx(unsigned int value) { static ccstring which[] = { "XCR0 (user state)", "IA32_XSS (supervisor state)" }; static named_item names[] = { { "supported in IA32_XSS or XCR0" , 0, 0, which }, { "64-byte alignment in compacted XSAVE" , 1, 1, bools }, { "XFD faulting supported" , 2, 2, bools }, }; print_names(value, names, LENGTH(names), /* max_len => */ 40); } static void print_d_n(const unsigned int words[WORD_NUM], unsigned int sub) { // The XSAVE areas are explained in 325462: Intel 64 and IA-32 Architectures // Software Developer's Manual Combined Volumes: 1, 2A, 2B, 2C, 3A, 3B, and // 3C, Volume 1: Basic Architecture, section 13.1: XSAVE-Supported Features // and State-Component Bitmaps. // // These align with the supported feature names[] in print_d_0_eax() for // values > 1. static ccstring features[64] = { /* 0 => */ "internal error", /* 1 => */ "internal error", /* 2 => */ "AVX/YMM", /* 3 => */ "MPX BNDREGS", /* 4 => */ "MPX BNDCSR", /* 5 => */ "AVX-512 opmask", /* 6 => */ "AVX-512 ZMM_Hi256", /* 7 => */ "AVX-512 Hi16_ZMM", /* 8 => */ "PT", /* 9 => */ "PKRU", /* 10 => */ "PASID", /* 11 => */ "CET_U user", /* 12 => */ "CET_S supervisor", /* 13 => */ "HDC", /* 14 => */ "UINTR", /* 15 => */ "LBR", /* 16 => */ "HWP", /* 17 => */ "XTILECFG", /* 18 => */ "XTILEDATA", /* 19 => */ "APX EGPR", /* 20 => */ "unknown", /* 21 => */ "unknown", /* 22 => */ "unknown", /* 23 => */ "unknown", /* 24 => */ "unknown", /* 25 => */ "unknown", /* 26 => */ "unknown", /* 27 => */ "unknown", /* 28 => */ "unknown", /* 29 => */ "unknown", /* 30 => */ "unknown", /* 31 => */ "unknown", /* 32 => */ "unknown", /* 33 => */ "unknown", /* 34 => */ "unknown", /* 35 => */ "unknown", /* 36 => */ "unknown", /* 37 => */ "unknown", /* 38 => */ "unknown", /* 39 => */ "unknown", /* 40 => */ "unknown", /* 41 => */ "unknown", /* 42 => */ "unknown", /* 43 => */ "unknown", /* 44 => */ "unknown", /* 45 => */ "unknown", /* 46 => */ "unknown", /* 47 => */ "unknown", /* 48 => */ "unknown", /* 49 => */ "unknown", /* 50 => */ "unknown", /* 51 => */ "unknown", /* 52 => */ "unknown", /* 53 => */ "unknown", /* 54 => */ "unknown", /* 55 => */ "unknown", /* 56 => */ "unknown", /* 57 => */ "unknown", /* 58 => */ "unknown", /* 59 => */ "unknown", /* 60 => */ "unknown", /* 61 => */ "unknown", /* 62 => */ "LWP", // AMD only /* 63 => */ "unknown" }; ccstring feature = features[sub]; int feature_pad = 17-strlen(feature); if (sub > 9) { printf(" %s features (0xd/0x%x):\n", feature, sub); } else { printf(" %s features (0xd/%d):\n", feature, sub); } printf(" %s save state byte size%*s = 0x%08x (%u)\n", feature, feature_pad, "", words[WORD_EAX], words[WORD_EAX]); printf(" %s save state byte offset%*s = 0x%08x (%u)\n", feature, feature_pad, "", words[WORD_EBX], words[WORD_EBX]); print_d_n_ecx(words[WORD_ECX]); } static void print_f_0_edx(unsigned int value) { static named_item names[] = { { "supports L3 cache monitoring" , 1, 1, bools }, }; print_names(value, names, LENGTH(names), /* max_len => */ 0); } static void print_f_1_eax(unsigned int value, const code_stash_t* stash) { static named_item names[] = { { "QoS monitoring counter size" , 0, 7, MINUS24_IMAGES }, { "IA32_QM_CTR bit 61 is overflow" , 8, 8, bools }, { "non-CPU agent cache monitoring (CMT)" , 9, 9, bools }, { "non-CPU agent mem bandwidth mon (MBM)" , 10, 10, bools }, }; print_names(value, names, LENGTH(names), /* max_len => */ 43); unsigned int counter_size_raw = BIT_EXTRACT_LE(value, 0, 8); unsigned int counter_size; if (counter_size_raw == 0) { if (stash) { unsigned int synth_family = Synth_Family(stash->val_1_eax); unsigned int synth_model = Synth_Model(stash->val_1_eax); if (synth_family == 0x17 && 0x30 <= synth_model && synth_model <= 0x9f) { // V1.0 PQoS => 62 counter_size = 62; } else if (synth_family == 0x19 && synth_model <= 0x0f) { // V2.0 PQoS => 44 counter_size = 44; } else if (synth_family == 0x19 && 0x20 <= synth_model && synth_model <= 0x5f) { // V2.0 PQoS => 44 counter_size = 44; } else { counter_size = 0; } } else { counter_size = 0; } } else { counter_size = 24 + counter_size_raw; } if (counter_size != 0) { printf(" (QoS monitoring counter size synth) = %u\n", counter_size); } } static void print_f_1_edx(unsigned int value) { static named_item names[] = { { "supports L3 occupancy monitoring" , 0, 0, bools }, { "supports L3 total bandwidth monitoring" , 1, 1, bools }, { "supports L3 local bandwidth monitoring" , 2, 2, bools }, }; print_names(value, names, LENGTH(names), /* max_len => */ 43); } static void print_10_0_ebx(unsigned int value) { static named_item names[] = { { "L3 cache allocation technology supported", 1, 1, bools }, { "L2 cache allocation technology supported", 2, 2, bools }, { "memory bandwidth allocation supported" , 3, 3, bools }, { "cache bandwidth allocation supported" , 5, 5, bools }, }; print_names(value, names, LENGTH(names), /* max_len => */ 0); } static void print_10_12_eax(unsigned int value) { static named_item names[] = { { "length of capacity bit mask" , 0, 4, MINUS1_IMAGES }, }; print_names(value, names, LENGTH(names), /* max_len => */ 40); } static void print_10_12_ecx(unsigned int value) { static named_item names[] = { { "non-CPU agent support" , 1, 1, bools }, { "code and data prioritization supported" , 2, 2, bools }, { "non-contiguous bitmask supported" , 3, 3, bools }, }; print_names(value, names, LENGTH(names), /* max_len => */ 40); } static void print_10_3_eax(unsigned int value) { static named_item names[] = { { "maximum throttling value" , 0, 11, MINUS1_IMAGES }, }; print_names(value, names, LENGTH(names), /* max_len => */ 40); } static void print_10_3_ecx(unsigned int value) { static named_item names[] = { { "per-thread MBA control" , 0, 0, bools }, { "delay values are linear" , 2, 2, bools }, }; print_names(value, names, LENGTH(names), /* max_len => */ 40); } static void print_10_5_eax(unsigned int value) { static ccstring scopes[1<<4] = { "invalid (0)", "logical processor (1)" }; static named_item names[] = { { "maximum throttling value" , 0, 7, MINUS1_IMAGES }, { "QoS_Core_BW_Thrtl_n MSR scope" , 8, 11, scopes }, }; print_names(value, names, LENGTH(names), /* max_len => */ 40); } static void print_10_5_ecx(unsigned int value) { static ccstring linears[] = { "non-linear (0)", "linear (1)" }; static named_item names[] = { { "bandwidth control response" , 3, 3, linears }, }; print_names(value, names, LENGTH(names), /* max_len => */ 40); } static void print_10_n_edx(unsigned int value) { static named_item names[] = { { "highest COS number supported" , 0, 15, NIL_IMAGES }, }; print_names(value, names, LENGTH(names), /* max_len => */ 40); } static void print_12_0_eax(unsigned int value) { static named_item names[] = { { "SGX1 supported" , 0, 0, bools }, { "SGX2 supported" , 1, 1, bools }, { "SGX ENCLV E*VIRTCHILD, ESETCONTEXT" , 5, 5, bools }, { "SGX ENCLS ETRACKC, ERDINFO, ELDBC, ELDUC", 6, 6, bools }, { "SGX ENCLU EVERIFYREPORT2" , 7, 7, bools }, { "SGX ENCLS EUPDATESVN" , 10, 10, bools }, { "SGX ENCLU EDECCSSA" , 11, 11, bools }, }; print_names(value, names, LENGTH(names), /* max_len => */ 40); } static void print_12_0_ebx(unsigned int value) { // MISCSELECT is described in Table 38-4: Bit Vector Layout of MISCSELECT // Field of Extended Information. static named_item names[] = { { "MISCSELECT.EXINFO supported: #PF & #GP" , 0, 0, bools }, { "MISCSELECT.CPINFO supported: #CP" , 1, 1, bools }, }; print_names(value, names, LENGTH(names), /* max_len => */ 40); } static void print_12_0_edx(unsigned int value) { static named_item names[] = { { "MaxEnclaveSize_Not64 (log2)" , 0, 7, NIL_IMAGES }, { "MaxEnclaveSize_64 (log2)" , 8, 15, NIL_IMAGES }, }; print_names(value, names, LENGTH(names), /* max_len => */ 40); } static void print_12_1_eax(unsigned int value) { // SECS.ATTRIBUTES are described in 325462: Intel 64 and IA-32 Architectures // Software Developer's Manual Combined Volumes: 1, 2A, 2B, 2C, 3A, 3B, 3C, // 3D, and 4, Volume 3: System Programming Guide, section 33.7.1: ATTRIBUTES. // // eax contains ATTRIBUTES[31:0]. static named_item names[] = { { "enclave initialized by EINIT" , 0, 0, bools }, { "enclave debugger read/write permission" , 1, 1, bools }, { "enclave 64-bit mode" , 2, 2, bools }, { "provisioning key available" , 4, 4, bools }, { "EINIT token key available" , 5, 5, bools }, { "CET attributes enabled" , 6, 6, bools }, { "KSS key separation & sharing enabled" , 7, 7, bools }, // The following described in "Asynchronous Enclave Exit Notify and // the EDECCSSA User Leaf Function" White Paper from Intel. { "AEX attribute enabled" , 10, 10, bools }, }; print_names(value, names, LENGTH(names), /* max_len => */ 38); } static void print_12_1_ebx(unsigned int value UNUSED) { // SECS.ATTRIBUTES are described in 325462: Intel 64 and IA-32 Architectures // Software Developer's Manual Combined Volumes: 1, 2A, 2B, 2C, 3A, 3B, 3C, // 3D, and 4, Volume 3: System Programming Guide, section 33.7.1: ATTRIBUTES. // // ebx contains ATTRIBUTES[63:32]. // Currently all bits reserved. } static void print_12_1_ecx(unsigned int value) { // SECS.ATTRIBUTES are described in 325462: Intel 64 and IA-32 Architectures // Software Developer's Manual Combined Volumes: 1, 2A, 2B, 2C, 3A, 3B, 3C, // 3D, and 4, Volume 3: System Programming Guide, section 33.7.1: ATTRIBUTES. // // ebx contains ATTRIBUTES[95:64], which is XFRM[31:0] (described in Volume // 3, 37.7.2.1 SECS.ATTRIBUTES.XFVM), which is equivalent to XCR0[31:0] // (described in Volume 1, 13.1 XSAVE-Supported Features and State-Component // Bitmaps). // // See also print_d_0_eax(). static named_item names[] = { { " XCR0 supported: x87 state" , 0, 0, bools }, { " XCR0 supported: SSE state" , 1, 1, bools }, { " XCR0 supported: AVX state" , 2, 2, bools }, { " XCR0 supported: MPX BNDREGS" , 3, 3, bools }, { " XCR0 supported: MPX BNDCSR" , 4, 4, bools }, { " XCR0 supported: AVX-512 opmask" , 5, 5, bools }, { " XCR0 supported: AVX-512 ZMM_Hi256" , 6, 6, bools }, { " XCR0 supported: AVX-512 Hi16_ZMM" , 7, 7, bools }, { " IA32_XSS supported: PT state" , 8, 8, bools }, { " XCR0 supported: PKRU state" , 9, 9, bools }, { " XCR0 supported: CET_U state" , 11, 11, bools }, { " XCR0 supported: CET_S state" , 12, 12, bools }, { " IA32_XSS supported: HDC state" , 13, 13, bools }, { " IA32_XSS supported: UINTR state" , 14, 14, bools }, { " LBR supported" , 15, 15, bools }, { " IA32_XSS supported: HWP state" , 16, 16, bools }, { " XTILECFG supported" , 17, 17, bools }, { " XTILEDATA supported" , 18, 18, bools }, }; print_names(value, names, LENGTH(names), /* max_len => */ 38); } static void print_12_1_edx(unsigned int value UNUSED) { // SECS.ATTRIBUTES are described in 325462: Intel 64 and IA-32 Architectures // Software Developer's Manual Combined Volumes: 1, 2A, 2B, 2C, 3A, 3B, 3C, // 3D, and 4, Volume 3: System Programming Guide, section 33.7.1: ATTRIBUTES. // // ebx contains ATTRIBUTES[95:64], which is XFRM[63:32] (described in Volume // 3, 37.7.2.1 SECS.ATTRIBUTES.XFVM), which is equivalent to XCR0[63:32] // (described in Volume 1, 13.1 XSAVE-Supported Features and State-Component // Bitmaps). // // See also print_d_0_edx(). // Currently all bits reserved. } static void print_12_n_eax(unsigned int value, unsigned int max_len) { static ccstring types[1<<4] = { /* 0 => */ "invalid", /* 1 => */ "EPC section" }; static named_item names[] = { { "type" , 0, 3, types }, }; print_names(value, names, LENGTH(names), /* max_len => */ max_len); } static void print_12_n_ecx(unsigned int value) { static ccstring props[1<<4] = { /* 0 => */ "enumerated as 0", /* 1 => */ "confidentiality, integrity & replay protection", /* 2 => */ "confidentiality protection only", /* 3 => */ "confidentiality & integrity protection only" }; static named_item names[] = { { "section property" , 0, 3, props }, }; print_names(value, names, LENGTH(names), /* max_len => */ 24); } static void print_14_0_ebx(unsigned int value) { static named_item names[] = { { "IA32_RTIT_CR3_MATCH is accessible" , 0, 0, bools }, { "configurable PSB & cycle-accurate" , 1, 1, bools }, { "IP & TraceStop filtering; PT preserve" , 2, 2, bools }, { "MTC timing packet; suppress COFI-based" , 3, 3, bools }, { "PTWRITE support" , 4, 4, bools }, { "power event trace support" , 5, 5, bools }, { "PSB/PMI preservation support" , 6, 6, bools }, { "IA32_RTIT_CTL EventEn enable supported" , 7, 7, bools }, { "IA32_RTIT_CTL DisTNT disable supported" , 8, 8, bools }, { "PTTT processor trace trigger tracing" , 9, 9, bools }, }; print_names(value, names, LENGTH(names), /* max_len => */ 38); } static void print_14_0_ecx(unsigned int value) { static named_item names[] = { { "ToPA output scheme support" , 0, 0, bools }, { "ToPA can hold many output entries" , 1, 1, bools }, { "single-range output scheme support" , 2, 2, bools }, { "output to trace transport" , 3, 3, bools }, { "IP payloads have LIP values & CS" , 31, 31, bools }, }; print_names(value, names, LENGTH(names), /* max_len => */ 38); } static void print_14_1_eax(unsigned int value) { static named_item names[] = { { "configurable address ranges" , 0, 2, NIL_IMAGES }, { "number of IA32_RTIT_TRIGGERx_CFG MSRs" , 8, 10, D4_IMAGES }, { "supported MTC periods bitmask" , 16, 31, NIL_IMAGES }, }; print_names(value, names, LENGTH(names), /* max_len => */ 38); } static void print_14_1_ebx(unsigned int value) { static named_item names[] = { { "supported cycle threshold bitmask" , 0, 15, NIL_IMAGES }, { "supported config PSB freq bitmask" , 16, 31, NIL_IMAGES }, }; print_names(value, names, LENGTH(names), /* max_len => */ 38); } static void print_14_1_ecx(unsigned int value) { static named_item names[] = { { "trigger action attribution supported" , 0, 0, bools }, { "TRACE_PAUSE, TRACE_RESUME supported" , 1, 1, bools }, { "trigger input DR match supported" , 15, 15, bools }, }; print_names(value, names, LENGTH(names), /* max_len => */ 38); } static void print_16_eax(unsigned int value) { static named_item names[] = { { "Core Base Frequency (MHz)" , 0, 15, NIL_IMAGES }, }; print_names(value, names, LENGTH(names), /* max_len => */ 0); } static void print_16_ebx(unsigned int value) { static named_item names[] = { { "Core Maximum Frequency (MHz)" , 0, 15, NIL_IMAGES }, }; print_names(value, names, LENGTH(names), /* max_len => */ 0); } static void print_16_ecx(unsigned int value) { static named_item names[] = { { "Bus (Reference) Frequency (MHz)" , 0, 15, NIL_IMAGES }, }; print_names(value, names, LENGTH(names), /* max_len => */ 0); } static void print_17_0_ebx(unsigned int value) { static ccstring schemes[] = { /* 0 => */ "assigned by intel", /* 1 => */ "industry standard" }; static named_item names[] = { { "vendor id" , 0, 15, NIL_IMAGES }, { "vendor scheme" , 16, 16, schemes }, }; print_names(value, names, LENGTH(names), /* max_len => */ 0); } static void print_18_n_ebx(unsigned int value) { static ccstring parts[1<<3] = { /* 0 => */ "soft between logical processors", /* 1 => */ NULL, /* 2 => */ NULL, /* 3 => */ NULL, /* 4 => */ NULL, /* 5 => */ NULL, /* 6 => */ NULL, /* 7 => */ NULL }; static named_item names[] = { { "4KB page size entries supported" , 0, 0, bools }, { "2MB page size entries supported" , 1, 1, bools }, { "4MB page size entries supported" , 2, 2, bools }, { "1GB page size entries supported" , 3, 3, bools }, { "partitioning" , 8, 10, parts }, { "ways of associativity" , 16, 31, NIL_IMAGES }, }; print_names(value, names, LENGTH(names), /* max_len => */ 33); } static void print_18_n_edx(unsigned int value) { static ccstring tlbs[1<<5] = { /* 00000b => */ "invalid (0)", /* 00001b => */ "data TLB", /* 00010b => */ "instruction TLB", /* 00011b => */ "unified TLB", /* 00100b => */ "load-only TLB", /* 00101b => */ "store-only TLB" }; static named_item names[] = { { "translation cache type" , 0, 4, tlbs }, { "translation cache level" , 5, 7, MINUS1_IMAGES }, { "fully associative" , 8, 8, bools }, { "maximum number of addressible IDs" , 14, 25, MINUS1_IMAGES }, }; print_names(value, names, LENGTH(names), /* max_len => */ 33); } static void print_19_eax(unsigned int value) { static named_item names[] = { { "CPL0-only restriction supported" , 0, 0, bools }, { "no-encrypt restriction supported" , 1, 1, bools }, { "no-decrypt restriction supported" , 2, 2, bools }, }; print_names(value, names, LENGTH(names), /* max_len => */ 32); } static void print_19_ebx(unsigned int value) { static named_item names[] = { { "AESKLE: AES instructions" , 0, 0, bools }, { "AES wide instructions" , 2, 2, bools }, { "MSRs & IWKEY backups" , 4, 4, bools }, }; print_names(value, names, LENGTH(names), /* max_len => */ 32); } static void print_19_ecx(unsigned int value) { static named_item names[] = { { "LOADIWKEY NoBackup parameter" , 0, 0, bools }, { "IWKEY randomization supported" , 1, 1, bools }, }; print_names(value, names, LENGTH(names), /* max_len => */ 32); } static void print_1a_0_eax(unsigned int value) { static ccstring coretypes[1<<8] = { /* 00h-0fh => */ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, /* 10h-1fh => */ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, /* 20h => */ "Intel Atom", /* 21h-2fh => */ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, /* 30h-3fh => */ NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, /* 40h => */ "Intel Core" }; static named_item names[] = { { "native model ID of core" , 0, 23, NIL_IMAGES }, { "core type" , 24, 31, coretypes }, }; print_names(value, names, LENGTH(names), /* max_len => */ 0); } static void print_1b_n_eax(unsigned int value) { static ccstring types[1<<12] = { /* 0 => */ "invalid (0)", /* 1 => */ "target identifier (1)" }; static named_item names[] = { { "sub-leaf type" , 0, 11, types }, }; print_names(value, names, LENGTH(names), /* max_len => */ 0); } static void print_1b_n_target(unsigned int target, unsigned int value) { static ccstring targets[1<<12] = { /* 0 => */ "ignored (0)", /* 1 => */ "MKTME (1)", /* 2 => */ "TSE (2)" }; char buf[128]; sprintf(buf, "identifier of target %u", target); named_item names[] = { { buf, 0, 31, targets } }; print_names(value, names, LENGTH(names), /* max_len => */ 0); } static void print_1c_eax(unsigned int value) { static ccstring ipvs[1<<1] = { /* 0 => */ "EIP (0)", /* 1 => */ "LIP (1)" }; static named_item names[] = { { "IA32_LBR_DEPTH.DEPTH 8 supported" , 0, 0, bools }, { "IA32_LBR_DEPTH.DEPTH 16 supported" , 1, 1, bools }, { "IA32_LBR_DEPTH.DEPTH 24 supported" , 2, 2, bools }, { "IA32_LBR_DEPTH.DEPTH 32 supported" , 3, 3, bools }, { "IA32_LBR_DEPTH.DEPTH 40 supported" , 4, 4, bools }, { "IA32_LBR_DEPTH.DEPTH 48 supported" , 5, 5, bools }, { "IA32_LBR_DEPTH.DEPTH 56 supported" , 6, 6, bools }, { "IA32_LBR_DEPTH.DEPTH 64 supported" , 7, 7, bools }, { "deep C-state reset supported" , 30, 30, bools }, { "LBR IP values contain" , 31, 31, ipvs }, }; print_names(value, names, LENGTH(names), /* max_len => */ 33); } static void print_1c_ebx(unsigned int value) { static named_item names[] = { { "CPL filtering supported" , 0, 0, bools }, { "branch filtering supported" , 1, 1, bools }, { "call-stack mode supported" , 2, 2, bools }, }; print_names(value, names, LENGTH(names), /* max_len => */ 33); } static void print_1c_ecx(unsigned int value) { static named_item names[] = { { "mispredict bit supported" , 0, 0, bools }, { "timed LBRs supported" , 1, 1, bools }, { "branch type field supported" , 2, 2, bools }, { "event logging supported bitmap" , 16, 19, NIL_IMAGES }, }; print_names(value, names, LENGTH(names), /* max_len => */ 33); } static void print_1d_n_eax(unsigned int value) { static named_item names[] = { { "total_tile_bytes" , 0, 15, NIL_IMAGES }, { "bytes_per_tile" , 16, 31, NIL_IMAGES }, }; print_names(value, names, LENGTH(names), /* max_len => */ 16); } static void print_1d_n_ebx(unsigned int value) { static named_item names[] = { { "bytes_per_row" , 0, 15, NIL_IMAGES }, { "max_names" , 16, 31, NIL_IMAGES }, }; print_names(value, names, LENGTH(names), /* max_len => */ 16); } static void print_1d_n_ecx(unsigned int value) { static named_item names[] = { { "max_rows" , 0, 15, NIL_IMAGES }, }; print_names(value, names, LENGTH(names), /* max_len => */ 16); } static void print_1e_0_ebx(unsigned int value) { static named_item names[] = { { "tmul_maxk" , 0, 7, NIL_IMAGES }, { "tmul_maxn" , 8, 23, NIL_IMAGES }, }; print_names(value, names, LENGTH(names), /* max_len => */ 40); } static void print_1e_1_eax(unsigned int value) { static named_item names[] = { { "AMX-INT8: tile 8-bit integer support" , 0, 0, bools }, { "AMX-BF16: tile bfloat16 support" , 1, 1, bools }, { "AMX-COMPLEX: tile AMX-COMPLEX instrs" , 2, 2, bools }, { "AMX-FP16: tile FP16 support" , 3, 3, bools }, { "AMX-FP8: tile FP8 support" , 4, 4, bools }, { "AMX-TRANSPOSE: tile AMX-TRANSPOSE instrs", 5, 5, bools }, { "AMX-TF32: tile TF32 (FP19) instrs" , 6, 6, bools }, { "AMX-AVX512: tile AMX-AVX512 instrs" , 7, 7, bools }, { "AMX-MOVRS: tile MOVRS instrs" , 8, 8, bools }, }; print_names(value, names, LENGTH(names), /* max_len => */ 40); } static void print_20_ebx(unsigned int value) { /* ** The meanings of the bits correlate with the IA32_HRESET_ENABLE MSR bits. */ static named_item names[] = { { "HRESET supported: EHFI history" , 0, 0, bools }, }; print_names(value, names, LENGTH(names), /* max_len => */ 0); } static void print_23_0_eax(unsigned int value) { // Most of the 23/0/eax bits just indicate whether a subleaf exists. // But this one does a little bit more. static named_item names[] = { { "architectural PEBS support" , 5, 5, bools }, }; print_names(value, names, LENGTH(names), /* max_len => */ 36); } static void print_23_0_ebx(unsigned int value) { static named_item names[] = { { "IA32_PERFEVTSELx UnitMask2 supported" , 0, 0, bools }, { "IA32_PERFEVTSELx EQ bit supported" , 1, 1, bools }, }; print_names(value, names, LENGTH(names), /* max_len => */ 36); } static void print_23_0_ecx(unsigned int value) { static named_item names[] = { { "number of slots per cycle" , 0, 7, NIL_IMAGES }, }; print_names(value, names, LENGTH(names), /* max_len => */ 36); } static void print_23_3_eax(unsigned int value) { static named_item names[] = { { "core cycles" , 0, 0, bools }, { "instructions retired" , 1, 1, bools }, { "reference cycles" , 2, 2, bools }, { "last level cache references" , 3, 3, bools }, { "last level cache misses" , 4, 4, bools }, { "branch instructions retired" , 5, 5, bools }, { "branch mispredicts retired" , 6, 6, bools }, { "topdown slots" , 7, 7, bools }, { "topdown backend bound" , 8, 8, bools }, { "topdown bad speculation" , 9, 9, bools }, { "topdown frontend bound" , 10, 10, bools }, { "topdown retiring" , 11, 11, bools }, { "LBR inserts" , 12, 12, bools }, }; print_names(value, names, LENGTH(names), /* max_len => */ 0); } static void print_23_4_ebx(unsigned int value) { // Comments suggest these 2 bits are "all or none". static ccstring lbrs[1<<2] = { /* 00 => */ "not supported (0b00)", /* 01 => */ "unknown (0b01)", /* 02 => */ "unknown (0b02)", /* 03 => */ "supported (0b03)" }; static named_item names[] = { { "ALLOW_IN_RECORD bit support" , 3, 3, bools }, { "CNTR general-purpose subgroup support" , 4, 4, bools }, { "CNTR fixed-function subgroup support" , 5, 5, bools }, { "CNTR perf metrics subgroup support" , 6, 6, bools }, { "LBR bits support" , 8, 9, lbrs }, { "XER XMMn support" , 16, 16, bools }, { "XER YMMn Hi support" , 17, 17, bools }, { "XER AVX-512 opmask support" , 20, 20, bools }, { "XER AVX-512 ZMM_Hi256 support" , 21, 21, bools }, { "XER AVX-512 Hi16_ZMM support" , 22, 22, bools }, { "general-purpose group is available" , 29, 29, bools }, { "auxiliary group is available" , 30, 30, bools }, }; print_names(value, names, LENGTH(names), /* max_len => */ 0); } static void print_24_0_ebx(unsigned int value) { static named_item names[] = { { "AVX10 converged vector ISA version" , 0, 7, NIL_IMAGES }, { "128-bit vectors supported" , 16, 16, bools }, { "256-bit vectors supported" , 17, 17, bools }, { "512-bit vectors supported" , 18, 18, bools }, }; print_names(value, names, LENGTH(names), /* max_len => */ 0); } static void print_20000001_edx(unsigned int value) { // I found a vague reference to this leaf in Intel Xeon Phi Coprocessor // System Developers Guide, 4.2.17 CPUID: "0x20000001 for graphics function // information." But I found no document that specifies that information. // sandpile.org had the following bit. static named_item names[] = { { "k1om" , 0, 0, bools }, }; printf(" Xeon Phi graphics function features (0x20000001/edx):\n"); print_names(value, names, LENGTH(names), /* max_len => */ 0); } static void print_hypervisor_1_eax_kvm(unsigned int reg, unsigned int value) { // See Linux Documentation/virt/kvm/x86/cpuid.rst. static named_item names[] = { { "kvmclock available at MSR 0x11" , 0, 0, bools }, { "delays unnecessary for PIO ops" , 1, 1, bools }, { "mmu_op" , 2, 2, bools }, { "kvmclock available at MSR 0x4b564d00" , 3, 3, bools }, { "async pf enable available by MSR" , 4, 4, bools }, { "steal clock supported" , 5, 5, bools }, { "guest EOI optimization enabled" , 6, 6, bools }, { "guest spinlock optimization enabled" , 7, 7, bools }, { "guest TLB flush optimization enabled" , 9, 9, bools }, { "async PF VM exit enable available by MSR", 10, 10, bools }, { "guest send IPI optimization enabled" , 11, 11, bools }, { "host HLT poll disable at MSR 0x4b564d05" , 12, 12, bools }, { "guest sched yield optimization enabled" , 13, 13, bools }, { "guest uses intrs for page ready APF evs" , 14, 14, bools }, { "extended destination ID" , 15, 15, bools }, { "map gpa range hypercall supported" , 16, 16, bools }, { "MSR_KVM_MIGRATION_CONTROL supported" , 17, 17, bools }, { "stable: no guest per-cpu warps expected" , 24, 24, bools }, }; printf(" hypervisor features (0x%08x/eax):\n", reg); print_names(value, names, LENGTH(names), /* max_len => */ 0); } static void print_hypervisor_1_edx_kvm(unsigned int reg, unsigned int value) { static named_item names[] = { { "realtime hint: no unbound preemption" , 0, 0, bools }, }; printf(" hypervisor features (0x%08x/edx):\n", reg); print_names(value, names, LENGTH(names), /* max_len => */ 0); } static void print_hypervisor_1_eax_acrn(unsigned int reg, unsigned int value) { // See Linux Documentation/virt/acrn/cpuid.rst. static named_item names[] = { { "guest VM is a privileged VM" , 0, 0, bools }, }; printf(" hypervisor features (0x%08x/eax):\n", reg); print_names(value, names, LENGTH(names), /* max_len => */ 0); } static void print_hypervisor_2_ecx_xen(unsigned int value) { static named_item names[] = { { "MMU_PT_UPDATE_PRESERVE_AD supported" , 0, 0, bools }, }; print_names(value, names, LENGTH(names), /* max_len => */ 0); } static void print_hypervisor_3_0_eax_xen(unsigned int value) { static named_item names[] = { { "vtsc" , 0, 0, bools }, { "host tsc is safe" , 1, 1, bools }, { "boot cpu has RDTSCP" , 2, 2, bools }, }; print_names(value, names, LENGTH(names), /* max_len => */ 0); } static void print_hypervisor_3_0_ebx_xen(unsigned int value) { static ccstring modes[] = { "default", "always emulate", "never emulate", "paravirtualized rdtscp" }; if (value >= LENGTH(modes)) { printf(" tsc mode = 0x%0x (%u)\n", value, value); } else { printf(" tsc mode = %s (%u)\n", modes[value], value); } } static void print_hypervisor_3_eax_microsoft(unsigned int reg, unsigned int value) { // Bits correspond to the HV_PARTITION_PRIVILEGE_MASK. // See: https://docs.microsoft.com/en-us/virtualization/hyper-v-on-windows/tlfs/datatypes/hv_partition_privilege_mask static named_item names[] = { { "VP run time" , 0, 0, bools }, { "partition reference counter" , 1, 1, bools }, { "basic synIC MSRs" , 2, 2, bools }, { "synthetic timer MSRs" , 3, 3, bools }, { "APIC access MSRs" , 4, 4, bools }, { "hypercall MSRs" , 5, 5, bools }, { "access virtual process index MSR" , 6, 6, bools }, { "virtual system reset MSR" , 7, 7, bools }, { "map/unmap statistics pages MSR" , 8, 8, bools }, { "reference TSC access" , 9, 9, bools }, { "guest idle state MSR" , 10, 10, bools }, { "TSC/APIC frequency MSRs" , 11, 11, bools }, { "guest debugging MSRs" , 12, 12, bools }, { "reenlightenment MSRs" , 13, 13, bools }, { "invariant TSC MSR" , 15, 15, bools }, // LX* }; printf(" hypervisor feature identification (0x%08x/eax):\n", reg); print_names(value, names, LENGTH(names), /* max_len => */ 0); } static void print_hypervisor_3_ebx_microsoft(unsigned int reg, unsigned int value) { static named_item names[] = { { "CreatePartitions" , 0, 0, bools }, { "AccessPartitionId" , 1, 1, bools }, { "AccessMemoryPool" , 2, 2, bools }, { "AdjustMessageBuffers" , 3, 3, bools }, { "PostMessages" , 4, 4, bools }, { "SignalEvents" , 5, 5, bools }, { "CreatePort" , 6, 6, bools }, { "ConnectPort" , 7, 7, bools }, { "AccessStats" , 8, 8, bools }, { "Debugging" , 11, 11, bools }, { "CPUManagement" , 12, 12, bools }, { "ConfigureProfiler" , 13, 13, bools }, { "AccessVSM" , 16, 16, bools }, { "AccessVpRegisters" , 17, 17, bools }, { "EnableExtendedHypercalls" , 20, 20, bools }, { "StartVirtualProcessor" , 21, 21, bools }, { "Isolation" , 22, 22, bools }, // LX* }; printf(" hypervisor partition creation flags (0x%08x/ebx):\n", reg); print_names(value, names, LENGTH(names), /* max_len => */ 0); } static void print_hypervisor_3_ecx_microsoft(unsigned int reg, unsigned int value) { static named_item names[] = { { "maximum process power state" , 0, 3, NIL_IMAGES }, { "invariant Mperf" , 5, 5, bools }, { "supervisor shadow stack" , 6, 6, bools }, { "architectural PMU" , 7, 7, bools }, { "exception trap intercept" , 8, 8, bools }, }; printf(" hypervisor power management features (0x%08x/ecx):\n", reg); print_names(value, names, LENGTH(names), /* max_len => */ 0); } static void print_hypervisor_3_edx_microsoft(unsigned int reg, unsigned int value) { static named_item names[] = { { "MWAIT available" , 0, 0, bools }, { "guest debugging support available" , 1, 1, bools }, { "performance monitor support available" , 2, 2, bools }, { "CPU dynamic partitioning events avail" , 3, 3, bools }, { "hypercall XMM input parameters available", 4, 4, bools }, { "virtual guest idle state available" , 5, 5, bools }, { "hypervisor sleep state available" , 6, 6, bools }, { "query NUMA distance available" , 7, 7, bools }, { "determine timer frequency available" , 8, 8, bools }, { "inject synthetic machine check available", 9, 9, bools }, { "guest crash MSRs available" , 10, 10, bools }, { "debug MSRs available" , 11, 11, bools }, { "NPIEP available" , 12, 12, bools }, { "disable hypervisor available" , 13, 13, bools }, { "extended gva ranges for flush virt addrs", 14, 14, bools }, { "hypercall XMM register return available" , 15, 15, bools }, { "sint polling mode available" , 17, 17, bools }, { "hypercall MSR lock available" , 18, 18, bools }, { "use direct synthetic timers" , 19, 19, bools }, { "VSM PAT register available" , 20, 20, bools }, { "VSM bndcfgs register available" , 21, 21, bools }, { "synthetic time unhalted timer available" , 23, 23, bools }, { "Intel LBR: last branch records supported", 26, 26, bools }, }; printf(" hypervisor feature identification (0x%08x/edx):\n", reg); print_names(value, names, LENGTH(names), /* max_len => */ 0); } static void print_hypervisor_4_eax_xen(unsigned int reg, unsigned int value) { static named_item names[] = { { "virtualized APIC registers" , 0, 0, bools }, { "virtualized x2APIC accesses" , 1, 1, bools }, { "IOMMU mappings for other domain memory" , 2, 2, bools }, { "vcpu id is valid" , 3, 3, bools }, { "domain id is valid" , 4, 4, bools }, { "expanded destination id" , 5, 5, bools }, { "upcalls with physical IRQ vectors" , 6, 6, bools }, }; printf(" HVM-specific parameters (0x%08x):\n", reg); print_names(value, names, LENGTH(names), /* max_len => */ 38); } static void print_hypervisor_4_eax_microsoft(unsigned int value) { static named_item names[] = { { "use hypercalls for AS switches" , 0, 0, bools }, { "use hypercalls for local TLB flushes" , 1, 1, bools }, { "use hypercalls for remote TLB flushes" , 2, 2, bools }, { "use MSRs to access EOI, ICR, TPR" , 3, 3, bools }, { "use MSRs to initiate system RESET" , 4, 4, bools }, { "use relaxed timing" , 5, 5, bools }, { "use DMA remapping" , 6, 6, bools }, { "use interrupt remapping" , 7, 7, bools }, { "use x2APIC MSRs" , 8, 8, bools }, { "deprecate AutoEOI" , 9, 9, bools }, { "use SyntheticClusterIpi hypercall" , 10, 10, bools }, { "use ExProcessorMasks" , 11, 11, bools }, { "hypervisor is nested with Hyper-V" , 12, 12, bools }, { "use INT for MBEC system calls" , 13, 13, bools }, { "use enlightened VMCS interface" , 14, 14, bools }, { "use synced timeline" , 15, 15, bools }, { "use direct local flush entire" , 17, 17, bools }, { "no non-architectural core sharing" , 18, 18, bools }, { "use hypercalls for MMIO config space I/O", 21, 21, bools }, }; print_names(value, names, LENGTH(names), /* max_len => */ 41); } static void print_hypervisor_4_ecx_microsoft(unsigned int value) { static named_item names[] = { { "physical address width" , 0, 6, NIL_IMAGES }, }; print_names(value, names, LENGTH(names), /* max_len => */ 41); } static void print_hypervisor_5_0_ebx_xen(unsigned int reg, unsigned int value) { static named_item names[] = { { "maximum machine address width" , 0, 7, NIL_IMAGES }, }; printf(" PV-specific parameters (0x%08x):\n", reg); print_names(value, names, LENGTH(names), /* max_len => */ 0); } static void print_hypervisor_6_eax_microsoft(unsigned int reg, unsigned int value) { static named_item names[] = { { "APIC overlay assist" , 0, 0, bools }, { "MSR bitmaps" , 1, 1, bools }, { "performance counters" , 2, 2, bools }, { "second-level address translation" , 3, 3, bools }, { "DMA remapping" , 4, 4, bools }, { "interrupt remapping" , 5, 5, bools }, { "memory patrol scrubber" , 6, 6, bools }, { "DMA protection" , 7, 7, bools }, { "HPET requested" , 8, 8, bools }, { "synthetic timers are volatile" , 9, 9, bools }, { "hypervisor level of current guest" , 10, 13, NIL_IMAGES }, { "physical destination mode requested" , 14, 14, bools }, { "hardware memory zeroing support" , 16, 16, bools }, { "unrestricted guest support" , 17, 17, bools }, { "resource allocation support" , 18, 18, bools }, { "resource monitoring support" , 19, 19, bools }, { "guest virtual PMU support" , 20, 20, bools }, { "guest virtual LBR support" , 21, 21, bools }, { "guest virtual IPT support" , 22, 22, bools }, { "APIC emulation support" , 23, 23, bools }, { "ACPI WDAT table used by hypervisor" , 24, 24, bools }, }; printf(" hypervisor hardware features used (0x%08x/eax):\n", reg); print_names(value, names, LENGTH(names), /* max_len => */ 0); } static void print_hypervisor_7_eax_microsoft(unsigned int value) { static named_item names[] = { { "StartLogicalProcessor" , 0, 0, bools }, { "CreateRootvirtualProcessor" , 1, 1, bools }, { "PerformanceCounterSync" , 2, 2, bools }, }; print_names(value, names, LENGTH(names), /* max_len => */ 26); } static void print_hypervisor_7_ebx_microsoft(unsigned int value) { static named_item names[] = { { "ProcessorPowerManagement" , 0, 0, bools }, { "MwaitIdleStates" , 1, 1, bools }, { "LogicalProcessorIdling" , 2, 2, bools }, }; print_names(value, names, LENGTH(names), /* max_len => */ 26); } static void print_hypervisor_7_ecx_microsoft(unsigned int value) { static named_item names[] = { { "RemapGuestUncached" , 0, 0, bools }, }; print_names(value, names, LENGTH(names), /* max_len => */ 26); } static void print_hypervisor_8_eax_microsoft(unsigned int value) { static named_item names[] = { { "SvmSupported" , 0, 0, bools }, { "MaxPasidSpacePasidCount" , 11, 31, NIL_IMAGES }, }; print_names(value, names, LENGTH(names), /* max_len => */ 0); } static void print_hypervisor_9_eax_microsoft(unsigned int value) { static named_item names[] = { { "AccessSynicRegs" , 2, 2, bools }, { "AccessIntrCtrlRegs" , 4, 4, bools }, { "AccessHypercallMsrs" , 5, 5, bools }, { "AccessVpIndex" , 6, 6, bools }, { "AccessReenlightenmentControls" , 12, 12, bools }, }; print_names(value, names, LENGTH(names), /* max_len => */ 37); } static void print_hypervisor_9_edx_microsoft(unsigned int value) { static named_item names[] = { { "XmmRegistersForFastHypercallAvailable" , 4, 4, bools }, { "FastHypercallOutputAvailable" , 15, 15, bools }, { "SintPoillingModeAvailable" , 17, 17, bools }, }; print_names(value, names, LENGTH(names), /* max_len => */ 37); } static void print_hypervisor_a_eax_microsoft(unsigned int value) { static named_item names[] = { { "enlightened VMCS version (low)" , 0, 7, NIL_IMAGES }, { "enlightened VMCS version (high)" , 8, 15, NIL_IMAGES }, { "direct virtual flush hypercalls support" , 17, 17, bools }, { "HvFlushGuestPhysicalAddress* hypercalls" , 18, 18, bools }, { "enlightened MSR bitmap support" , 19, 19, bools }, { "page fault combining virtual exceptions" , 20, 20, bools }, { "VMCS GuestIa32DebugCtl support" , 21, 21, bools }, { "nested enlightened TLB flush support" , 22, 22, bools }, }; print_names(value, names, LENGTH(names), /* max_len => */ 39); } static void print_hypervisor_a_ebx_microsoft(unsigned int value) { static named_item names[] = { { "VMCS HvFlushGuestPhysicalAddress*" , 0, 0, bools }, }; print_names(value, names, LENGTH(names), /* max_len => */ 39); } static void print_hypervisor_c_eax_microsoft(unsigned int value) { static named_item names[] = { { "paravisor present" , 0, 0, bools }, // LX* }; print_names(value, names, LENGTH(names), /* max_len => */ 0); } static void print_hypervisor_c_ebx_microsoft(unsigned int value) { static ccstring isoltypes[1<<4] = { /* 0 => */ "none (0)", /* 1 => */ "VBS (1)", /* 2 => */ "SNP (2)", /* 3 => */ "TDX (3)" }; static named_item names[] = { { "isolation type" , 0, 3, isoltypes }, // LX* { "shared GPA boundary active" , 5, 5, bools }, // LX* { "shared GPA boundary bits" , 6, 11, NIL_IMAGES }, // LX* }; print_names(value, names, LENGTH(names), /* max_len => */ 0); } static void print_hypervisor_82_eax_microsoft(unsigned int value) { static named_item names[] = { { "allow kernel debugging" , 1, 1, bools }, // Qemu* }; print_names(value, names, LENGTH(names), /* max_len => */ 0); } static void print_80000001_eax_amd(unsigned int value, const print_opts_t* opts) { static named_item names[] = { { "family/generation" , 8, 11, NIL_IMAGES }, { "model" , 4, 7, NIL_IMAGES }, { "stepping id" , 0, 3, NIL_IMAGES }, { "extended family" , 20, 27, NIL_IMAGES }, { "extended model" , 16, 19, NIL_IMAGES }, }; printf(" extended processor signature (0x80000001/eax):\n"); print_names(value, names, LENGTH(names), /* max_len => */ 15); unsigned int synth_family = Synth_Family(value); unsigned int synth_model = Synth_Model(value); printf(" (family synth) = 0x%x (%u)\n", synth_family, synth_family); printf(" (model synth) = 0x%x (%u)\n", synth_model, synth_model); if (opts->simple) { print_x_synth_amd(value); } } static void print_80000001_eax_hygon(unsigned int value, const print_opts_t* opts) { static named_item names[] = { { "family/generation" , 8, 11, NIL_IMAGES }, { "model" , 4, 7, NIL_IMAGES }, { "stepping id" , 0, 3, NIL_IMAGES }, { "extended family" , 20, 27, NIL_IMAGES }, { "extended model" , 16, 19, NIL_IMAGES }, }; printf(" extended processor signature (0x80000001/eax):\n"); print_names(value, names, LENGTH(names), /* max_len => */ 15); unsigned int synth_family = Synth_Family(value); unsigned int synth_model = Synth_Model(value); printf(" (family synth) = 0x%x (%u)\n", synth_family, synth_family); printf(" (model synth) = 0x%x (%u)\n", synth_model, synth_model); if (opts->simple) { print_x_synth_hygon(value); } } static void print_80000001_eax_via(unsigned int value, const print_opts_t* opts) { static named_item names[] = { { "generation" , 8, 11, NIL_IMAGES }, { "model" , 4, 7, NIL_IMAGES }, { "stepping" , 0, 3, NIL_IMAGES }, }; printf(" extended processor signature (0x80000001/eax):\n"); print_names(value, names, LENGTH(names), /* max_len => */ 0); if (opts->simple) { print_x_synth_via(value); } } static void print_80000001_eax_transmeta(unsigned int value, const print_opts_t* opts) { static named_item names[] = { { "generation" , 8, 11, NIL_IMAGES }, { "model" , 4, 7, NIL_IMAGES }, { "stepping" , 0, 3, NIL_IMAGES }, }; printf(" extended processor signature (0x80000001/eax):\n"); print_names(value, names, LENGTH(names), /* max_len => */ 14); if (opts->simple) { ccstring synth = decode_synth_transmeta(value, NULL); printf(" (simple synth) = "); if (synth != NULL) { printf("%s", synth); } printf("\n"); } } static void print_80000001_eax(unsigned int value, vendor_t vendor, const print_opts_t* opts) { switch (vendor) { case VENDOR_AMD: print_80000001_eax_amd(value, opts); break; case VENDOR_VIA: print_80000001_eax_via(value, opts); break; case VENDOR_TRANSMETA: print_80000001_eax_transmeta(value, opts); break; case VENDOR_HYGON: print_80000001_eax_hygon(value, opts); break; case VENDOR_INTEL: case VENDOR_CYRIX: case VENDOR_UMC: case VENDOR_NEXGEN: case VENDOR_RISE: case VENDOR_SIS: case VENDOR_NSC: case VENDOR_VORTEX: case VENDOR_RDC: case VENDOR_ZHAOXIN: case VENDOR_UNKNOWN: /* DO NOTHING */ break; } } static void print_80000001_edx_intel(unsigned int value) { static named_item names[] = { { "SYSCALL and SYSRET instructions" , 11, 11, bools }, { "execution disable" , 20, 20, bools }, { "1-GB large page support" , 26, 26, bools }, { "RDTSCP" , 27, 27, bools }, { "64-bit extensions technology available" , 29, 29, bools }, }; printf(" extended feature flags (0x80000001/edx):\n"); print_names(value, names, LENGTH(names), /* max_len => */ 0); } static void print_80000001_edx_amd(unsigned int value) { static named_item names[] = { { "x87 FPU on chip" , 0, 0, bools }, { "virtual-8086 mode enhancement" , 1, 1, bools }, { "debugging extensions" , 2, 2, bools }, { "page size extensions" , 3, 3, bools }, { "time stamp counter" , 4, 4, bools }, { "RDMSR and WRMSR support" , 5, 5, bools }, { "physical address extensions" , 6, 6, bools }, { "machine check exception" , 7, 7, bools }, { "CMPXCHG8B inst." , 8, 8, bools }, { "APIC on chip" , 9, 9, bools }, { "SYSCALL and SYSRET instructions" , 11, 11, bools }, { "memory type range registers" , 12, 12, bools }, { "global paging extension" , 13, 13, bools }, { "machine check architecture" , 14, 14, bools }, { "conditional move/compare instruction" , 15, 15, bools }, { "page attribute table" , 16, 16, bools }, { "page size extension" , 17, 17, bools }, { "multiprocessing capable" , 19, 19, bools }, { "no-execute page protection" , 20, 20, bools }, { "AMD multimedia instruction extensions" , 22, 22, bools }, { "MMX Technology" , 23, 23, bools }, { "FXSAVE/FXRSTOR" , 24, 24, bools }, { "SSE extensions" , 25, 25, bools }, { "1-GB large page support" , 26, 26, bools }, { "RDTSCP" , 27, 27, bools }, { "long mode (AA-64)" , 29, 29, bools }, { "3DNow! instruction extensions" , 30, 30, bools }, { "3DNow! instructions" , 31, 31, bools }, }; printf(" extended feature flags (0x80000001/edx):\n"); print_names(value, names, LENGTH(names), /* max_len => */ 0); } static void print_80000001_edx_cyrix_via(unsigned int value) { static named_item names[] = { { "x87 FPU on chip" , 0, 0, bools }, { "virtual-8086 mode enhancement" , 1, 1, bools }, { "debugging extensions" , 2, 2, bools }, { "page size extensions" , 3, 3, bools }, { "time stamp counter" , 4, 4, bools }, { "RDMSR and WRMSR support" , 5, 5, bools }, { "physical address extensions" , 6, 6, bools }, { "machine check exception" , 7, 7, bools }, { "CMPXCHG8B inst." , 8, 8, bools }, { "APIC on chip" , 9, 9, bools }, { "SYSCALL and SYSRET instructions" , 11, 11, bools }, { "memory type range registers" , 12, 12, bools }, { "global paging extension" , 13, 13, bools }, { "machine check architecture" , 14, 14, bools }, { "conditional move/compare instruction" , 15, 15, bools }, { "page attribute table" , 16, 16, bools }, { "page size extension" , 17, 17, bools }, { "multiprocessing capable" , 19, 19, bools }, { "AMD multimedia instruction extensions" , 22, 22, bools }, { "MMX Technology" , 23, 23, bools }, { "extended MMX" , 24, 24, bools }, { "SSE extensions" , 25, 25, bools }, { "AA-64" , 29, 29, bools }, { "3DNow! instruction extensions" , 30, 30, bools }, { "3DNow! instructions" , 31, 31, bools }, }; printf(" extended feature flags (0x80000001/edx):\n"); print_names(value, names, LENGTH(names), /* max_len => */ 0); } static void print_80000001_edx_transmeta(unsigned int value) { static named_item names[] = { { "x87 FPU on chip" , 0, 0, bools }, { "virtual-8086 mode enhancement" , 1, 1, bools }, { "debugging extensions" , 2, 2, bools }, { "page size extensions" , 3, 3, bools }, { "time stamp counter" , 4, 4, bools }, { "RDMSR and WRMSR support" , 5, 5, bools }, { "CMPXCHG8B inst." , 8, 8, bools }, { "APIC on chip" , 9, 9, bools }, { "memory type range registers" , 12, 12, bools }, { "global paging extension" , 13, 13, bools }, { "machine check architecture" , 14, 14, bools }, { "conditional move/compare instruction" , 15, 15, bools }, { "FP conditional move instructions" , 16, 16, bools }, { "page size extension" , 17, 17, bools }, { "AMD multimedia instruction extensions" , 22, 22, bools }, { "MMX Technology" , 23, 23, bools }, { "FXSAVE/FXRSTOR" , 24, 24, bools }, }; printf(" extended feature flags (0x80000001/edx):\n"); print_names(value, names, LENGTH(names), /* max_len => */ 0); } static void print_80000001_edx_nsc(unsigned int value) { static named_item names[] = { { "x87 FPU on chip" , 0, 0, bools }, { "virtual-8086 mode enhancement" , 1, 1, bools }, { "debugging extensions" , 2, 2, bools }, { "page size extensions" , 3, 3, bools }, { "time stamp counter" , 4, 4, bools }, { "RDMSR and WRMSR support" , 5, 5, bools }, { "machine check exception" , 7, 7, bools }, { "CMPXCHG8B inst." , 8, 8, bools }, { "SYSCALL and SYSRET instructions" , 11, 11, bools }, { "global paging extension" , 13, 13, bools }, { "conditional move/compare instruction" , 15, 15, bools }, { "FPU conditional move instruction" , 16, 16, bools }, { "MMX Technology" , 23, 23, bools }, { "6x86MX multimedia extensions" , 24, 24, bools }, }; printf(" extended feature flags (0x80000001/edx):\n"); print_names(value, names, LENGTH(names), /* max_len => */ 0); } static void print_80000001_edx(unsigned int value, vendor_t vendor) { switch (vendor) { case VENDOR_INTEL: print_80000001_edx_intel(value); break; case VENDOR_AMD: case VENDOR_HYGON: print_80000001_edx_amd(value); break; case VENDOR_CYRIX: case VENDOR_VIA: print_80000001_edx_cyrix_via(value); break; case VENDOR_TRANSMETA: print_80000001_edx_transmeta(value); break; case VENDOR_NSC: print_80000001_edx_nsc(value); break; case VENDOR_UMC: case VENDOR_NEXGEN: case VENDOR_RISE: case VENDOR_SIS: case VENDOR_VORTEX: case VENDOR_RDC: case VENDOR_ZHAOXIN: case VENDOR_UNKNOWN: /* DO NOTHING */ break; } } static void print_80000001_ecx_amd(unsigned int value) { static named_item names[] = { { "LAHF/SAHF supported in 64-bit mode" , 0, 0, bools }, { "CMP Legacy" , 1, 1, bools }, { "SVM: secure virtual machine" , 2, 2, bools }, { "extended APIC space" , 3, 3, bools }, { "AltMovCr8" , 4, 4, bools }, { "LZCNT advanced bit manipulation" , 5, 5, bools }, { "SSE4A support" , 6, 6, bools }, { "misaligned SSE mode" , 7, 7, bools }, { "3DNow! PREFETCH/PREFETCHW instructions" , 8, 8, bools }, { "OS visible workaround" , 9, 9, bools }, { "instruction based sampling" , 10, 10, bools }, { "XOP support" , 11, 11, bools }, { "SKINIT/STGI support" , 12, 12, bools }, { "watchdog timer support" , 13, 13, bools }, { "lightweight profiling support" , 15, 15, bools }, { "4-operand FMA instruction" , 16, 16, bools }, { "TCE: translation cache extension" , 17, 17, bools }, { "NodeId MSR C001100C" , 19, 19, bools }, // LX* { "TBM support" , 21, 21, bools }, { "topology extensions" , 22, 22, bools }, { "core performance counter extensions" , 23, 23, bools }, { "NB/DF performance counter extensions" , 24, 24, bools }, { "data breakpoint extension" , 26, 26, bools }, { "performance time-stamp counter support" , 27, 27, bools }, { "LLC performance counter extensions" , 28, 28, bools }, { "MWAITX/MONITORX supported" , 29, 29, bools }, { "Address mask extension support" , 30, 30, bools }, }; print_names(value, names, LENGTH(names), /* max_len => */ 0); } static void print_80000001_ecx_intel(unsigned int value) { static named_item names[] = { { "LAHF/SAHF supported in 64-bit mode" , 0, 0, bools }, { "LZCNT advanced bit manipulation" , 5, 5, bools }, { "3DNow! PREFETCH/PREFETCHW instructions" , 8, 8, bools }, }; print_names(value, names, LENGTH(names), /* max_len => */ 0); } static void print_80000001_ecx(unsigned int value, vendor_t vendor) { switch (vendor) { case VENDOR_AMD: printf(" AMD feature flags (0x80000001/ecx):\n"); print_80000001_ecx_amd(value); break; case VENDOR_INTEL: printf(" Intel feature flags (0x80000001/ecx):\n"); print_80000001_ecx_intel(value); break; case VENDOR_HYGON: printf(" Hygon feature flags (0x80000001/ecx):\n"); print_80000001_ecx_amd(value); break; case VENDOR_CYRIX: case VENDOR_VIA: case VENDOR_TRANSMETA: case VENDOR_UMC: case VENDOR_NEXGEN: case VENDOR_RISE: case VENDOR_SIS: case VENDOR_NSC: case VENDOR_VORTEX: case VENDOR_RDC: case VENDOR_ZHAOXIN: case VENDOR_UNKNOWN: /* DO NOTHING */ break; } } static void print_80000001_ebx_amd(unsigned int value, unsigned int val_1_eax) { unsigned int max_len = 0; if (MaskF(val_1_eax) == ShftXF(0) + ShftF(15) && MaskM(val_1_eax) < ShftXM(4) + ShftM(0)) { static named_item names[] = { { "raw" , 0, 31, NIL_IMAGES }, { "BrandId" , 0, 16, NIL_IMAGES }, { "BrandTableIndex" , 6, 12, NIL_IMAGES }, { "NN" , 0, 6, NIL_IMAGES }, }; printf(" extended brand id (0x80000001/ebx):\n"); print_names(value, names, LENGTH(names), /* max_len => */ 0); } else if (MaskF(val_1_eax) == ShftXF(0) + ShftF(15) && MaskM(val_1_eax) >= ShftXM(4) + ShftM(0)) { static named_item names[] = { { "raw" , 0, 31, NIL_IMAGES }, { "BrandId" , 0, 16, NIL_IMAGES }, { "PwrLmt:high" , 6, 8, NIL_IMAGES }, { "PwrLmt:low" , 14, 14, NIL_IMAGES }, { "BrandTableIndex" , 9, 13, NIL_IMAGES }, { "NN:high" , 15, 15, NIL_IMAGES }, { "NN:low" , 0, 5, NIL_IMAGES }, }; printf(" extended brand id (0x80000001/ebx):\n"); print_names(value, names, LENGTH(names), /* max_len => */ 0); } else if (MaskF(val_1_eax) == ShftXF(1) + ShftF(15) || MaskF(val_1_eax) == ShftXF(2) + ShftF(15)) { static named_item names[] = { { "raw" , 0, 31, NIL_IMAGES }, { "BrandId" , 0, 15, NIL_IMAGES }, { "str1" , 11, 14, NIL_IMAGES }, { "str2" , 0, 3, NIL_IMAGES }, { "PartialModel" , 4, 10, NIL_IMAGES }, { "PG" , 15, 15, NIL_IMAGES }, }; printf(" extended brand id (0x80000001/ebx):\n"); max_len = 12; print_names(value, names, LENGTH(names), /* max_len => */ max_len); } else { static named_item names[] = { { "raw" , 0, 31, NIL_IMAGES }, { "BrandId" , 0, 15, NIL_IMAGES }, }; printf(" extended brand id (0x80000001/ebx):\n"); max_len = 7; print_names(value, names, LENGTH(names), /* max_len => */ max_len); } // PkgType values come from these two guides (depending on family): // AMD BIOS and Kernel Developer's Guide (BKDG) for ... // Processor Programming Reference (PPPR) for ... // // NOTE: AMD Family = XF + F, e.g. 0x17 (17h) = 0xf + 0x8 // AMD Model = (XM << 4) + M, e.g. 0x18 (18h) = (0x1 << 4) + 0x8 if (MaskF(val_1_eax) >= ShftXF(1) + ShftF(15)) { ccstring* use_pkg_type = NIL_IMAGES; if (MaskF(val_1_eax) == ShftXF(1) + ShftF(15)) { // Family 10h static ccstring pkg_type[1<<4] = { "Fr2/Fr5/Fr6 (0)", "AM2r2/AM3 (1)", "S1g3/S1g4 (2)", "G34 (3)", "ASB2 (4)", "C32 (5)" }; use_pkg_type = pkg_type; } else if (MaskF(val_1_eax) == ShftXF(6) + ShftF(15)) { // Family 15h if (MaskM(val_1_eax) <= ShftXM(0) + ShftM(15)) { static ccstring pkg_type[1<<4] = { NULL, "AM3r2 (1)", NULL, "G34r1 (3)", NULL, "C32r1 (5)" }; use_pkg_type = pkg_type; } else if (MaskM(val_1_eax) >= ShftXM(1) + ShftM(0) && MaskM(val_1_eax) <= ShftXM(1) + ShftM(15)) { static ccstring pkg_type[1<<4] = { "FP2 (BGA) (0)", "FS1r2 (uPGA) (1)", "FM2 (PGA) (2)" }; use_pkg_type = pkg_type; } else if (MaskM(val_1_eax) >= ShftXM(3) + ShftM(0) && MaskM(val_1_eax) <= ShftXM(3) + ShftM(15)) { static ccstring pkg_type[1<<4] = { "FP3 (BGA) (0)", "FM2r2 (uPGA) (1)" }; use_pkg_type = pkg_type; } else if (MaskM(val_1_eax) >= ShftXM(6) + ShftM(0) && MaskM(val_1_eax) <= ShftXM(6) + ShftM(15)) { static ccstring pkg_type[1<<4] = { "FP4 (BGA) (0)", NULL, "AM4 (uPGA) (2)", "FM2r2 (uPGA) (3)" }; use_pkg_type = pkg_type; } else if (MaskM(val_1_eax) >= ShftXM(7) + ShftM(0) && MaskM(val_1_eax) <= ShftXM(7) + ShftM(15)) { static ccstring pkg_type[1<<4] = { "FP4 (BGA) (0)", NULL, "AM4 (uPGA) (2)", NULL, "FT4 (BGA) (4)" }; use_pkg_type = pkg_type; } } else if (MaskF(val_1_eax) == ShftXF(7) + ShftF(15)) { // Family 16h if (MaskM(val_1_eax) <= ShftXM(0) + ShftM(15)) { static ccstring pkg_type[1<<4] = { "FT3 (BGA) (0)", "FS1b (1)" }; use_pkg_type = pkg_type; } else if (MaskM(val_1_eax) >= ShftXM(3) + ShftM(0) && MaskM(val_1_eax) <= ShftXM(3) + ShftM(15)) { static ccstring pkg_type[1<<4] = { "FT3b (BGA) (0)", NULL, NULL, "FP4 (3)" }; use_pkg_type = pkg_type; } } else if (MaskF(val_1_eax) == ShftXF(8) + ShftF(15)) { // Family 17h if (MaskMm(val_1_eax) == ShftXM(0) + ShftM(0) || MaskMm(val_1_eax) == ShftXM(0) + ShftM(8)) { static ccstring pkg_type[1<<4] = { NULL, NULL, "AM4 (2)" }; use_pkg_type = pkg_type; } else if (MaskMm(val_1_eax) == ShftXM(1) + ShftM(8) || MaskMm(val_1_eax) == ShftXM(2) + ShftM(0)) { static ccstring pkg_type[1<<4] = { "FP5 (0)", NULL, "AM4 (2)" }; use_pkg_type = pkg_type; } else if (MaskMm(val_1_eax) == ShftXM(7) + ShftM(0)) { static ccstring pkg_type[1<<4] = { NULL, NULL, "AM4 (2)" }; use_pkg_type = pkg_type; } } else if (MaskF(val_1_eax) == ShftXF(10) + ShftF(15)) { // Family 19h if (MaskMm(val_1_eax) == ShftXM(1) + ShftM(0)) { static ccstring pkg_type[1<<4] = { NULL, NULL, NULL, NULL, "SP5 (4)" }; use_pkg_type = pkg_type; } else if (MaskMm(val_1_eax) == ShftXM(2) + ShftM(0) || MaskMm(val_1_eax) == ShftXM(5) + ShftM(0)) { static ccstring pkg_type[1<<4] = { NULL, NULL, "AM4 (2)" }; use_pkg_type = pkg_type; } else if (MaskMm(val_1_eax) == ShftXM(6) + ShftM(0)) { static ccstring pkg_type[1<<4] = { NULL, NULL, NULL, NULL, "SP5 (4)" }; use_pkg_type = pkg_type; } else if (MaskMm(val_1_eax) == ShftXM(7) + ShftM(0)) { static ccstring pkg_type[1<<4] = { NULL, NULL, NULL, NULL, "FP7 (4)", "FP7r2 (5)" }; use_pkg_type = pkg_type; } else if (MaskM(val_1_eax) == ShftXM(10) + ShftM(0)) { static ccstring pkg_type[1<<4] = { NULL, NULL, NULL, NULL, "SP5 (4)", NULL, NULL, NULL, "SP6 (8)" }; use_pkg_type = pkg_type; } } else if (MaskF(val_1_eax) == ShftXF(10) + ShftF(15)) { // Family 1Ah if (MaskMm(val_1_eax) == ShftXM(0) + ShftM(0)) { static ccstring pkg_type[1<<4] = { NULL, NULL, NULL, NULL, "SP5 (4)" }; use_pkg_type = pkg_type; } else if (MaskMm(val_1_eax) == ShftXM(4) + ShftM(0)) { static ccstring pkg_type[1<<4] = { NULL, NULL, NULL, NULL, "SP5 (4)" }; use_pkg_type = pkg_type; } } named_item names[] = { { "PkgType", 28, 31, use_pkg_type } }; print_names(value, names, LENGTH(names), /* max_len => */ max_len); } } static void print_80000001_ebx(unsigned int value, vendor_t vendor, unsigned int val_1_eax) { switch (vendor) { case VENDOR_AMD: case VENDOR_HYGON: print_80000001_ebx_amd(value, val_1_eax); break; case VENDOR_INTEL: case VENDOR_CYRIX: case VENDOR_VIA: case VENDOR_TRANSMETA: case VENDOR_UMC: case VENDOR_NEXGEN: case VENDOR_RISE: case VENDOR_SIS: case VENDOR_NSC: case VENDOR_VORTEX: case VENDOR_RDC: case VENDOR_ZHAOXIN: case VENDOR_UNKNOWN: /* DO NOTHING */ break; } } static void print_80000005_eax(unsigned int value) { static named_item names[] = { { "instruction # entries" , 0, 7, NIL_IMAGES }, { "instruction associativity" , 8, 15, NIL_IMAGES }, { "data # entries" , 16, 23, NIL_IMAGES }, { "data associativity" , 24, 31, NIL_IMAGES }, }; printf(" L1 TLB/cache information: 2M/4M pages & L1 TLB" " (0x80000005/eax):\n"); print_names(value, names, LENGTH(names), /* max_len => */ 0); } static void print_80000005_ebx(unsigned int value) { static named_item names[] = { { "instruction # entries" , 0, 7, NIL_IMAGES }, { "instruction associativity" , 8, 15, NIL_IMAGES }, { "data # entries" , 16, 23, NIL_IMAGES }, { "data associativity" , 24, 31, NIL_IMAGES }, }; printf(" L1 TLB/cache information: 4K pages & L1 TLB" " (0x80000005/ebx):\n"); print_names(value, names, LENGTH(names), /* max_len => */ 0); } static void print_80000005_ecx(unsigned int value) { static named_item names[] = { { "line size (bytes)" , 0, 7, NIL_IMAGES }, { "lines per tag" , 8, 15, NIL_IMAGES }, { "associativity" , 16, 23, NIL_IMAGES }, { "size (KB)" , 24, 31, NIL_IMAGES }, }; printf(" L1 data cache information (0x80000005/ecx):\n"); print_names(value, names, LENGTH(names), /* max_len => */ 0); } static void print_80000005_edx(unsigned int value) { static named_item names[] = { { "line size (bytes)" , 0, 7, NIL_IMAGES }, { "lines per tag" , 8, 15, NIL_IMAGES }, { "associativity" , 16, 23, NIL_IMAGES }, { "size (KB)" , 24, 31, NIL_IMAGES }, }; printf(" L1 instruction cache information (0x80000005/edx):\n"); print_names(value, names, LENGTH(names), /* max_len => */ 0); } static ccstring l2_assoc[1<<4] = { "L2 off (0)", "direct mapped (1)", "2-way (2)", "3-way (3)", "4 to 5-way (4)", "6 to 7-way (5)", "8 to 15-way (6)", NULL, "16 to 31-way (8)", NULL, "32 to 47-way (10)", "48 to 63-way (11)", "64 to 95-way (12)", "96 to 127-way (13)", "128 or more-way (14)", "full (15)" }; static void print_80000006_eax(unsigned int value) { static named_item names[] = { { "instruction # entries" , 0, 11, NIL_IMAGES }, { "instruction associativity" , 12, 15, l2_assoc }, { "data # entries" , 16, 27, NIL_IMAGES }, { "data associativity" , 28, 31, l2_assoc }, }; printf(" L2 TLB/cache information: 2M/4M pages & L2 TLB" " (0x80000006/eax):\n"); print_names(value, names, LENGTH(names), /* max_len => */ 0); } static void print_80000006_ebx(unsigned int value) { static named_item names[] = { { "instruction # entries" , 0, 11, NIL_IMAGES }, { "instruction associativity" , 12, 15, l2_assoc }, { "data # entries" , 16, 27, NIL_IMAGES }, { "data associativity" , 28, 31, l2_assoc }, }; printf(" L2 TLB/cache information: 4K pages & L2 TLB (0x80000006/ebx):\n"); print_names(value, names, LENGTH(names), /* max_len => */ 0); } static void print_80000006_ecx(unsigned int value, code_stash_t* stash) { static named_item names[] = { { "line size (bytes)" , 0, 7, NIL_IMAGES }, { "lines per tag" , 8, 11, NIL_IMAGES }, { "associativity" , 12, 15, l2_assoc }, { "size (KB)" , 16, 31, NIL_IMAGES }, }; printf(" L2 unified cache information (0x80000006/ecx):\n"); print_names(value, names, LENGTH(names), /* max_len => */ 0); if (stash) { if (((value >> 12) & 0xf) == 4 && (value >> 16) == 256) { stash->L2_4w_256K = TRUE; } else if (((value >> 12) & 0xf) == 4 && (value >> 16) == 512) { stash->L2_4w_512K = TRUE; } } } static void print_80000006_edx(unsigned int value) { static named_item names[] = { { "line size (bytes)" , 0, 7, NIL_IMAGES }, { "lines per tag" , 8, 11, NIL_IMAGES }, { "associativity" , 12, 15, l2_assoc }, { "size (in 512KB units)" , 18, 31, NIL_IMAGES }, }; printf(" L3 cache information (0x80000006/edx):\n"); print_names(value, names, LENGTH(names), /* max_len => */ 0); } static void print_80000007_ebx(unsigned int value) { static named_item names[] = { { "MCA overflow recovery support" , 0, 0, bools }, { "SUCCOR support" , 1, 1, bools }, { "HWA: hardware assert support" , 2, 2, bools }, { "scalable MCA support" , 3, 3, bools }, }; printf(" RAS Capability (0x80000007/ebx):\n"); print_names(value, names, LENGTH(names), /* max_len => */ 0); } static void print_80000007_ecx(unsigned int value) { static named_item names[] = { { "CmpUnitPwrSampleTimeRatio" , 0, 31, NIL_IMAGES }, }; printf(" Advanced Power Management Features (0x80000007/ecx):\n"); print_names(value, names, LENGTH(names), /* max_len => */ 0); } static void print_80000007_edx(unsigned int value) { static named_item names[] = { { "TS: temperature sensing diode" , 0, 0, bools }, { "FID: frequency ID control" , 1, 1, bools }, { "VID: voltage ID control" , 2, 2, bools }, { "TTP: thermal trip" , 3, 3, bools }, { "TM: thermal monitor" , 4, 4, bools }, { "STC: software thermal control" , 5, 5, bools }, { "100 MHz multiplier control" , 6, 6, bools }, { "hardware P-State control" , 7, 7, bools }, { "TscInvariant" , 8, 8, bools }, { "CPB: core performance boost" , 9, 9, bools }, { "read-only effective frequency interface" , 10, 10, bools }, { "processor feedback interface" , 11, 11, bools }, { "APM power reporting" , 12, 12, bools }, { "connected standby" , 13, 13, bools }, { "RAPL: running average power limit" , 14, 14, bools }, { "fast CPPC" , 15, 15, bools }, }; printf(" Advanced Power Management Features (0x80000007/edx):\n"); print_names(value, names, LENGTH(names), /* max_len => */ 0); } static void print_80000008_eax(unsigned int value) { static named_item names[] = { { "maximum physical address bits" , 0, 7, NIL_IMAGES }, { "maximum linear (virtual) address bits" , 8, 15, NIL_IMAGES }, { "maximum guest physical address bits" , 16, 23, NIL_IMAGES }, }; printf(" Physical Address and Linear Address Size (0x80000008/eax):\n"); print_names(value, names, LENGTH(names), /* max_len => */ 0); } static void print_80000008_ebx(unsigned int value, const code_stash_t* stash) { static named_item names[] = { { "CLZERO instruction" , 0, 0, bools }, { "instructions retired count support" , 1, 1, bools }, { "always save/restore error pointers" , 2, 2, bools }, { "INVLPGB instruction" , 3, 3, bools }, { "RDPRU instruction" , 4, 4, bools }, { "memory bandwidth enforcement" , 6, 6, bools }, { "MCOMMIT instruction" , 8, 8, bools }, { "WBNOINVD instruction" , 9, 9, bools }, { "IBPB: indirect branch prediction barrier", 12, 12, bools }, { "interruptible WBINVD, WBNOINVD" , 13, 13, bools }, { "IBRS: indirect branch restr speculation" , 14, 14, bools }, { "STIBP: 1 thr indirect branch predictor" , 15, 15, bools }, { "CPU prefers: IBRS always on" , 16, 16, bools }, { "CPU prefers: STIBP always on" , 17, 17, bools }, { "IBRS preferred over software solution" , 18, 18, bools }, { "IBRS provides same mode protection" , 19, 19, bools }, { "EFER[LMSLE] not supported" , 20, 20, bools }, { "INVLPGB supports TLB flush guest nested" , 21, 21, bools }, { "ppin processor id number supported" , 23, 23, bools }, // Xen* { "SSBD: speculative store bypass disable" , 24, 24, bools }, { "virtualized SSBD" , 25, 25, bools }, { "SSBD fixed in hardware" , 26, 26, bools }, { "CPPC: collaborative processor perf ctrl" , 27, 27, bools }, { "PSFD: predictive store forward disable" , 28, 28, bools }, { "not vulnerable to branch type confusion" , 29, 29, bools }, { "IBPB_RET: ret addr predictor cleared" , 30, 30, bools }, { "branch sampling feature support" , 31, 31, bools }, }; printf(" Extended Feature Extensions ID (0x80000008/ebx):\n"); print_names(value, names, LENGTH(names), /* max_len => */ 0); if (stash) { boolean not_vuln_BTC = (BIT_EXTRACT_LE(value, 29, 30) || Synth_Family(stash->val_80000001_eax) == 0x19); printf(" (vuln to branch type confusion synth) = %s\n", bools[!not_vuln_BTC]); } } static void print_80000008_ecx(unsigned int value) { static ccstring tscSize[1<<2] = { "40 bits (0)", "48 bits (1)", "56 bits (2)", "64 bits (3)" }; static named_item names[] = { // bit field 0, 7 is reported by caller { "ApicIdCoreIdSize" , 12, 15, NIL_IMAGES }, { "performance time-stamp counter size" , 16, 17, tscSize }, }; print_names(value, names, LENGTH(names), /* max_len => */ 0); } static void print_80000008_edx(unsigned int value) { static named_item names[] = { { "max page count for INVLPGB instruction" , 0, 15, NIL_IMAGES }, { "RDPRU instruction max input support" , 16, 23, NIL_IMAGES }, }; printf(" Feature Extended Size (0x80000008/edx):\n"); print_names(value, names, LENGTH(names), /* max_len => */ 0); } static void print_8000000a_eax(unsigned int value) { static named_item names[] = { { "SvmRev: SVM revision" , 0, 7, NIL_IMAGES }, }; printf(" SVM Secure Virtual Machine (0x8000000a/eax):\n"); print_names(value, names, LENGTH(names), /* max_len => */ 0); } static void print_8000000a_edx(unsigned int value) { static named_item names[] = { { "nested paging" , 0, 0, bools }, { "LBR virtualization" , 1, 1, bools }, { "SVM lock" , 2, 2, bools }, { "NRIP save" , 3, 3, bools }, { "MSR based TSC rate control" , 4, 4, bools }, { "VMCB clean bits support" , 5, 5, bools }, { "flush by ASID" , 6, 6, bools }, { "decode assists" , 7, 7, bools }, { "PMC virtualization" , 8, 8, bools }, { "SSSE3/SSE5 opcode set disable" , 9, 9, bools }, { "pause intercept filter" , 10, 10, bools }, { "pause filter threshold" , 12, 12, bools }, { "AVIC: AMD virtual interrupt controller" , 13, 13, bools }, { "virtualized VMLOAD/VMSAVE" , 15, 15, bools }, { "virtualized global interrupt flag (GIF)" , 16, 16, bools }, { "GMET: guest mode execute trap" , 17, 17, bools }, { "X2AVIC: virtualized X2APIC" , 18, 18, bools }, { "supervisor shadow stack" , 19, 19, bools }, { "guest Spec_ctl support" , 20, 20, bools }, { "ROGPT: read-only guest page table" , 21, 21, bools }, { "host MCE override" , 23, 23, bools }, { "INVLPGB/TLBSYNC hyperv interc enable" , 24, 24, bools }, { "VNMI: NMI virtualization" , 25, 25, bools }, { "IBS virtualization" , 26, 26, bools }, { "extended LVT AVIC access changes" , 27, 27, bools }, { "guest VMCB addr check" , 28, 28, bools }, { "bus lock threshold" , 29, 29, bools }, { "idlt HLT intercept" , 30, 30, bools }, { "EXITINFO1 non-interceptible shutdown" , 31, 31, bools }, }; printf(" SVM Secure Virtual Machine (0x8000000a/edx):\n"); print_names(value, names, LENGTH(names), /* max_len => */ 0); } static void print_8000000a_ebx(unsigned int value) { printf(" NASID: number of address space identifiers = 0x%x (%u):\n", value, value); } static void print_80000019_eax(unsigned int value) { static named_item names[] = { { "instruction # entries" , 0, 11, NIL_IMAGES }, { "instruction associativity" , 12, 15, l2_assoc }, { "data # entries" , 16, 27, NIL_IMAGES }, { "data associativity" , 28, 31, l2_assoc }, }; printf(" L1 TLB information: 1G pages (0x80000019/eax):\n"); print_names(value, names, LENGTH(names), /* max_len => */ 0); } static void print_80000019_ebx(unsigned int value) { static named_item names[] = { { "instruction # entries" , 0, 11, NIL_IMAGES }, { "instruction associativity" , 12, 15, l2_assoc }, { "data # entries" , 16, 27, NIL_IMAGES }, { "data associativity" , 28, 31, l2_assoc }, }; printf(" L2 TLB information: 1G pages (0x80000019/ebx):\n"); print_names(value, names, LENGTH(names), /* max_len => */ 0); } static void print_8000001a_eax(unsigned int value) { static named_item names[] = { { "128-bit SSE executed full-width" , 0, 0, bools }, { "MOVU* better than MOVL*/MOVH*" , 1, 1, bools }, { "256-bit SSE executed full-width" , 2, 2, bools }, { "512-bit SSE executed full-width" , 3, 3, bools }, }; printf(" Performance Optimization Identifiers (0x8000001a/eax):\n"); print_names(value, names, LENGTH(names), /* max_len => */ 0); } static void print_8000001b_eax(unsigned int value) { static named_item names[] = { { "IBS feature flags valid" , 0, 0, bools }, { "IBS fetch sampling" , 1, 1, bools }, { "IBS execution sampling" , 2, 2, bools }, { "read write of op counter" , 3, 3, bools }, { "op counting mode" , 4, 4, bools }, { "branch target address reporting" , 5, 5, bools }, { "IbsOpCurCnt and IbsOpMaxCnt extend 7" , 6, 6, bools }, { "invalid RIP indication support" , 7, 7, bools }, { "fused branch micro-op indication support", 8, 8, bools }, { "IBS fetch control extended MSR support" , 9, 9, bools }, { "IBS op data 4 MSR support" , 10, 10, bools }, { "IBS L3 miss filtering support" , 11, 11, bools }, { "IBS load latency filtering support" , 12, 12, bools }, { "simplified DTLB page size & miss report" , 19, 19, bools }, }; printf(" Instruction Based Sampling Identifiers (0x8000001b/eax):\n"); print_names(value, names, LENGTH(names), /* max_len => */ 0); } static void print_8000001c_eax(unsigned int value) { static named_item names[] = { { "lightweight profiling" , 0, 0, bools }, { "LWPVAL instruction" , 1, 1, bools }, { "instruction retired event" , 2, 2, bools }, { "branch retired event" , 3, 3, bools }, { "DC miss event" , 4, 4, bools }, { "core clocks not halted event" , 5, 5, bools }, { "core reference clocks not halted event" , 6, 6, bools }, { "continuous mode sampling" , 29, 29, bools }, { "tsc in event record" , 30, 30, bools }, { "interrupt on threshold overflow" , 31, 31, bools }, }; printf(" Lightweight Profiling Capabilities: Availability" " (0x8000001c/eax):\n"); print_names(value, names, LENGTH(names), /* max_len => */ 0); } static void print_8000001c_ebx(unsigned int value) { static named_item names[] = { { "LWPCB byte size" , 0, 7, NIL_IMAGES }, { "event record byte size" , 8, 15, NIL_IMAGES }, { "maximum EventId" , 16, 23, NIL_IMAGES }, { "EventInterval1 field offset" , 24, 31, NIL_IMAGES }, }; printf(" Lightweight Profiling Capabilities (0x8000001c/ebx):\n"); print_names(value, names, LENGTH(names), /* max_len => */ 0); } static void print_8000001c_ecx(unsigned int value) { static named_item names[] = { { "latency counter bit size" , 0, 4, NIL_IMAGES }, { "data cache miss address valid" , 5, 5, bools }, { "amount cache latency is rounded" , 6, 8, NIL_IMAGES }, { "LWP implementation version" , 9, 15, NIL_IMAGES }, { "event ring buffer size in records" , 16, 23, NIL_IMAGES }, { "branch prediction filtering" , 28, 28, bools }, { "IP filtering" , 29, 29, bools }, { "cache level filtering" , 30, 30, bools }, { "cache latency filteing" , 31, 31, bools }, }; printf(" Lightweight Profiling Capabilities (0x8000001c/ecx):\n"); print_names(value, names, LENGTH(names), /* max_len => */ 0); } static void print_8000001c_edx(unsigned int value) { static named_item names[] = { { "lightweight profiling" , 0, 0, bools }, { "LWPVAL instruction" , 1, 1, bools }, { "instruction retired event" , 2, 2, bools }, { "branch retired event" , 3, 3, bools }, { "DC miss event" , 4, 4, bools }, { "core clocks not halted event" , 5, 5, bools }, { "core reference clocks not halted event" , 6, 6, bools }, { "continuous mode sampling" , 29, 29, bools }, { "tsc in event record" , 30, 30, bools }, { "interrupt on threshold overflow" , 31, 31, bools }, }; printf(" Lightweight Profiling Capabilities: Supported" " (0x8000001c/edx):\n"); print_names(value, names, LENGTH(names), /* max_len => */ 0); } static void print_8000001d_eax(unsigned int value) { static ccstring cache_type[1<<5] = { "no more caches (0)", "data (1)", "instruction (2)", "unified (3)" }; static named_item names[] = { { "type" , 0, 4, cache_type }, { "level" , 5, 7, NIL_IMAGES }, { "self-initializing" , 8, 8, bools }, { "fully associative" , 9, 9, bools }, { "extra cores sharing this cache" , 14, 25, NIL_IMAGES }, }; print_names(value, names, LENGTH(names), /* max_len => */ 31); } static void print_8000001d_ebx(unsigned int value) { static named_item names[] = { { "line size in bytes" , 0, 11, MINUS1_IMAGES }, { "physical line partitions" , 12, 21, MINUS1_IMAGES }, { "number of ways" , 22, 31, MINUS1_IMAGES }, }; print_names(value, names, LENGTH(names), /* max_len => */ 31); } static void print_8000001d_edx(unsigned int value) { static named_item names[] = { { "write-back invalidate" , 0, 0, bools }, { "cache inclusive of lower levels" , 1, 1, bools }, }; print_names(value, names, LENGTH(names), /* max_len => */ 31); } static void print_8000001d_synth(const unsigned int words[]) { unsigned int ways_assoc = BIT_EXTRACT_LE(words[WORD_EBX], 22, 32) + 1; unsigned int parts = BIT_EXTRACT_LE(words[WORD_EBX], 12, 22) + 1; unsigned int line_size = BIT_EXTRACT_LE(words[WORD_EBX], 0, 12) + 1; unsigned int sets = words[WORD_ECX] + 1; unsigned int size = (ways_assoc * parts * line_size * sets); printf(" (synth size) = %u", size); if (size > 1048576) { if ((size % 1048576) == 0) { printf(" (%u MB)", size / 1048576); } else { printf(" (%.1f MB)", ((float)size) / 1048576.0); } } else if (size > 1024) { if ((size % 1024) == 0) { printf(" (%u KB)", size / 1024); } else { printf(" (%.1f KB)", ((float)size) / 1024.0); } } printf("\n"); } static void print_8000001e_ebx_f16(unsigned int value) { static named_item names[] = { { "compute unit ID" , 0, 7, NIL_IMAGES }, { "cores per compute unit" , 8, 9, MINUS1_IMAGES }, }; printf(" Compute Unit Identifiers (0x8000001e/ebx):\n"); print_names(value, names, LENGTH(names), /* max_len => */ 0); } static void print_8000001e_ebx_gt_f16(unsigned int value) { static named_item names[] = { { "core ID" , 0, 7, NIL_IMAGES }, { "threads per core" , 8, 15, MINUS1_IMAGES }, }; printf(" Core Identifiers (0x8000001e/ebx):\n"); print_names(value, names, LENGTH(names), /* max_len => */ 0); } static void print_8000001e_ecx(unsigned int value) { static named_item names[] = { { "node ID" , 0, 7, NIL_IMAGES }, { "nodes per processor" , 8, 10, MINUS1_IMAGES }, }; printf(" Node Identifiers (0x8000001e/ecx):\n"); print_names(value, names, LENGTH(names), /* max_len => */ 0); } static void print_8000001f_eax(unsigned int value) { static named_item names[] = { { "SME: secure memory encryption support" , 0, 0, bools }, { "SEV: secure encrypted virtualize support", 1, 1, bools }, { "VM page flush MSR support" , 2, 2, bools }, { "SEV-ES: SEV encrypted state support" , 3, 3, bools }, { "SEV-SNP: SEV secure nested paging" , 4, 4, bools }, { "VMPL: VM permission levels" , 5, 5, bools }, { "RMPQUERY instruction support" , 6, 6, bools }, { "VMPL supervisor shadow stack support" , 7, 7, bools }, { "Secure TSC supported" , 8, 8, bools }, { "virtual TSC_AUX supported" , 9, 9, bools }, { "hardware cache coher across enc domains" , 10, 10, bools }, { "SEV guest exec only from 64-bit host" , 11, 11, bools }, { "restricted injection" , 12, 12, bools }, { "alternate injection" , 13, 13, bools }, { "full debug state swap for SEV-ES/SEV-SNP", 14, 14, bools }, { "disallowing IBS use by host" , 15, 15, bools }, { "VTE: SEV virtual transparent encryption" , 16, 16, bools }, { "VMGEXIT parameter support" , 17, 17, bools }, { "virtual TOM MSR support" , 18, 18, bools }, { "IBS virtual support for SEV-ES/SEV-SNP" , 19, 19, bools }, { "PMC virtual support for SEV-ES/SEV-SNP" , 20, 20, bools }, { "RMPREAD instruction" , 21, 21, bools }, { "guest intercept control support" , 22, 22, bools }, { "segmented RMP support" , 23, 23, bools }, { "VMSA register protection support" , 24, 24, bools }, { "SMT protection support" , 25, 25, bools }, { "secure AVIC support" , 26, 26, bools }, { "allowed SEV features support" , 27, 27, bools }, { "SVSM communication page MSR support" , 28, 28, bools }, { "VIRT_RMPUPDATE & VIRT_PSMASH MSR support", 29, 29, bools }, { "write to hypervisor in-used allowed" , 30, 30, bools }, { "IBPB on entry support" , 31, 31, bools }, }; print_names(value, names, LENGTH(names), /* max_len => */ 40); } static void print_8000001f_ebx(unsigned int value) { static named_item names[] = { { "encryption bit position in PTE" , 0, 5, NIL_IMAGES }, { "physical address space width reduction" , 6, 11, NIL_IMAGES }, { "number of VM permission levels" , 12, 15, NIL_IMAGES }, }; print_names(value, names, LENGTH(names), /* max_len => */ 40); } static void print_80000020_0_ebx(unsigned int value) { static named_item names[] = { { "L3 bandwidth enforcement" , 1, 1, bools }, { "L3 slow memory bandwidth enforcement" , 2, 2, bools }, { "bandwidth monitoring event configuration", 3, 3, bools }, { "L3 range reservation support" , 4, 4, bools }, { "assignable bandwidth monitoring counters", 5, 5, bools }, { "SDCI allocation enforcement" , 6, 6, bools }, }; print_names(value, names, LENGTH(names), /* max_len => */ 0); } static void print_80000020_3_ebx(unsigned int value) { static named_item names[] = { { "number of bandwidth events available" , 0, 7, NIL_IMAGES }, }; print_names(value, names, LENGTH(names), /* max_len => */ 38); } static void print_80000020_3_ecx(unsigned int value) { static named_item names[] = { { "reads to local NUMA" , 0, 0, bools }, { "reads to non-local NUMA" , 1, 1, bools }, { "non-temporal writes to local NUMA" , 2, 2, bools }, { "non-temporal writes to non-local NUMA" , 3, 3, bools }, { "reads to slow memory in local NUMA" , 4, 4, bools }, { "reads to slow memory in non-local NUMA" , 5, 5, bools }, { "dirty victims writes" , 6, 6, bools }, }; print_names(value, names, LENGTH(names), /* max_len => */ 38); } static void print_80000020_5_eax(unsigned int value) { static named_item names[] = { { "QM_CTR counter size-24" , 0, 7, NIL_IMAGES }, { "QM_CTR bit 61 is overflow" , 8, 8, bools }, }; print_names(value, names, LENGTH(names), /* max_len => */ 33); unsigned int counter_size_raw = BIT_EXTRACT_LE(value, 0, 8); unsigned int counter_size; if (counter_size_raw == 0) { counter_size = 0; } else { counter_size = 24 + counter_size_raw; } if (counter_size != 0) { printf(" (QM_CTR counter size) = %u\n", counter_size); } } static void print_80000020_5_ebx(unsigned int value) { static named_item names[] = { { "maximum supported ABCM counter ID" , 0, 15, NIL_IMAGES }, }; print_names(value, names, LENGTH(names), /* max_len => */ 33); } static void print_80000020_5_ecx(unsigned int value) { static named_item names[] = { { "can measure COS bandwidth" , 0, 0, bools }, }; print_names(value, names, LENGTH(names), /* max_len => */ 33); } static void print_80000021_eax(unsigned int value) { static named_item names[] = { { "no nested data-breakpoints" , 0, 0, bools }, { "FsGsKernelGsBaseNonSerializing" , 1, 1, bools }, { "LFENCE always serializing" , 2, 2, bools }, { "SMM paging configuration lock support" , 3, 3, bools }, { "null selector clears base" , 6, 6, bools }, { "upper address ignore support" , 7, 7, bools }, { "automatic IBRS" , 8, 8, bools }, { "SMM_CTL MSR not supported" , 9, 9, bools }, { "FSRS: fast short REP STOSB support" , 10, 10, bools }, { "FSRC: fast short REP CMPSB support" , 11, 11, bools }, { "prefetch control MSR support" , 13, 13, bools }, { "L2TLB sizes are multiples of 32" , 14, 14, bools }, { "AMD enhanced REP MOVSB/STOSB" , 15, 15, bools }, { "reserves 0F 01/7 for AMD use" , 16, 16, bools }, { "CPUID disable for non-privileged" , 17, 17, bools }, { "enhanced predictive store forwarding" , 18, 18, bools }, { "fast short REP SCASB support" , 19, 19, bools }, { "IC PREFETCH support" , 20, 20, bools }, { "FP512 to FP256 downgrade support" , 21, 21, bools }, { "workload OS feedback support" , 22, 22, bools }, { "ret addr predictor security support" , 24, 24, bools }, { "guest: selective branch pred barrier" , 27, 27, bools }, { "guest: PRED_CMD[IBPB] flushes br predict", 28, 28, bools }, { "unaffected by spec return stack overflow", 29, 29, bools }, { "unaffected by SRSO at user-kernel bound" , 30, 30, bools }, { "BP_CFG can mitigate other SRSO cases" , 31, 31, bools }, }; print_names(value, names, LENGTH(names), /* max_len => */ 0); } static void print_80000021_ebx(unsigned int value) { unsigned int ups = BIT_EXTRACT_LE(value, 0, 12) * 16; printf(" microcode patch size = "); if (ups == 0) { printf("<= 0x15c0 (5568) (legacy value)\n"); } else { printf("%u (0x%0x)\n", ups, ups); } unsigned int raps = BIT_EXTRACT_LE(value, 16, 24) * 8; printf(" return addr predictor size = %u (0x%0x)\n", raps, raps); } static void print_80000022_eax(unsigned int value) { static named_item names[] = { { "AMD performance monitoring V2" , 0, 0, bools }, { "AMD LBR V2" , 1, 1, bools }, { "AMD LBR stack & PMC freezing" , 2, 2, bools }, }; print_names(value, names, LENGTH(names), /* max_len => */ 37); } static void print_80000022_ebx(unsigned int value) { static named_item names[] = { { "number of core perf ctrs" , 0, 3, NIL_IMAGES }, { "number of LBR stack entries" , 4, 9, NIL_IMAGES }, { "number of avail Northbridge perf ctrs" , 10, 15, NIL_IMAGES }, { "number of available UMC PMCs" , 16, 23, NIL_IMAGES }, }; print_names(value, names, LENGTH(names), /* max_len => */ 37); } static void print_80000023_eax(unsigned int value) { static named_item names[] = { { "secure host multi-key memory support" , 0, 0, bools }, }; print_names(value, names, LENGTH(names), /* max_len => */ 36); } static void print_80000023_ebx(unsigned int value) { static named_item names[] = { { "number of encryption key IDs" , 0, 15, NIL_IMAGES }, }; print_names(value, names, LENGTH(names), /* max_len => */ 36); } static void print_80000025_eax(unsigned int value) { static named_item names[] = { { "RMP segment size minimum supported" , 0, 5, NIL_IMAGES }, { "RMP segment size maximum supported" , 6, 11, NIL_IMAGES }, }; print_names(value, names, LENGTH(names), /* max_len => */ 34); } static void print_80000025_ebx(unsigned int value) { static named_item names[] = { { "cacheable RMP segment definitions" , 0, 9, NIL_IMAGES }, { "cached segments hard limit" , 11, 11, bools }, }; print_names(value, names, LENGTH(names), /* max_len => */ 34); } static void print_80000026_eax(unsigned int value) { static named_item names[] = { { "bit width of level" , 0, 4, NIL_IMAGES }, { "power efficiency ranking available" , 29, 29, bools }, { "cores heterogeneous at this level" , 30, 30, bools }, { "components have varying number of cores" , 31, 31, bools }, }; print_names(value, names, LENGTH(names), /* max_len => */ 39); } static void print_80000026_1_ebx(unsigned int value) { // These strings are from 55901 for Raphael. Is it possible they will differ // on other uarch's? static ccstring native_model[1<<4] = { "Zen4 (0)" }; static ccstring core_type[1<<4] = { "performance (0)", "efficiency (1)" }; static named_item names[] = { { "number of logical processors at level" , 0, 15, NIL_IMAGES }, { "power efficiency ranking" , 16, 23, NIL_IMAGES }, { "native model ID" , 24, 27, native_model }, { "core type" , 28, 31, core_type }, }; print_names(value, names, LENGTH(names), /* max_len => */ 39); } static void print_80000026_n_ebx(unsigned int value) { static named_item names[] = { { "number of logical processors at level" , 0, 15, NIL_IMAGES }, }; print_names(value, names, LENGTH(names), /* max_len => */ 39); } static void print_80000026_ecx(unsigned int value) { static ccstring level_type[1<<8] = { "invalid (0)", "core (1)", "complex (2)", "die (3)", "socket (4)" }; static named_item names[] = { { "level number" , 0, 7, NIL_IMAGES }, { "level type" , 8, 15, level_type }, }; print_names(value, names, LENGTH(names), /* max_len => */ 39); } static void print_80860001_eax(unsigned int value, const print_opts_t* opts) { static named_item names[] = { { "generation" , 8, 11, NIL_IMAGES }, { "model" , 4, 7, NIL_IMAGES }, { "stepping" , 0, 3, NIL_IMAGES }, }; printf(" Transmeta processor signature (0x80860001/eax):\n"); print_names(value, names, LENGTH(names), /* max_len => */ 0); if (opts->simple) { ccstring synth = decode_synth_transmeta(value, NULL); printf(" (simple synth) = "); if (synth != NULL) { printf("%s", synth); } printf("\n"); } } static void print_80860001_edx(unsigned int value) { static named_item names[] = { { "recovery CMS active" , 0, 0, bools }, { "LongRun" , 1, 1, bools }, { "LongRun Table Interface LRTI (CMS 4.2)" , 3, 3, bools }, { "persistent translation technology 1.x" , 7, 7, bools }, { "persistent translation technology 2.0" , 8, 8, bools }, { "processor break events" , 12, 12, bools }, }; printf(" Transmeta feature flags (0x80860001/edx):\n"); print_names(value, names, LENGTH(names), /* max_len => */ 0); } static void print_transmeta_proc_rev_meaning(unsigned int proc_rev) { switch (proc_rev & 0xffff0000) { case 0x01010000: printf("(TM3200)"); break; case 0x01020000: printf("(TM5400)"); break; case 0x01030000: if ((proc_rev & 0xffffff00) == 0x00000000) { printf("(TM5400 / TM5600)"); } else { printf("(unknown)"); } break; case 0x01040000: case 0x01050000: printf("(TM5500 / TM5800)"); break; default: printf("(unknown)"); break; } } static void print_80860001_ebx_ecx(unsigned int val_ebx, unsigned int val_ecx) { printf(" Transmeta processor revision (0x80000001/edx)" " = %u.%u-%u.%u-%u ", (val_ebx >> 24) & 0xff, (val_ebx >> 16) & 0xff, (val_ebx >> 8) & 0xff, (val_ebx >> 0) & 0xff, val_ecx); if (val_ebx == 0x20000000) { printf("(see 80860002/eax)"); } else { print_transmeta_proc_rev_meaning(val_ebx); } printf("\n"); } static void print_80860002_eax(unsigned int value, code_stash_t* stash) { if (stash->transmeta_proc_rev == 0x02000000) { printf(" Transmeta processor revision (0x80860002/eax)" " = %u.%u-%u.%u ", (value >> 24) & 0xff, (value >> 16) & 0xff, (value >> 8) & 0xff, (value >> 0) & 0xff); print_transmeta_proc_rev_meaning(value); printf("\n"); if (stash) { stash->transmeta_proc_rev = value; } } } static void print_c0000001_edx(unsigned int value) { static named_item names[] = { { "alternate instruction set" , 0, 0, bools }, // sandpile.org { "alternate instruction set enabled" , 1, 1, bools }, // sandpile.org { "random number generator" , 2, 2, bools }, { "random number generator enabled" , 3, 3, bools }, { "LongHaul MSR 0000_110Ah" , 4, 4, bools }, // sandpile.org { "FEMMS" , 5, 5, bools }, // sandpile.org { "advanced cryptography engine (ACE)" , 6, 6, bools }, { "advanced cryptography engine (ACE)enabled", 7, 7, bools }, { "montgomery multiplier/hash (ACE2)" , 8, 8, bools }, { "montgomery multiplier/hash (ACE2) enabled", 9, 9, bools }, { "padlock hash engine (PHE)" , 10, 10, bools }, { "padlock hash engine (PHE) enabled" , 11, 11, bools }, { "padlock montgomery mult. (PMM)" , 12, 12, bools }, // LX* { "padlock montgomery mult. (PMM) enabled" , 13, 13, bools }, // LX* }; printf(" extended feature flags (0xc0000001/edx):\n"); print_names(value, names, LENGTH(names), /* max_len => */ 0); } static void print_c0000002_ebx(unsigned int value) { printf(" input voltage (mV) = %d (0x%0x)\n", (BIT_EXTRACT_LE(value, 0, 8) << 4) + 700, BIT_EXTRACT_LE(value, 0, 8)); static named_item names[] = { { "current clock multipler" , 8, 15, NIL_IMAGES }, { "clock ratio transition in progress" , 16, 16, bools }, { "voltage transition in progress" , 17, 17, bools }, { "thermal monitor 2 transition" , 18, 18, bools }, { "thermal monitor 2 transition" , 19, 19, bools }, { "performance control MSR transition" , 20, 21, NIL_IMAGES }, { "lowest clock ratio" , 24, 31, NIL_IMAGES }, }; print_names(value, names, LENGTH(names), /* max_len => */ 34); } static void print_c0000002_ecx(unsigned int value) { printf(" highest voltage (mV) = %d (0x%0x)\n", (BIT_EXTRACT_LE(value, 0, 8) << 4) + 700, BIT_EXTRACT_LE(value, 0, 8)); printf(" lowest voltage (mV) = %d (0x%0x)\n", (BIT_EXTRACT_LE(value, 16, 24) << 4) + 700, BIT_EXTRACT_LE(value, 16, 24)); static named_item names[] = { { "highest clock multiplier" , 8, 15, NIL_IMAGES }, { "lowest clock multiplier" , 24, 31, NIL_IMAGES }, }; print_names(value, names, LENGTH(names), /* max_len => */ 34); } static void print_c0000002_edx(unsigned int value) { static ccstring mb_reset[1<<1] = { "0xffffffff (0)", "0x000ffff0 (1)" }; static ccstring bus_clock[1<<2] = { "100 MHz (0)", "133 MHz (1)", "200 MHz (2)", "166 MHz (3)" }; static named_item names[] = { { "MB reset vector" , 14, 14, mb_reset }, { "APIC cluster ID" , 16, 17, NIL_IMAGES }, { "input front side bus clock" , 16, 17, bus_clock }, { "APIC agent ID" , 20, 21, NIL_IMAGES }, { "current clock multiplier" , 22, 26, NIL_IMAGES }, }; print_names(value, names, LENGTH(names), /* max_len => */ 34); } static void print_c0000004_eax(unsigned int value) { static named_item names[] = { { "thermal monitor temperature" , 0, 7, NIL_IMAGES }, }; print_names(value, names, LENGTH(names), /* max_len => */ 0); } static void print_c0000004_ebx(unsigned int value) { printf(" current voltage (mV) = %d (0x%0x)\n", (BIT_EXTRACT_LE(value, 0, 8) << 4) + 700, BIT_EXTRACT_LE(value, 0, 8)); // This is a mirror of MSR 198h [31:0] // If it had been read via rdmsr, this would be eax. static named_item names[] = { { "current clock ratio" , 8, 15, X2_IMAGES }, { "clock ratio transition in progress" , 16, 16, bools }, { "voltage transition in progress" , 17, 17, bools }, { "thermal monitor 2 transition in progress", 18, 18, NIL_IMAGES }, { "thermal monitor 2 transition in progress", 19, 19, NIL_IMAGES }, { "IA32_PERF_CTL transition in progress" , 20, 20, NIL_IMAGES }, { "IA32_PERF_CTL transition in progress" , 21, 21, NIL_IMAGES }, { "lowest clock ratio" , 24, 30, X2_IMAGES }, { "XE operation (R/O)" , 31, 31, bools }, }; print_names(value, names, LENGTH(names), /* max_len => */ 40); } static void print_c0000004_ecx(unsigned int value) { // This is a mirror of MSR 198h [63:32] // If it had been read via rdmsr, this would be edx. static named_item names[] = { { "highest supported voltage" , 0, 7, NIL_IMAGES }, { "highest supported clock ratio" , 8, 15, X2_IMAGES }, { "lowest supported voltage" , 16, 23, NIL_IMAGES }, { "lowest supported clock ratio" , 24, 31, X2_IMAGES }, }; print_names(value, names, LENGTH(names), /* max_len => */ 40); } static void usage(void) { printf("usage: %s [options...]\n", program); printf("\n"); printf("Dump detailed information about the CPU(s) gathered from the CPUID" " instruction,\n"); printf("and also determine the exact model of CPU(s).\n"); printf("\n"); printf("options:\n"); printf("\n"); printf(" -1, --one-cpu display information only for the current" " CPU\n"); printf(" -f FILE, --file=FILE read raw hex information (-r output) from" " FILE instead\n"); printf(" of from executions of the cpuid" " instruction.\n"); printf(" If FILE is '-', read from stdin.\n"); printf(" -l V, --leaf=V display information for the single specified" " leaf.\n"); printf(" If -s/--subleaf is not specified, 0 is" " assumed.\n"); printf(" NOTE: If a leaf cannot be interpreted" " in isolation, it\n"); printf(" will be displayed as raw hex.\n"); printf(" -s V, --subleaf=V display information for the single specified" " subleaf.\n"); printf(" It requires -l/--leaf.\n"); printf(" -h, -H, --help display this help information\n"); printf(" -i, --inst use the CPUID instruction: The information" " it provides\n"); printf(" is reliable. It is not necessary to" " be root.\n"); printf(" (This option is the default.)\n"); #ifdef USE_CPUID_MODULE printf(" -k, --kernel use the CPUID kernel module: The" " information does not\n"); printf(" seem to be reliable on all combinations of" " CPU type\n"); printf(" and kernel version. Typically, it is" " necessary to be\n"); printf(" root.\n"); #endif printf(" -r, --raw display raw hex information with no" " decoding\n"); printf(" -S, --simple display (simple synth), based on only" " single leaves\n"); printf(" -v, --version display cpuid version\n"); printf("\n"); exit(1); } #ifdef USE_CPUID_MODULE static void explain_dev_cpu_errno(void) { if (errno == ENODEV || errno == ENXIO) { fprintf(stderr, "%s: if running a modular kernel, execute" " \"modprobe cpuid\",\n", program); fprintf(stderr, "%s: wait a few seconds, and then try again\n", program); fprintf(stderr, "%s: or consider using the -i option\n", program); } else if (errno == ENOENT) { fprintf(stderr, "%s: if running a modular kernel, execute" " \"modprobe cpuid\",\n", program); fprintf(stderr, "%s: wait a few seconds, and then try again;\n", program); fprintf(stderr, "%s: if it still fails, try executing:\n", program); fprintf(stderr, "%s: mknod /dev/cpu/0/cpuid c %u 0\n", program, CPUID_MAJOR); fprintf(stderr, "%s: mknod /dev/cpu/1/cpuid c %u 1\n", program, CPUID_MAJOR); fprintf(stderr, "%s: etc.\n", program); fprintf(stderr, "%s: and then try again\n", program); fprintf(stderr, "%s: or consider using the -i option\n", program); } else if ((errno == EPERM || errno == EACCES) && getuid() != 0) { fprintf(stderr, "%s: on most systems," " it is necessary to execute this as root\n", program); fprintf(stderr, "%s: or consider using the -i option\n", program); } exit(1); } #endif #define IS_HYPERVISOR_LEAF(reg, want) \ (0x4000000 <= (reg) && (reg) < 0x40010000 && ((reg) & 0xff) == (want)) #define FOUR_CHARS_VALUE(s) \ ((unsigned int)((s)[0] + ((s)[1] << 8) + ((s)[2] << 16) + ((s)[3] << 24))) #define IS_VENDOR_ID(words, s) \ ( (words)[WORD_EBX] == FOUR_CHARS_VALUE(&(s)[0]) \ && (words)[WORD_EDX] == FOUR_CHARS_VALUE(&(s)[4]) \ && (words)[WORD_ECX] == FOUR_CHARS_VALUE(&(s)[8])) #define IS_HYPERVISOR_ID(words, s) \ ( (words)[WORD_EBX] == FOUR_CHARS_VALUE(&(s)[0]) \ && (words)[WORD_ECX] == FOUR_CHARS_VALUE(&(s)[4]) \ && (words)[WORD_EDX] == FOUR_CHARS_VALUE(&(s)[8])) static hypervisor_t get_hypervisor (const unsigned int words[WORD_NUM]) { if (IS_HYPERVISOR_ID(words, "VMwareVMware")) { return HYPERVISOR_VMWARE; } else if (IS_HYPERVISOR_ID(words, "XenVMMXenVMM")) { return HYPERVISOR_XEN; } else if (IS_HYPERVISOR_ID(words, "KVMKVMKVM\0\0\0")) { return HYPERVISOR_KVM; } else if (IS_HYPERVISOR_ID(words, "Microsoft Hv")) { return HYPERVISOR_MICROSOFT; } else if (IS_HYPERVISOR_ID(words, "ACRNACRNACRN")) { return HYPERVISOR_ACRN; } else { return HYPERVISOR_UNKNOWN; } } static void print_esc_substring (const char* str, unsigned int len) { unsigned int i = 0; for (; i < len; i++) { unsigned char c = ((const unsigned char*)str)[i]; if (isgraph(c) || (c) == ' ') { putchar(c); } else { printf("\\%o", c); } } } static void print_reg_raw (unsigned int reg, unsigned int sub, const unsigned int words[WORD_NUM]) { printf(" 0x%08x 0x%02x: eax=0x%08x ebx=0x%08x ecx=0x%08x edx=0x%08x\n", reg, sub, words[WORD_EAX], words[WORD_EBX], words[WORD_ECX], words[WORD_EDX]); } static void print_reg (unsigned int reg, unsigned int sub, const unsigned int words[WORD_NUM], const print_opts_t* opts, code_stash_t* stash) { if (stash) { if (reg == 0) { stash->val_0_eax = words[WORD_EAX]; if (IS_VENDOR_ID(words, "GenuineIntel")) { stash->vendor = VENDOR_INTEL; } else if (IS_VENDOR_ID(words, "AuthenticAMD")) { stash->vendor = VENDOR_AMD; } else if (IS_VENDOR_ID(words, "CyrixInstead")) { stash->vendor = VENDOR_CYRIX; } else if (IS_VENDOR_ID(words, "CentaurHauls")) { stash->vendor = VENDOR_VIA; } else if (IS_VENDOR_ID(words, "UMC UMC UMC ")) { stash->vendor = VENDOR_UMC; } else if (IS_VENDOR_ID(words, "NexGenDriven")) { stash->vendor = VENDOR_NEXGEN; } else if (IS_VENDOR_ID(words, "RiseRiseRise")) { stash->vendor = VENDOR_RISE; } else if (IS_VENDOR_ID(words, "GenuineTMx86")) { stash->vendor = VENDOR_TRANSMETA; } else if (IS_VENDOR_ID(words, "SiS SiS SiS ")) { stash->vendor = VENDOR_SIS; } else if (IS_VENDOR_ID(words, "Geode by NSC")) { stash->vendor = VENDOR_NSC; } else if (IS_VENDOR_ID(words, "Vortex86 SoC")) { stash->vendor = VENDOR_VORTEX; } else if (IS_VENDOR_ID(words, "Genuine RDC")) { stash->vendor = VENDOR_RDC; } else if (IS_VENDOR_ID(words, "HygonGenuine")) { stash->vendor = VENDOR_HYGON; } else if (IS_VENDOR_ID(words, " Shanghai ")) { stash->vendor = VENDOR_ZHAOXIN; } } else if (reg == 1) { stash->val_1_eax = words[WORD_EAX]; stash->val_1_ebx = words[WORD_EBX]; stash->val_1_ecx = words[WORD_ECX]; stash->val_1_edx = words[WORD_EDX]; } else if (reg == 4) { stash->saw_4 = TRUE; if (sub == 0) { stash->val_4_eax = words[WORD_EAX]; } } else if (reg == 7) { if (sub == 1) { stash->val_7_1_edx = words[WORD_EDX]; } } else if (reg == 0xb) { if (words[WORD_EAX] != 0 || words[WORD_EBX] != 0 || words[WORD_ECX] != 0 || words[WORD_EDX] != 0) { // If this returns all 0's, it's an unsupported leaf, and not even // the extended APIC ID should be used. AMD is particularly prone // to this. stash->saw_b = TRUE; } if (sub == 0) { stash->val_b_edx = words[WORD_EDX]; } if (sub < LENGTH(stash->val_b_eax)) { stash->val_b_eax[sub] = words[WORD_EAX]; } if (sub < LENGTH(stash->val_b_ebx)) { stash->val_b_ebx[sub] = words[WORD_EBX]; } } else if (reg == 0x17) { if (sub == 1) { memcpy(&stash->soc_brand[0], words, sizeof(unsigned int)*WORD_NUM); } else if (sub == 2) { memcpy(&stash->soc_brand[16], words, sizeof(unsigned int)*WORD_NUM); } else if (sub == 3) { memcpy(&stash->soc_brand[32], words, sizeof(unsigned int)*WORD_NUM); } } else if (reg == 0x1a) { if (sub == 0) { stash->val_1a_0_eax = words[WORD_EAX]; } } else if (reg == 0x1f) { stash->saw_1f = TRUE; if (sub == 0) { stash->val_1f_edx = words[WORD_EDX]; } if (sub < LENGTH(stash->val_1f_eax)) { stash->val_1f_eax[sub] = words[WORD_EAX]; } if (sub < LENGTH(stash->val_1f_ebx)) { stash->val_1f_ebx[sub] = words[WORD_EBX]; } if (sub < LENGTH(stash->val_1f_ecx)) { stash->val_1f_ecx[sub] = words[WORD_ECX]; } } else if (IS_HYPERVISOR_LEAF(reg, 0)) { stash->hypervisor = get_hypervisor(words); } else if (reg == 0x80000001) { stash->val_80000001_eax = words[WORD_EAX]; stash->val_80000001_ebx = words[WORD_EBX]; stash->val_80000001_ecx = words[WORD_ECX]; stash->val_80000001_edx = words[WORD_EDX]; } else if (reg == 0x80000002) { memcpy(&stash->brand[0], words, sizeof(unsigned int)*WORD_NUM); } else if (reg == 0x80000003) { memcpy(&stash->brand[16], words, sizeof(unsigned int)*WORD_NUM); } else if (reg == 0x80000004) { memcpy(&stash->brand[32], words, sizeof(unsigned int)*WORD_NUM); } else if (reg == 0x80000008) { stash->val_80000008_ecx = words[WORD_ECX]; } else if (reg == 0x8000001e) { stash->saw_8000001e = TRUE; stash->val_8000001e_eax = words[WORD_EAX]; stash->val_8000001e_ebx = words[WORD_EBX]; } else if (reg == 0x80860003) { memcpy(&stash->transmeta_info[0], words, sizeof(unsigned int)*WORD_NUM); } else if (reg == 0x80860004) { memcpy(&stash->transmeta_info[16], words, sizeof(unsigned int)*WORD_NUM); } else if (reg == 0x80860005) { memcpy(&stash->transmeta_info[32], words, sizeof(unsigned int)*WORD_NUM); } else if (reg == 0x80860006) { memcpy(&stash->transmeta_info[48], words, sizeof(unsigned int)*WORD_NUM); } } if (opts->raw) { print_reg_raw(reg, sub, words); } else if (reg == 0) { // max already set to words[WORD_EAX] in calling function printf(" vendor_id = \"%-4.4s%-4.4s%-4.4s\"\n", (const char*)&words[WORD_EBX], (const char*)&words[WORD_EDX], (const char*)&words[WORD_ECX]); } else if (reg == 1) { print_1_eax(words[WORD_EAX], (stash ? stash->vendor : VENDOR_UNKNOWN), opts); print_1_ebx(words[WORD_EBX]); print_brand(words[WORD_EAX], words[WORD_EBX]); print_1_edx(words[WORD_EDX]); print_1_ecx(words[WORD_ECX]); } else if (reg == 2) { if (sub == 0) { printf(" cache and TLB information (2):\n"); } if (stash) { unsigned int word = 0; for (; word < 4; word++) { if ((words[word] & 0x80000000) == 0) { const unsigned char* bytes = (const unsigned char*)&words[word]; unsigned int byte = (sub == 0 && word == WORD_EAX ? 1 : 0); for (; byte < 4; byte++) { print_2_byte(bytes[byte], stash->vendor, stash->val_1_eax); stash_intel_cache(stash, bytes[byte]); } } } } else { // Too many of the byte codes are vendor, family, or model dependent, // so don't even try to decode. print_reg_raw(reg, sub, words); } } else if (reg == 3) { if (stash) { printf(" processor serial number =" " %04X-%04X-%04X-%04X-%04X-%04X\n", stash->val_1_eax >> 16, stash->val_1_eax & 0xffff, words[WORD_EDX] >> 16, words[WORD_EDX] & 0xffff, words[WORD_ECX] >> 16, words[WORD_ECX] & 0xffff); } else { print_reg_raw(reg, sub, words); } } else if (reg == 4) { if (sub == 0) { printf(" deterministic cache parameters (4):\n"); } printf(" --- cache %d ---\n", sub); if ((words[WORD_EAX] & 0x1f) == 0) { printf(" cache type = " "no more caches (0)\n"); } else { print_4_eax(words[WORD_EAX]); print_4_ebx(words[WORD_EBX]); print_4_ecx(words[WORD_ECX]); print_4_edx(words[WORD_EDX]); printf(" number of sets (s) = %llu\n", (unsigned long long)words[WORD_ECX] + 1ULL); print_4_synth(words); } } else if (reg == 5) { printf(" MONITOR/MWAIT (5):\n"); print_5_eax(words[WORD_EAX]); print_5_ebx(words[WORD_EBX]); print_5_ecx(words[WORD_ECX]); print_5_edx(words[WORD_EDX]); } else if (reg == 6) { printf(" Thermal and Power Management Features (6):\n"); print_6_eax(words[WORD_EAX]); print_6_ebx(words[WORD_EBX]); print_6_ecx(words[WORD_ECX]); print_6_edx(words[WORD_EDX]); } else if (reg == 7) { if (sub == 0) { printf(" extended feature flags (7):\n"); print_7_0_ebx(words[WORD_EBX]); print_7_0_ecx(words[WORD_ECX]); print_7_0_edx(words[WORD_EDX]); } else if (sub == 1) { print_7_1_eax(words[WORD_EAX]); print_7_1_ebx(words[WORD_EBX]); print_7_1_ecx(words[WORD_ECX]); print_7_1_edx(words[WORD_EDX]); } else if (sub == 2) { print_7_2_edx(words[WORD_EDX]); } else { /* Reserved: DO NOTHING */ } } else if (reg == 8) { /* Reserved: DO NOTHING */ } else if (reg == 9) { printf(" Direct Cache Access Parameters (9):\n"); printf(" PLATFORM_DCA_CAP MSR bits = %u\n", words[WORD_EAX]); } else if (reg == 0xa) { printf(" Architecture Performance Monitoring Features (0xa):\n"); print_a_eax(words[WORD_EAX]); print_a_ebx(words[WORD_EBX], words[WORD_EAX]); print_a_ecx(words[WORD_ECX]); print_a_edx(words[WORD_EDX]); } else if (reg == 0xb) { if (sub == 0) { printf(" x2APIC features / processor topology (0xb):\n"); // This is invariant across subleaves, so print it only once printf(" extended APIC ID = %u\n", words[WORD_EDX]); } printf(" --- level %d ---\n", sub); print_b_1f_ecx(words[WORD_ECX]); print_b_1f_eax(words[WORD_EAX]); print_b_1f_ebx(words[WORD_EBX]); } else if (reg == 0xc) { /* Reserved: DO NOTHING */ } else if (reg == 0xd) { if (sub == 0) { printf(" XSAVE features (0xd/0):\n"); printf(" XCR0 valid bit field mask = 0x%08x%08x\n", words[WORD_EDX], words[WORD_EAX]); print_d_0_eax(words[WORD_EAX]); print_d_0_edx(words[WORD_EDX]); // No bits current are defined in d_0_edx printf(" bytes required by fields in XCR0 = 0x%08x (%u)\n", words[WORD_EBX], words[WORD_EBX]); printf(" bytes required by XSAVE/XRSTOR area = 0x%08x (%u)\n", words[WORD_ECX], words[WORD_ECX]); } else if (sub == 1) { print_d_1_eax(words[WORD_EAX]); printf(" SAVE area size in bytes = 0x%08x (%u)\n", words[WORD_EBX], words[WORD_EBX]); printf(" IA32_XSS valid bit field mask = 0x%08x%08x\n", words[WORD_EDX], words[WORD_ECX]); print_d_1_ecx(words[WORD_ECX]); // edx could be used in the future, after ecx fills up. } else if (sub >= 2 && sub < 63) { print_d_n(words, sub); } else { print_reg_raw(reg, sub, words); } } else if (reg == 0xe) { /* Reserved: DO NOTHING */ } else if (reg == 0xf) { if (sub == 0) { printf(" Quality of Service Monitoring Resource Type (0xf/0):\n"); printf(" Maximum range of RMID = %u\n", words[WORD_EBX]); print_f_0_edx(words[WORD_EDX]); } else if (sub == 1) { printf(" L3 Cache Quality of Service Monitoring (0xf/1):\n"); printf(" Conversion factor from IA32_QM_CTR to bytes = %u\n", words[WORD_EBX]); printf(" Maximum range of RMID = %u\n", words[WORD_ECX]); printf(" Counter width = %u\n", 24 + BIT_EXTRACT_LE(words[WORD_EAX], 0, 8)); print_f_1_eax(words[WORD_EAX], stash); print_f_1_edx(words[WORD_EDX]); } else { print_reg_raw(reg, sub, words); } } else if (reg == 0x10) { if (sub == 0) { printf(" Resource Director Technology Allocation (0x10/0):\n"); print_10_0_ebx(words[WORD_EBX]); } else if (sub == 1 || sub == 2) { if (sub == 1) { printf(" L3 Cache Allocation Technology (0x10/1):\n"); } else if (sub == 2) { printf(" L2 Cache Allocation Technology (0x10/2):\n"); } print_10_12_eax(words[WORD_EAX]); printf(" Bit-granular map of isolation/contention = 0x%08x\n", words[WORD_EBX]); print_10_12_ecx(words[WORD_ECX]); print_10_n_edx(words[WORD_EDX]); } else if (sub == 3) { printf(" Memory Bandwidth Allocation (0x10/3):\n"); print_10_3_eax(words[WORD_EAX]); print_10_3_ecx(words[WORD_ECX]); print_10_n_edx(words[WORD_EDX]); } else if (sub == 5) { printf(" Cache Bandwidth Allocation (0x10/5):\n"); print_10_5_eax(words[WORD_EAX]); print_10_5_ecx(words[WORD_ECX]); print_10_n_edx(words[WORD_EDX]); } else { print_reg_raw(reg, sub, words); } } else if (reg == 0x12) { if (sub == 0) { printf(" Software Guard Extensions (SGX) capability (0x12/0):\n"); print_12_0_eax(words[WORD_EAX]); print_12_0_ebx(words[WORD_EBX]); print_12_0_edx(words[WORD_EDX]); } else if (sub == 1) { printf(" SGX attributes: ECREATE SECS.ATTRIBUTES (0x12/1):\n"); printf(" valid bit mask = 0x%08x%08x%08x%08x\n", words[WORD_EDX], words[WORD_ECX], words[WORD_EBX], words[WORD_EAX]); print_12_1_eax(words[WORD_EAX]); print_12_1_ebx(words[WORD_EBX]); printf(" XFRM: XSAVE feature request mask = 0x%08x%08x\n", words[WORD_EDX], words[WORD_ECX]); print_12_1_ecx(words[WORD_ECX]); print_12_1_edx(words[WORD_EDX]); } else { if ((words[WORD_EAX] & 0xf) == 0) { printf(" SGX Enclave Page Cache (EPC) enumeration (0x12/0x%x):\n", sub); print_12_n_eax(words[WORD_EAX], /* max_len => */ 0); } else if ((words[WORD_EAX] & 0xf) == 1) { printf(" SGX Enclave Page Cache (EPC) enumeration (0x12/0x%x):\n", sub); print_12_n_eax(words[WORD_EAX], /* max_len => */ 24); printf(" section physical address = 0x%08x%08x\n", words[WORD_EBX] & 0xfffff, words[WORD_EAX] & 0xfffff000); printf(" section size = 0x%08x%08x\n", words[WORD_EDX] & 0xfffff, words[WORD_ECX] & 0xfffff000); print_12_n_ecx(words[WORD_ECX]); } else { print_reg_raw(reg, sub, words); } } } else if (reg == 0x14) { if (sub == 0) { printf(" Intel Processor Trace (0x14):\n"); print_14_0_ebx(words[WORD_EBX]); print_14_0_ecx(words[WORD_ECX]); } else if (sub == 1) { print_14_1_eax(words[WORD_EAX]); print_14_1_ebx(words[WORD_EBX]); print_14_1_ecx(words[WORD_ECX]); } else { print_reg_raw(reg, sub, words); } } else if (reg == 0x15) { printf(" Time Stamp Counter/Core Crystal Clock Information (0x15):\n"); printf(" TSC/clock ratio = %u/%u\n", words[WORD_EBX], words[WORD_EAX]); printf(" nominal core crystal clock = %u Hz\n", words[WORD_ECX]); } else if (reg == 0x16) { printf(" Processor Frequency Information (0x16):\n"); print_16_eax(words[WORD_EAX]); print_16_ebx(words[WORD_EBX]); print_16_ecx(words[WORD_ECX]); } else if (reg == 0x17) { if (sub == 0) { printf(" System-On-Chip Vendor Attribute (0x17):\n"); print_17_0_ebx(words[WORD_EBX]); printf(" project id = 0x%08x (%u)\n", words[WORD_ECX], words[WORD_ECX]); printf(" stepping id = 0x%08x (%u)\n", words[WORD_EDX], words[WORD_EDX]); } else if (sub == 1) { if (stash) { // DO NOTHING: saved in soc_brand above } else { print_reg_raw(reg, sub, words); } } else if (sub == 2) { if (stash) { // DO NOTHING: saved in soc_brand above } else { print_reg_raw(reg, sub, words); } } else if (sub == 3) { if (stash) { printf(" SoC brand = \"%s\"\n", stash->soc_brand); } else { print_reg_raw(reg, sub, words); } } else { print_reg_raw(reg, sub, words); } } else if (reg == 0x18) { printf(" Deterministic Address Translation Parameters (0x18/%d):\n", sub); print_18_n_ebx(words[WORD_EBX]); printf(" number of sets = 0x%08x (%u)\n", words[WORD_ECX], words[WORD_ECX]); print_18_n_edx(words[WORD_EDX]); } else if (reg == 0x19) { printf(" Key Locker information (0x19):\n"); print_19_eax(words[WORD_EAX]); print_19_ebx(words[WORD_EBX]); print_19_ecx(words[WORD_ECX]); } else if (reg == 0x1a) { printf(" Native Model ID Information (0x1a/0):\n"); print_1a_0_eax(words[WORD_EAX]); } else if (reg == 0x1b) { printf(" PCONFIG information (0x1b/0x%x):\n", sub); print_1b_n_eax(words[WORD_EAX]); if ((words[WORD_EAX] & 0xfff) != 0) { print_1b_n_target(3 * sub + 1, words[WORD_EBX]); print_1b_n_target(3 * sub + 2, words[WORD_ECX]); print_1b_n_target(3 * sub + 3, words[WORD_EDX]); } } else if (reg == 0x1c) { printf(" Architectural LBR Capabilities (0x1c/0):\n"); print_1c_eax(words[WORD_EAX]); print_1c_ebx(words[WORD_EBX]); print_1c_ecx(words[WORD_ECX]); } else if (reg == 0x1d) { if (sub == 0) { printf(" Tile Information (0x1d):\n"); printf(" max_palette = %u\n", words[WORD_EAX]); } else { printf(" --- palette %d ---\n", sub); print_1d_n_eax(words[WORD_EAX]); print_1d_n_ebx(words[WORD_EBX]); print_1d_n_ecx(words[WORD_ECX]); } } else if (reg == 0x1e) { if (sub == 0) { printf(" TMUL Information (0x1e):\n"); print_1e_0_ebx(words[WORD_EBX]); } else if (sub == 1) { print_1e_1_eax(words[WORD_EAX]); } else { print_reg_raw(reg, sub, words); } } else if (reg == 0x1f) { if (sub == 0) { printf(" V2 extended topology (0x1f):\n"); // This is invariant across subleaves, so print it only once printf(" x2APIC ID of logical processor = 0x%x (%u)\n", words[WORD_EDX], words[WORD_EDX]); } printf(" --- level %d ---\n", sub); print_b_1f_ecx(words[WORD_ECX]); print_b_1f_eax(words[WORD_EAX]); print_b_1f_ebx(words[WORD_EBX]); } else if (reg == 0x20) { if (sub == 0) { printf(" Processor History Reset information (0x20):\n"); print_20_ebx(words[WORD_EBX]); } else { print_reg_raw(reg, sub, words); } } else if (reg == 0x21) { printf(" tdx_guest_id = "); if (words[WORD_EBX] > 0 && words[WORD_EDX] > 0 && words[WORD_ECX] > 0) { printf("\"%-4.4s%-4.4s%-4.4s\"\n", (const char*)&words[WORD_EBX], (const char*)&words[WORD_EDX], (const char*)&words[WORD_ECX]); } else { printf("none\n"); } } else if (reg == 0x23) { if (sub == 0) { printf(" Architecture Performance Monitoring Extended (0x23/0):\n"); print_23_0_eax(words[WORD_EAX]); print_23_0_ebx(words[WORD_EBX]); print_23_0_ecx(words[WORD_ECX]); } else if (sub == 1) { printf(" Architecture Performance Monitoring" " Extended Counters Supported Bitmaps" " (0x23/1):\n"); printf(" general counters bitmap = 0x%0llx\n", (unsigned long long)words[WORD_EAX]); printf(" fixed counters bitmap = 0x%0llx\n", (unsigned long long)words[WORD_EBX]); } else if (sub == 2) { printf(" Architecture Performance Monitoring" " Extended Auto Counter Reload (ACR) Bitmaps" " (0x23/2):\n"); printf(" general can be reloaded = 0x%0llx\n", (unsigned long long)words[WORD_EAX]); printf(" fixed can be reloaded = 0x%0llx\n", (unsigned long long)words[WORD_EBX]); printf(" general can cause reloads = 0x%0llx\n", (unsigned long long)words[WORD_ECX]); printf(" fixed can cause reloads = 0x%0llx\n", (unsigned long long)words[WORD_EDX]); } else if (sub == 3) { printf(" Architecture Performance Monitoring" " Extended Supported Events" " (0x23/3):\n"); print_23_3_eax(words[WORD_EAX]); } else if (sub == 4) { printf(" Architecture Performance Monitoring" " Extended IA32_PMC_{GP,FX}n_CFG_C MSRs" " (0x23/4):\n"); print_23_4_ebx(words[WORD_EBX]); } else if (sub == 5) { printf(" Architecture Performance Monitoring" " Extended Architectural PEBS" " (0x23/5):\n"); printf(" PEBS general counters bitmap = 0x%0llx\n", (unsigned long long)words[WORD_EAX]); printf(" PEBS & PDIST general counters bitmap = 0x%0llx\n", (unsigned long long)words[WORD_EBX]); printf(" PEBS fixed counters bitmap = 0x%0llx\n", (unsigned long long)words[WORD_ECX]); printf(" PEBS & PDIST fixed counters bitmap = 0x%0llx\n", (unsigned long long)words[WORD_EDX]); } else { print_reg_raw(reg, sub, words); } } else if (reg == 0x24) { if (sub == 0) { printf(" Converged Vector ISA (0x24/0):\n"); print_24_0_ebx(words[WORD_EBX]); } else { print_reg_raw(reg, sub, words); } } else if (reg == 0x20000000) { // max already set to words[WORD_EAX] in calling function } else if (reg == 0x20000001) { print_20000001_edx(words[WORD_EDX]); } else if (IS_HYPERVISOR_LEAF(reg, 0)) { printf(" hypervisor_id (0x%08x) = \"", reg); print_esc_substring((const char*)&words[WORD_EBX], sizeof(words[0])); print_esc_substring((const char*)&words[WORD_ECX], sizeof(words[0])); print_esc_substring((const char*)&words[WORD_EDX], sizeof(words[0])); printf("\"\n"); } else if (IS_HYPERVISOR_LEAF(reg, 1) && stash && stash->hypervisor == HYPERVISOR_XEN) { printf(" hypervisor version (0x%08x/eax):\n", reg); printf(" version = %d.%d\n", BIT_EXTRACT_LE(words[WORD_EAX], 16, 32), BIT_EXTRACT_LE(words[WORD_EAX], 0, 16)); } else if (IS_HYPERVISOR_LEAF(reg, 1) && stash && stash->hypervisor == HYPERVISOR_KVM) { print_hypervisor_1_eax_kvm(reg, words[WORD_EAX]); print_hypervisor_1_edx_kvm(reg, words[WORD_EDX]); } else if (IS_HYPERVISOR_LEAF(reg, 1) && stash && stash->hypervisor == HYPERVISOR_MICROSOFT) { printf(" hypervisor interface identification (0x%08x/eax):\n", reg); printf(" version = \"%-4.4s\"\n", (const char*)&words[WORD_EAX]); } else if (IS_HYPERVISOR_LEAF(reg, 1) && stash && stash->hypervisor == HYPERVISOR_ACRN) { print_hypervisor_1_eax_acrn(reg, words[WORD_EAX]); } else if (IS_HYPERVISOR_LEAF(reg, 2) && stash && stash->hypervisor == HYPERVISOR_XEN) { printf(" hypervisor features (0x%08x):\n", reg); printf(" number of hypercall-transfer pages = 0x%0x (%u)\n", words[WORD_EAX], words[WORD_EAX]); printf(" MSR base address = 0x%0x\n", words[WORD_EBX]); print_hypervisor_2_ecx_xen(words[WORD_ECX]); } else if (IS_HYPERVISOR_LEAF(reg, 2) && stash && stash->hypervisor == HYPERVISOR_MICROSOFT) { printf(" hypervisor system identity (0x%08x):\n", reg); printf(" build = %d\n", words[WORD_EAX]); printf(" version = %d.%d\n", BIT_EXTRACT_LE(words[WORD_EBX], 16, 32), BIT_EXTRACT_LE(words[WORD_EBX], 0, 16)); printf(" service pack = %d\n", words[WORD_ECX]); printf(" service branch = %d\n", BIT_EXTRACT_LE(words[WORD_EDX], 24, 32)); printf(" service number = %d\n", BIT_EXTRACT_LE(words[WORD_EDX], 0, 24)); } else if (IS_HYPERVISOR_LEAF(reg, 3) && stash && stash->hypervisor == HYPERVISOR_XEN && sub == 0) { printf(" hypervisor time features (0x%08x/00):\n", reg); print_hypervisor_3_0_eax_xen(words[WORD_EAX]); print_hypervisor_3_0_ebx_xen(words[WORD_EBX]); printf(" tsc frequency (kHz) = %u\n", words[WORD_ECX]); printf(" incarnation = 0x%0x (%u)\n", words[WORD_EDX], words[WORD_EDX]); } else if (IS_HYPERVISOR_LEAF(reg, 3) && stash && stash->hypervisor == HYPERVISOR_XEN && sub == 1) { printf(" hypervisor time scale & offset (0x%08x/01):\n", reg); unsigned long long vtsc_offset = ((unsigned long long)words[WORD_EAX] + ((unsigned long long)words[WORD_EBX] << 32)); printf(" vtsc offset = 0x%0llx (%llu)\n", vtsc_offset, vtsc_offset); printf(" vtsc mul_frac = 0x%0x (%u)\n", words[WORD_ECX], words[WORD_ECX]); printf(" vtsc shift = 0x%0x (%u)\n", words[WORD_EDX], words[WORD_EDX]); } else if (IS_HYPERVISOR_LEAF(reg, 3) && stash && stash->hypervisor == HYPERVISOR_XEN && sub == 2) { printf(" hypervisor time physical cpu frequency (0x%08x/02):\n", reg); printf(" cpu frequency (kHZ) = %u\n", words[WORD_EAX]); } else if (IS_HYPERVISOR_LEAF(reg, 3) && stash && stash->hypervisor == HYPERVISOR_MICROSOFT) { print_hypervisor_3_eax_microsoft(reg, words[WORD_EAX]); print_hypervisor_3_ebx_microsoft(reg, words[WORD_EBX]); print_hypervisor_3_ecx_microsoft(reg, words[WORD_ECX]); print_hypervisor_3_edx_microsoft(reg, words[WORD_EDX]); } else if (IS_HYPERVISOR_LEAF(reg, 4) && stash && stash->hypervisor == HYPERVISOR_XEN) { print_hypervisor_4_eax_xen(reg, words[WORD_EAX]); printf(" vcpu id = 0x%x (%u)\n", words[WORD_EBX], words[WORD_EBX]); printf(" domain id = 0x%x (%u)\n", words[WORD_ECX], words[WORD_ECX]); } else if (IS_HYPERVISOR_LEAF(reg, 4) && stash && stash->hypervisor == HYPERVISOR_MICROSOFT) { printf(" hypervisor recommendations (0x%08x/eax):\n", reg); print_hypervisor_4_eax_microsoft(words[WORD_EAX]); print_hypervisor_4_ecx_microsoft(words[WORD_ECX]); printf(" maximum number of spinlock retry attempts = 0x%0x (%u)\n", words[WORD_EBX], words[WORD_EBX]); } else if (IS_HYPERVISOR_LEAF(reg, 5) && stash && stash->hypervisor == HYPERVISOR_XEN && sub == 0) { print_hypervisor_5_0_ebx_xen(reg, words[WORD_EBX]); } else if (IS_HYPERVISOR_LEAF(reg, 5) && stash && stash->hypervisor == HYPERVISOR_MICROSOFT) { printf(" hypervisor implementation limits (0x%08x):\n", reg); printf(" maximum number of virtual processors " " = 0x%0x (%u)\n", words[WORD_EAX], words[WORD_EAX]); printf(" maximum number of logical processors " " = 0x%0x (%u)\n", words[WORD_EBX], words[WORD_EBX]); printf(" maximum number of physical interrupt vectors for remapping" " = 0x%0x (%u)\n", words[WORD_ECX], words[WORD_ECX]); } else if (IS_HYPERVISOR_LEAF(reg, 6) && stash && stash->hypervisor == HYPERVISOR_MICROSOFT) { print_hypervisor_6_eax_microsoft(reg, words[WORD_EAX]); } else if (IS_HYPERVISOR_LEAF(reg, 7) && stash && stash->hypervisor == HYPERVISOR_MICROSOFT) { printf(" hypervisor root partition enlightenments (0x%08x):\n", reg); print_hypervisor_7_eax_microsoft(words[WORD_EAX]); print_hypervisor_7_ebx_microsoft(words[WORD_EBX]); print_hypervisor_7_ecx_microsoft(words[WORD_ECX]); } else if (IS_HYPERVISOR_LEAF(reg, 8) && stash && stash->hypervisor == HYPERVISOR_MICROSOFT) { printf(" hypervisor shared virtual memory (0x%08x):\n", reg); print_hypervisor_8_eax_microsoft(words[WORD_EAX]); } else if (IS_HYPERVISOR_LEAF(reg, 9) && stash && stash->hypervisor == HYPERVISOR_MICROSOFT) { printf(" hypervisor nested hypervisor features (0x%08x):\n", reg); print_hypervisor_9_eax_microsoft(words[WORD_EAX]); print_hypervisor_9_edx_microsoft(words[WORD_EDX]); } else if (IS_HYPERVISOR_LEAF(reg, 0xa) && stash && stash->hypervisor == HYPERVISOR_MICROSOFT) { printf(" hypervisor nested virtualization features (0x%08x):\n", reg); print_hypervisor_a_eax_microsoft(words[WORD_EAX]); print_hypervisor_a_ebx_microsoft(words[WORD_EBX]); } else if (IS_HYPERVISOR_LEAF(reg, 0xc) && stash && stash->hypervisor == HYPERVISOR_MICROSOFT) { printf(" hypervisor isolation configuration (0x%08x):\n", reg); print_hypervisor_c_eax_microsoft(words[WORD_EAX]); print_hypervisor_c_ebx_microsoft(words[WORD_EBX]); } else if (IS_HYPERVISOR_LEAF(reg, 0x10)) { printf(" hypervisor generic timing information (0x%08x):\n", reg); printf(" TSC frequency (Hz) = %d\n", words[WORD_EAX]); printf(" bus frequency (Hz) = %d\n", words[WORD_EBX]); } else if (IS_HYPERVISOR_LEAF(reg, 0x80)) { printf(" hypervisor synthetic debugger id = "); if (words[WORD_EBX] > 0 && words[WORD_EDX] > 0 && words[WORD_ECX] > 0) { printf("\"%-4.4s%-4.4s%-4.4s\"\n", (const char*)&words[WORD_EBX], (const char*)&words[WORD_EDX], (const char*)&words[WORD_ECX]); } else { printf("none\n"); } } else if (IS_HYPERVISOR_LEAF(reg, 0x81)) { printf(" hypervisor synthetic debugger interface = "); if (words[WORD_EAX] > 0) { printf("\"%-4.4s\"\n", (const char*)&words[WORD_EAX]); } else { printf("none\n"); } } else if (IS_HYPERVISOR_LEAF(reg, 0x82)) { printf(" hypervisor synthetic debugger platform capabilities" " (0x%08x):\n", reg); print_hypervisor_82_eax_microsoft(words[WORD_EAX]); } else if (reg == 0x80000000) { // max already set to words[WORD_EAX] in calling function } else if (reg == 0x80000001) { if (stash) { print_80000001_eax(words[WORD_EAX], stash->vendor, opts); print_80000001_edx(words[WORD_EDX], stash->vendor); print_80000001_ebx(words[WORD_EBX], stash->vendor, stash->val_1_eax); print_80000001_ecx(words[WORD_ECX], stash->vendor); } else { print_reg_raw(reg, sub, words); } } else if (reg == 0x80000002) { if (stash) { // DO NOTHING: saved in brand above } else { print_reg_raw(reg, sub, words); } } else if (reg == 0x80000003) { if (stash) { // DO NOTHING: saved in brand above } else { print_reg_raw(reg, sub, words); } } else if (reg == 0x80000004) { if (stash) { printf(" brand = \"%s\"\n", stash->brand); } else { print_reg_raw(reg, sub, words); } } else if (reg == 0x80000005) { print_80000005_eax(words[WORD_EAX]); print_80000005_ebx(words[WORD_EBX]); print_80000005_ecx(words[WORD_ECX]); print_80000005_edx(words[WORD_EDX]); } else if (reg == 0x80000006) { print_80000006_eax(words[WORD_EAX]); print_80000006_ebx(words[WORD_EBX]); print_80000006_ecx(words[WORD_ECX], stash); print_80000006_edx(words[WORD_EDX]); } else if (reg == 0x80000007) { print_80000007_ebx(words[WORD_EBX]); print_80000007_ecx(words[WORD_ECX]); print_80000007_edx(words[WORD_EDX]); } else if (reg == 0x80000008) { print_80000008_eax(words[WORD_EAX]); print_80000008_ebx(words[WORD_EBX], stash); printf(" Size Identifiers (0x80000008/ecx):\n"); if (stash) { unsigned int num_thrs = BIT_EXTRACT_LE(stash->val_80000008_ecx, 0, 8); if (Synth_Family(stash->val_80000001_eax) > 0x16) { printf(" number of threads = 0x%llx (%llu)\n", (unsigned long long)num_thrs + 1ULL, (unsigned long long)num_thrs + 1ULL); } else { printf(" number of CPU cores = 0x%llx (%llu)\n", (unsigned long long)num_thrs + 1ULL, (unsigned long long)num_thrs + 1ULL); } } print_80000008_ecx(words[WORD_ECX]); print_80000008_edx(words[WORD_EDX]); } else if (reg == 0x80000009) { /* reserved for Intel feature flag expansion */ } else if (reg == 0x8000000a) { print_8000000a_eax(words[WORD_EAX]); print_8000000a_edx(words[WORD_EDX]); print_8000000a_ebx(words[WORD_EBX]); } else if (0x8000000b <= reg && reg <= 0x80000018) { /* reserved for vendors to be determined feature flag expansion */ } else if (reg == 0x80000019) { print_80000019_eax(words[WORD_EAX]); print_80000019_ebx(words[WORD_EBX]); } else if (reg == 0x8000001a) { print_8000001a_eax(words[WORD_EAX]); } else if (reg == 0x8000001b) { print_8000001b_eax(words[WORD_EAX]); } else if (reg == 0x8000001c) { print_8000001c_eax(words[WORD_EAX]); print_8000001c_edx(words[WORD_EDX]); print_8000001c_ebx(words[WORD_EBX]); print_8000001c_ecx(words[WORD_ECX]); } else if (reg == 0x8000001d) { if (sub == 0) { printf(" Cache Properties (0x8000001d):\n"); } printf(" --- cache %d ---\n", sub); print_8000001d_eax(words[WORD_EAX]); print_8000001d_ebx(words[WORD_EBX]); printf(" number of sets = %llu\n", (unsigned long long)words[WORD_ECX] + 1ULL); print_8000001d_edx(words[WORD_EDX]); print_8000001d_synth(words); } else if (reg == 0x8000001e) { printf(" extended APIC ID = %u\n", words[WORD_EAX]); if (stash) { if (Synth_Family(stash->val_80000001_eax) > 0x16) { print_8000001e_ebx_gt_f16(words[WORD_EBX]); } else { print_8000001e_ebx_f16(words[WORD_EBX]); } } print_8000001e_ecx(words[WORD_ECX]); } else if (reg == 0x8000001f) { printf(" AMD Secure Encryption (0x8000001f):\n"); print_8000001f_eax(words[WORD_EAX]); print_8000001f_ebx(words[WORD_EBX]); printf(" number of SEV-enabled guests supported = 0x%0x (%u)\n", words[WORD_ECX], words[WORD_ECX]); printf(" minimum SEV guest ASID = 0x%0x (%u)\n", words[WORD_EDX], words[WORD_EDX]); } else if (reg == 0x80000020) { if (sub == 0) { printf(" PQoS Extended Features (0x80000020):\n"); print_80000020_0_ebx(words[WORD_EBX]); } else if (sub == 1) { printf(" PQoS L3 Memory Bandwidth Enforcement" " (0x80000020/1):\n"); printf(" capacity bitmask length = 0x%0llx (%llu)\n", (unsigned long long)words[WORD_EAX] + 1, (unsigned long long)words[WORD_EAX] + 1); printf(" number of classes of service = 0x%0x (%u)\n", words[WORD_EDX], words[WORD_EDX]); } else if (sub == 2) { printf(" PQoS L3 Slow Memory Bandwidth Enforcement" " (0x80000020/2):\n"); printf(" capacity bitmask length = 0x%0llx (%llu)\n", (unsigned long long)words[WORD_EAX] + 1, (unsigned long long)words[WORD_EAX] + 1); printf(" number of classes of service = 0x%0x (%u)\n", words[WORD_EDX], words[WORD_EDX]); } else if (sub == 3) { printf(" PQoS Bandwidth Monitoring Event Configuration" " (0x80000020/3):\n"); print_80000020_3_ebx(words[WORD_EBX]); print_80000020_3_ecx(words[WORD_ECX]); } else if (sub == 5) { printf(" PQoS Assignable Bandwidth Monitoring Counters" " (0x80000020/5):\n"); print_80000020_5_eax(words[WORD_EAX]); print_80000020_5_ebx(words[WORD_EBX]); print_80000020_5_ecx(words[WORD_ECX]); } else { print_reg_raw(reg, sub, words); } } else if (reg == 0x80000021) { printf(" Extended Feature 2 (0x80000021):\n"); print_80000021_eax(words[WORD_EAX]); print_80000021_ebx(words[WORD_EBX]); } else if (reg == 0x80000022) { printf(" Extended Performance Monitoring and Debugging (0x80000022):\n"); print_80000022_eax(words[WORD_EAX]); print_80000022_ebx(words[WORD_EBX]); printf(" active UMCs bitmask = 0x%0x\n", words[WORD_ECX]); } else if (reg == 0x80000023) { printf(" Multi-Key Encrypted Memory Capabilities (0x80000023):\n"); print_80000023_eax(words[WORD_EAX]); print_80000023_ebx(words[WORD_EBX]); } else if (reg == 0x80000025) { printf(" Segmented RMP Table (0x80000025):\n"); print_80000025_eax(words[WORD_EAX]); print_80000025_ebx(words[WORD_EBX]); } else if (reg == 0x80000026) { /* Similar to 0xb & 0x1f, but with extra bit fields */ if (sub == 0) { printf(" AMD Extended CPU Topology (0x80000026):\n"); // This is invariant across subleaves, so print it only once printf(" extended APIC ID = %u\n", words[WORD_EDX]); } printf(" --- level %d ---\n", sub); print_80000026_ecx(words[WORD_ECX]); print_80000026_eax(words[WORD_EAX]); if (sub == 1) { print_80000026_1_ebx(words[WORD_EBX]); } else { print_80000026_n_ebx(words[WORD_EBX]); } } else if (reg == 0x80860000) { // max already set to words[WORD_EAX] } else if (reg == 0x80860001) { print_80860001_eax(words[WORD_EAX], opts); print_80860001_edx(words[WORD_EDX]); print_80860001_ebx_ecx(words[WORD_EBX], words[WORD_ECX]); } else if (reg == 0x80860002) { print_80860002_eax(words[WORD_EAX], stash); printf(" Transmeta CMS revision (0x80000002/ecx)" " = %u.%u-%u.%u-%u\n", (words[WORD_EBX] >> 24) & 0xff, (words[WORD_EBX] >> 16) & 0xff, (words[WORD_EBX] >> 8) & 0xff, (words[WORD_EBX] >> 0) & 0xff, words[WORD_ECX]); } else if (reg == 0x80860003) { if (stash) { // DO NOTHING: saved in transmeta_info above } else { print_reg_raw(reg, sub, words); } } else if (reg == 0x80860004) { if (stash) { // DO NOTHING: saved in transmeta_info above } else { print_reg_raw(reg, sub, words); } } else if (reg == 0x80860005) { if (stash) { // DO NOTHING: saved in transmeta_info above } else { print_reg_raw(reg, sub, words); } } else if (reg == 0x80860006) { if (stash) { printf(" Transmeta information = \"%s\"\n", stash->transmeta_info); } else { print_reg_raw(reg, sub, words); } } else if (reg == 0x80860007) { printf(" Transmeta core clock frequency = %u MHz\n", words[WORD_EAX]); printf(" Transmeta processor voltage = %u mV\n", words[WORD_EBX]); printf(" Transmeta performance = %u%%\n", words[WORD_ECX]); printf(" Transmeta gate delay = %u fs\n", words[WORD_EDX]); } else if (reg == 0xc0000000) { // max already set to words[WORD_EAX] } else if (reg == 0xc0000001) { if (stash && stash->vendor == VENDOR_VIA) { /* TODO: figure out how to decode 0xc0000001:eax */ printf(" 0x%08x 0x%02x: eax=0x%08x\n", (unsigned int)reg, sub, words[WORD_EAX]); print_c0000001_edx(words[WORD_EDX]); } else { print_reg_raw(reg, sub, words); } } else if (reg == 0xc0000002) { if (stash && stash->vendor == VENDOR_VIA) { printf(" VIA C7 Current Performance Data (0xc0000002):\n"); if (BIT_EXTRACT_LE(words[WORD_EAX], 0, 8) != 0) { printf(" core temperature (degrees C) = %f\n", (double)words[WORD_EAX] / 256.0); } else { printf(" core temperature (degrees C) = %d\n", BIT_EXTRACT_LE(words[WORD_EAX], 8, 32)); } print_c0000002_ebx(words[WORD_EBX]); print_c0000002_ecx(words[WORD_ECX]); print_c0000002_edx(words[WORD_EDX]); } else { print_reg_raw(reg, sub, words); } } else if (reg == 0xc0000004) { if (stash && stash->vendor == VENDOR_VIA) { printf(" VIA Temperature (0xc0000004/eax):\n"); print_c0000004_eax(words[WORD_EAX]); printf(" VIA MSR 198 Mirror (0xc0000004):\n"); print_c0000004_ebx(words[WORD_EBX]); print_c0000004_ecx(words[WORD_ECX]); } else { print_reg_raw(reg, sub, words); } } else { print_reg_raw(reg, sub, words); } } // Return nr_cpu_ids, one more than the maximum CPU number. (This term is used // within the linux kernel.) For systems with contiguous CPU numbers, this is // the total number of CPUs. But it may be larger for systems with potentially // non-contiguous CPU numbers. static unsigned long get_nr_cpu_ids(void) { #if defined(USE_KERNEL_SCHED_SETAFFINITY) static unsigned long result = 0; if (result == 0) { unsigned long attempt = 1024; for (;;) { size_t setsize = attempt / 8; char* set = malloc(setsize); if (set == NULL) { fprintf(stderr, "%s: out of memory (get_nr_cpu_ids)\n", program); exit(1); } int status; status = syscall(__NR_sched_getaffinity, 0, setsize, set); free(set); if (status >= 0) { // The setsize is big enough result = attempt; break; } else if (status == -1 && errno != EINVAL) { fprintf(stderr, "%s: unable to getaffinity to determine nr_cpu_ids" "; errno = %d (%s)\n", program, errno, strerror(errno)); fprintf(stderr, "%s: using -1 will run on an arbitrary CPU, which does" " not require nr_cpu_ids.\n", program); exit(1); } // The setsize is not big enough: make another attempt attempt *= 2; } } return result; #elif defined(USE_PROCESSOR_BIND) || defined(USE_SCHED_SETAFFINITY_NP) return sysconf(_SC_NPROCESSORS_CONF); #elif defined(USE_CPUSET_SETAFFINITY) cpuset_t mask; CPU_ZERO(&mask); if (cpuset_getaffinity(CPU_LEVEL_WHICH, CPU_WHICH_TID, -1, sizeof(mask), &mask) == 0) { return CPU_COUNT(&mask); } else { return sysconf(_SC_NPROCESSORS_CONF); } #else unsigned long result = sysconf(_SC_NPROCESSORS_CONF); if (result > CPU_SETSIZE) result = CPU_SETSIZE; return result; #endif } unsigned int nr_cpu_ids; static void real_prepare(void) { nr_cpu_ids = get_nr_cpu_ids(); } #define USE_INSTRUCTION (-2) static int real_setup(unsigned int cpu, boolean one_cpu, boolean inst) { if (inst) { if (!one_cpu) { #if defined(USE_KERNEL_SCHED_SETAFFINITY) /* ** The interface for sched_setaffinity and cpusets has changed many ** times. Insulate this tool from all that by calling the system ** service directly. */ unsigned char* mask = malloc(nr_cpu_ids/8); bzero(mask, nr_cpu_ids/8); mask[cpu / 8] = (1 << (cpu % 8)); int status; status = syscall(__NR_sched_setaffinity, 0, nr_cpu_ids/8, mask); free(mask); #elif defined(USE_PROCESSOR_BIND) pthread_t thread = pthread_self(); int status = processor_bind(P_LWPID, thread, cpu, NULL); #elif defined(USE_CPUSET_SETAFFINITY) int status = 0; cpuset_t mask; CPU_ZERO(&mask); CPU_SET(cpu, &mask); if (cpuset_setaffinity(CPU_LEVEL_WHICH, CPU_WHICH_PID, -1, sizeof(mask), &mask) != 0) { status = -1; } #elif defined(USE_SCHED_SETAFFINITY_NP) int status = 0; cpuset_t *cpuset = cpuset_create(); cpuset_zero(cpuset); cpuset_set(cpu, cpuset); status = sched_setaffinity_np(0, cpuset_size(cpuset), cpuset); cpuset_destroy(cpuset); #elif defined(USE_PTHREAD_SETAFFINITY_NP) int status = 0; cpuset_t cpuset; CPUSET_ZERO(&cpuset); CPUSET_SET(cpu, &cpuset); pthread_t thread = pthread_self(); status = pthread_setaffinity_np(thread, sizeof(cpuset_t), &cpuset); #else cpu_set_t cpuset; CPU_ZERO(&cpuset); CPU_SET(cpu, &cpuset); int status; status = sched_setaffinity(0, sizeof(cpu_set_t), &cpuset); #endif if (status == -1) { if (errno == EINVAL) return -1; fprintf(stderr, "%s: unable to setaffinity to cpu %d; errno = %d (%s)\n", program, cpu, errno, strerror(errno)); fprintf(stderr, "%s: using -1 will avoid trying to setaffinity and run" " on an arbitrary CPU\n", program); exit(1); } sleep(0); /* to have a chance to migrate */ } return USE_INSTRUCTION; } else { #ifdef USE_CPUID_MODULE int cpuid_fd = -1; char cpuid_name[32]; if (cpuid_fd == -1 && cpu == 0) { cpuid_fd = open("/dev/cpuid", O_RDONLY); if (cpuid_fd == -1 && errno != ENOENT) { fprintf(stderr, "%s: cannot open /dev/cpuid; errno = %d (%s)\n", program, errno, strerror(errno)); explain_dev_cpu_errno(); } } if (cpuid_fd == -1) { sprintf(cpuid_name, "/dev/cpu/%u/cpuid", cpu); cpuid_fd = open(cpuid_name, O_RDONLY); if (cpuid_fd == -1) { if (cpu > 0) { if (errno == ENXIO) return -1; if (errno == ENODEV) return -1; } if (errno != ENOENT) { fprintf(stderr, "%s: cannot open /dev/cpuid or %s; errno = %d (%s)\n", program, cpuid_name, errno, strerror(errno)); explain_dev_cpu_errno(); } } } if (cpuid_fd == -1) { /* ** Lots of Linux's omit the /dev/cpuid or /dev/cpu/%u/cpuid files. ** Try creating a temporary file with mknod. ** ** mkstemp is of absolutely no security value here because I can't ** use the actual file it generates, and have to delete it and ** re-create it with mknod. But I have to use it anyway to ** eliminate errors from smartypants gcc/glibc during the link if I ** attempt to use tempnam. */ char tmpname[20]; int dummy_fd; strcpy(tmpname, "/tmp/cpuidXXXXXX"); dummy_fd = mkstemp(tmpname); if (dummy_fd != -1) { close(dummy_fd); remove(tmpname); { int status = mknod(tmpname, (S_IFCHR | S_IRUSR), makedev(CPUID_MAJOR, cpu)); if (status == 0) { cpuid_fd = open(tmpname, O_RDONLY); remove(tmpname); } } } if (cpuid_fd == -1) { if (cpu > 0) { if (errno == ENXIO) return -1; if (errno == ENODEV) return -1; } fprintf(stderr, "%s: cannot open /dev/cpuid or %s; errno = %d (%s)\n", program, cpuid_name, errno, strerror(errno)); explain_dev_cpu_errno(); } } return cpuid_fd; #else return -1; #endif } } static int real_get (int cpuid_fd, unsigned int reg, unsigned int sub, unsigned int words[], boolean quiet UNUSED) { if (cpuid_fd == USE_INSTRUCTION) { bzero(words, sizeof(unsigned int)*WORD_NUM); #ifdef USE_CPUID_COUNT __cpuid_count(reg, sub, words[WORD_EAX], words[WORD_EBX], words[WORD_ECX], words[WORD_EDX]); #else asm("cpuid" : "=a" (words[WORD_EAX]), "=b" (words[WORD_EBX]), "=c" (words[WORD_ECX]), "=d" (words[WORD_EDX]) : "a" (reg), "c" (sub)); #endif } else { #ifdef USE_CPUID_MODULE off64_t result; off64_t offset = ((off64_t)sub << 32) + reg; int status; result = lseek64(cpuid_fd, offset, SEEK_SET); if (result == -1) { if (quiet) { return FALSE; } else { fprintf(stderr, "%s: unable to seek cpuid file to offset 0x%llx;" " errno = %d (%s)\n", program, (long long unsigned)offset, errno, strerror(errno)); exit(1); } } unsigned int old_words[WORD_NUM]; if (sub != 0) memcpy(old_words, words, sizeof(old_words)); status = read(cpuid_fd, words, 16); if (status == -1) { if (quiet) { return FALSE; } else { fprintf(stderr, "%s: unable to read cpuid file at offset 0x%llx;" " errno = %d (%s)\n", program, (long long unsigned)offset, errno, strerror(errno)); exit(1); } } if (sub != 0 && memcmp(old_words, words, sizeof(old_words)) == 0) { if (quiet) { return FALSE; } else { static boolean said = FALSE; if (!said) { fprintf(stderr, "%s: reading cpuid file at offset 0x%llx produced" " duplicate results\n", program, (long long unsigned)offset); fprintf(stderr, "%s: older kernels do not support cpuid ecx control\n", program); fprintf(stderr, "%s: consider not using -k\n", program); said = TRUE; } bzero(words, sizeof(old_words)); return FALSE; } } #else return FALSE; #endif } return TRUE; } static void do_real_one(unsigned int reg, unsigned int sub, boolean one_cpu, boolean inst, const print_opts_t* opts) { real_prepare(); unsigned int cpu; for (cpu = 0; cpu < nr_cpu_ids; cpu++) { int cpuid_fd = -1; if (one_cpu && cpu > 0) break; cpuid_fd = real_setup(cpu, one_cpu, inst); if (cpuid_fd == -1) continue; if (inst && one_cpu) { printf("CPU:\n"); } else { printf("CPU %u:\n", cpu); } unsigned int words[WORD_NUM]; real_get(cpuid_fd, reg, sub, words, FALSE); print_reg(reg, sub, words, opts, NULL); } } static void do_real(boolean one_cpu, boolean inst, const print_opts_t* opts) { real_prepare(); unsigned int cpu; for (cpu = 0; cpu < nr_cpu_ids; cpu++) { int cpuid_fd = -1; code_stash_t stash = NIL_STASH; unsigned int max; unsigned int reg; if (one_cpu && cpu > 0) break; cpuid_fd = real_setup(cpu, one_cpu, inst); if (cpuid_fd == -1) continue; if (inst && one_cpu) { printf("CPU:\n"); } else { printf("CPU %u:\n", cpu); } max = 0; for (reg = 0; reg <= max; reg++) { unsigned int words[WORD_NUM]; real_get(cpuid_fd, reg, 0, words, FALSE); if (reg == 0) { max = words[WORD_EAX]; } if (reg == 2) { unsigned int max_subs = words[WORD_EAX] & 0xff; unsigned int sub = 0; for (;;) { print_reg(reg, sub, words, opts, &stash); sub++; if (sub >= max_subs) break; real_get(cpuid_fd, reg, 0, words, FALSE); } } else if (reg == 4) { unsigned int sub = 0; for (;;) { print_reg(reg, sub, words, opts, &stash); // exit when cache type indicates "no more caches" (0). if ((words[WORD_EAX] & 0x1f) == 0) break; sub++; real_get(cpuid_fd, reg, sub, words, FALSE); } } else if (reg == 7) { unsigned int max_subs = words[WORD_EAX]; unsigned int sub = 0; for (;;) { print_reg(reg, sub, words, opts, &stash); sub++; if (sub > max_subs) break; real_get(cpuid_fd, reg, sub, words, FALSE); } } else if (reg == 0xb) { unsigned int sub = 0; for (;;) { print_reg(reg, sub, words, opts, &stash); // exit when level type indicates invalid (0). if (BIT_EXTRACT_LE(words[WORD_ECX], 8, 16) == 0) break; sub++; real_get(cpuid_fd, reg, sub, words, FALSE); } } else if (reg == 0xd) { /* ** ecx values 0 & 1 are special. ** ** Intel: ** For ecx values 2..63, the leaf is present if the corresponding ** bit is present in the bit catenation of 0xd/0/edx + 0xd/0/eax, ** or the bit catenation of 0xd/1/edx + 0xd/1/ecx. ** AMD: ** Only 4 ecx values are defined and it's gappy. It's unclear ** what the upper bound of any loop would be, so it seems ** inappropriate to use one. */ print_reg(reg, 0, words, opts, &stash); unsigned long long valid_xcr0 = ((unsigned long long)words[WORD_EDX] << 32) | words[WORD_EAX]; real_get(cpuid_fd, reg, 1, words, FALSE); print_reg(reg, 1, words, opts, &stash); unsigned long long valid_xss = ((unsigned long long)words[WORD_EDX] << 32) | words[WORD_ECX]; unsigned long long valid_tries = valid_xcr0 | valid_xss; unsigned int sub; for (sub = 2; sub < 63; sub++) { if (valid_tries & (1ull << sub)) { real_get(cpuid_fd, reg, sub, words, FALSE); print_reg(reg, sub, words, opts, &stash); } } } else if (reg == 0xf) { unsigned int mask = words[WORD_EDX]; print_reg(reg, 0, words, opts, &stash); if (BIT_EXTRACT_LE(mask, 1, 2)) { real_get(cpuid_fd, reg, 1, words, FALSE); print_reg(reg, 1, words, opts, &stash); } } else if (reg == 0x10) { unsigned int mask = words[WORD_EBX]; print_reg(reg, 0, words, opts, &stash); unsigned int sub; for (sub = 1; sub < 32; sub++) { if (mask & (1 << sub)) { real_get(cpuid_fd, reg, sub, words, FALSE); print_reg(reg, sub, words, opts, &stash); } } } else if (reg == 0x12) { print_reg(reg, 0, words, opts, &stash); real_get(cpuid_fd, reg, 1, words, FALSE); print_reg(reg, 1, words, opts, &stash); unsigned int sub = 2; for (;; sub++) { real_get(cpuid_fd, reg, sub, words, FALSE); print_reg(reg, sub, words, opts, &stash); // 325462: Intel 64 and IA-32 Architectures Software Developer's // Manual Combined Volumes: 1, 2A, 2B, 2C, 3A, 3B, 3C, 3D, and 4, // Volume 3: System Programming Guide, section 32.7.2: Intel SGX // Resource Enumeration Leaves suggests a loop that exits when // encountering the first invalid leaf. if ((words[WORD_EAX] & 0xf) == 0) break; } } else if (reg == 0x14) { unsigned int max_subs = words[WORD_EAX]; unsigned int sub = 0; for (;;) { print_reg(reg, sub, words, opts, &stash); sub++; if (sub > max_subs) break; real_get(cpuid_fd, reg, sub, words, FALSE); } } else if (reg == 0x17) { unsigned int max_subs = words[WORD_EAX]; unsigned int sub = 0; for (;;) { print_reg(reg, sub, words, opts, &stash); sub++; if (sub > max_subs) break; real_get(cpuid_fd, reg, sub, words, FALSE); } } else if (reg == 0x18) { unsigned int max_subs = words[WORD_EAX]; unsigned int sub = 0; for (;;) { print_reg(reg, sub, words, opts, &stash); sub++; if (sub > max_subs) break; real_get(cpuid_fd, reg, sub, words, FALSE); } } else if (reg == 0x1b) { unsigned int prev_words[WORD_NUM]; print_reg(reg, 0, words, opts, &stash); unsigned int sub = 1; for (;; sub++) { memcpy(prev_words, words, sizeof(words)); real_get(cpuid_fd, reg, sub, words, FALSE); print_reg(reg, sub, words, opts, &stash); // Sub-leaf type of invalid (0) means that all subsequent // subleaves are invalid too. if ((words[WORD_EAX] & 0xfff) == 0) break; // This is a sanity check to avoid infinite recursion. At least // one hypervisor disregarded the subleaf number, and thus never // reported invalid (0) on any subleaf. It is not reasonable // that a subleaf should be identical to its predecessor, because // each subleaf encodes its own type. So abandon the loop in // that case. if (memcmp(words, prev_words, sizeof(words)) == 0) { break; } } } else if (reg == 0x1d) { unsigned int max_subs = words[WORD_EAX]; unsigned int sub = 0; for (;;) { print_reg(reg, sub, words, opts, &stash); sub++; if (sub > max_subs) break; real_get(cpuid_fd, reg, sub, words, FALSE); } } else if (reg == 0x1e) { // Leaf 0x1e having sub-leaves seems to be an afterthought. The // leaf doesn't indicate its max subleaf in any way, so a reader // must "just know". unsigned int max_subs = 1; unsigned int sub = 0; for (;;) { print_reg(reg, sub, words, opts, &stash); sub++; if (sub > max_subs) break; real_get(cpuid_fd, reg, sub, words, FALSE); } } else if (reg == 0x1f) { print_reg(reg, 0, words, opts, &stash); unsigned int sub; for (sub = 1; sub < 256; sub++) { real_get(cpuid_fd, reg, sub, words, FALSE); print_reg(reg, sub, words, opts, &stash); // exit when level type indicates invalid (0). if (BIT_EXTRACT_LE(words[WORD_ECX], 8, 16) == 0) break; } } else if (reg == 0x20) { unsigned int max_subs = words[WORD_EAX]; unsigned int sub = 0; for (;;) { print_reg(reg, sub, words, opts, &stash); sub++; if (sub > max_subs) break; real_get(cpuid_fd, reg, sub, words, FALSE); } } else if (reg == 0x23) { unsigned int mask = words[WORD_EAX]; print_reg(reg, 0, words, opts, &stash); unsigned int sub; for (sub = 1; sub < 32; sub++) { if (mask & (1 << sub)) { real_get(cpuid_fd, reg, sub, words, FALSE); print_reg(reg, sub, words, opts, &stash); } } } else if (reg == 0x24) { unsigned int max_subs = words[WORD_EAX]; unsigned int sub = 0; for (;;) { print_reg(reg, sub, words, opts, &stash); sub++; if (sub > max_subs) break; real_get(cpuid_fd, reg, sub, words, FALSE); } } else if (reg == 0x80000026) { print_reg(reg, 0, words, opts, &stash); unsigned int sub; for (sub = 1; sub < 256; sub++) { real_get(cpuid_fd, reg, sub, words, FALSE); print_reg(reg, sub, words, opts, &stash); // exit when level type indicates invalid (0). if (BIT_EXTRACT_LE(words[WORD_ECX], 8, 16) == 0) break; } } else { print_reg(reg, 0, words, opts, &stash); } } max = 0x20000000; for (reg = 0x20000000; reg <= max; reg++) { boolean success; unsigned int words[WORD_NUM]; success = real_get(cpuid_fd, reg, 0, words, TRUE); if (!success) break; if (reg == 0x20000000) { max = words[WORD_EAX]; if (max > 0x20000100) { // Pentium 4 (and probably many early CPUs) don't support this // leaf correctly and return garbage (which appears to be a // replica of the values for the last valid leaf in the // 0x0xxxxxxx range). As a sanity check to avoid an absurdly // long dump, if the value obviously is out-of-range, just // disable all further 0x2xxxxxxx leaves. max = 0x20000000; } } print_reg(reg, 0, words, opts, &stash); } if (BIT_EXTRACT_LE(stash.val_1_ecx, 31, 32)) { // Xen (and probably other hypervisors in the future) support // configurable ranges, so that hypervisors can exist under other // hypervisors. Walk the possible base addresses looking for valid // hypervisors. See Xen's tools/misc/xen-detect.c for the reg range & // stride. unsigned int base = 0x40000000; for (; base < 0x40010000; base += 0x100) { // Use the base leaf to determine if this is a valid hypervisor, its // identity, and its max register. Always print the base leaf, even // if it's invalid (to clearly indicate that it is). { boolean success; unsigned int words[WORD_NUM]; success = real_get(cpuid_fd, base, 0, words, TRUE); if (!success) break; print_reg(base, 0, words, opts, &stash); max = words[WORD_EAX]; if (stash.hypervisor == HYPERVISOR_KVM && max == 0) { max = base + 1; } // Check for broken hypervisor information. If it looks broken, // skip the reg loop, and break out of the base loop. Note that // HYPERVISOR_UNKNOWN does not imply broken by itself! if (stash.hypervisor == HYPERVISOR_UNKNOWN && max > base + 0x100) { break; } if (max < base) { break; } } // For a valid hypervisor, walk all additional leaves. for (reg = base+1; reg <= max; reg++) { boolean success; unsigned int words[WORD_NUM]; success = real_get(cpuid_fd, reg, 0, words, TRUE); if (!success) break; if (IS_HYPERVISOR_LEAF(reg, 3) && stash.hypervisor == HYPERVISOR_XEN) { unsigned int sub = 0; while (sub <= 2) { print_reg(reg, sub, words, opts, &stash); sub++; real_get(cpuid_fd, reg, sub, words, FALSE); } } else { print_reg(reg, 0, words, opts, &stash); } } } } max = 0x80000000; for (reg = 0x80000000; reg <= max; reg++) { boolean success; unsigned int words[WORD_NUM]; success = real_get(cpuid_fd, reg, 0, words, TRUE); if (!success) break; if (reg == 0x80000000) { max = words[WORD_EAX]; } if (reg == 0x8000001d) { unsigned int sub = 0; while ((words[WORD_EAX] & 0x1f) != 0) { print_reg(reg, sub, words, opts, &stash); sub++; real_get(cpuid_fd, reg, sub, words, FALSE); } } else if (reg == 0x80000020) { unsigned int mask = words[WORD_EBX]; print_reg(reg, 0, words, opts, &stash); unsigned int sub; for (sub = 1; sub < 32; sub++) { if (mask & (1 << sub)) { real_get(cpuid_fd, reg, sub, words, FALSE); print_reg(reg, sub, words, opts, &stash); } } } else { print_reg(reg, 0, words, opts, &stash); } } max = 0x80860000; for (reg = 0x80860000; reg <= max; reg++) { boolean success; unsigned int words[WORD_NUM]; success = real_get(cpuid_fd, reg, 0, words, TRUE); if (!success) break; if (reg == 0x80860000) { max = words[WORD_EAX]; } print_reg(reg, 0, words, opts, &stash); } max = 0xc0000000; for (reg = 0xc0000000; reg <= max; reg++) { boolean success; unsigned int words[WORD_NUM]; success = real_get(cpuid_fd, reg, 0, words, TRUE); if (!success) break; if (reg == 0xc0000000) { max = words[WORD_EAX]; } if (max > 0xc0001000) { // Assume some busted cpuid information and stop walking // further 0x4xxxxxxx registers. max = 0xc0000000; } print_reg(reg, 0, words, opts, &stash); } do_final(opts, &stash); close(cpuid_fd); } } static void do_file(ccstring filename, const print_opts_t* opts) { boolean seen_cpu = FALSE; unsigned int cpu = -1; /* ** The legacysub variable is a kludge to deal with those leaves that depend ** on the sub (a.k.a. ecx) values when the input is in cpuid's legacy style ** of dumping raw leaves, which lacked an explicit indication of the sub ** number. The lastreg also is used to reset the legacysub to 0 for new ** leaves. */ unsigned int lastreg = -1; unsigned int legacysub = 0; code_stash_t stash = NIL_STASH; FILE* file; if (strcmp(filename, "-") == 0) { file = stdin; } else { file = fopen(filename, "r"); if (file == NULL) { fprintf(stderr, "%s: unable to open %s; errno = %d (%s)\n", program, filename, errno, strerror(errno)); exit(1); } } while (!feof(file)) { char buffer[88]; char* ptr; int status; unsigned int reg; unsigned int sub; unsigned int words[WORD_NUM]; ptr = fgets(buffer, LENGTH(buffer), file); if (ptr == NULL && errno == 0) break; if (ptr == NULL) { if (errno != EPIPE) { fprintf(stderr, "%s: unable to read a line of text from %s;" " errno = %d (%s)\n", program, filename, errno, strerror(errno)); } exit(1); } status = sscanf(ptr, "CPU %u:\r", &cpu); if (status == 1 || strcmp(ptr, "CPU:\n") == SAME) { if (seen_cpu) { do_final(opts, &stash); } seen_cpu = TRUE; if (status == 1) { printf("CPU %u:\n", cpu); } else { printf("CPU:\n"); } lastreg = -1; legacysub = 0; { static code_stash_t empty_stash = NIL_STASH; stash = empty_stash; } continue; } status = sscanf(ptr, " 0x%x 0x%x: eax=0x%x ebx=0x%x ecx=0x%x edx=0x%x\r", ®, &sub, &words[WORD_EAX], &words[WORD_EBX], &words[WORD_ECX], &words[WORD_EDX]); if (status == 6) { print_reg(reg, sub, words, opts, &stash); lastreg = reg; continue; } status = sscanf(ptr, " 0x%x: eax=0x%x ebx=0x%x ecx=0x%x edx=0x%x\r", ®, &words[WORD_EAX], &words[WORD_EBX], &words[WORD_ECX], &words[WORD_EDX]); if (status == 5) { if (reg == lastreg) { legacysub++; } else { legacysub = 0; } print_reg(reg, legacysub, words, opts, &stash); lastreg = reg; continue; } fprintf(stderr, "%s: unexpected input with -f option: %s\n", program, ptr); exit(1); } if (seen_cpu) { do_final(opts, &stash); } if (file != stdin) { fclose(file); } } int main(int argc, string argv[]) { static ccstring shortopts = "+hH1ikrdf:vl:s:S"; static const struct option longopts[] = { { "help", no_argument, NULL, 'h' }, { "one-cpu", no_argument, NULL, '1' }, { "inst", no_argument, NULL, 'i' }, { "kernel", no_argument, NULL, 'k' }, { "raw", no_argument, NULL, 'r' }, { "debug", no_argument, NULL, 'd' }, { "file", required_argument, NULL, 'f' }, { "version", no_argument, NULL, 'v' }, { "leaf", required_argument, NULL, 'l' }, { "subleaf", required_argument, NULL, 's' }, { "simple", no_argument, NULL, 'S' }, { NULL, no_argument, NULL, '\0' } }; boolean opt_one_cpu = FALSE; boolean opt_inst = FALSE; boolean opt_kernel = FALSE; cstring opt_filename = NULL; boolean opt_version = FALSE; boolean opt_leaf = FALSE; unsigned long opt_leaf_val = 0; boolean opt_subleaf = FALSE; unsigned long opt_subleaf_val = 0; print_opts_t opts = NIL_PRINT_OPTS; program = strrchr(argv[0], '/'); if (program == NULL) { program = argv[0]; } else { program++; } opterr = 0; for (;;) { int longindex; int opt = getopt_long(argc, argv, shortopts, longopts, &longindex); if (opt == EOF) break; switch (opt) { case 'h': case 'H': usage(); /*NOTREACHED*/ break; case '1': opt_one_cpu = TRUE; break; case 'i': opt_inst = TRUE; break; case 'k': opt_kernel = TRUE; break; case 'r': opts.raw = TRUE; break; case 'd': opts.debug = TRUE; break; case 'f': opt_filename = optarg; break; case 'v': opt_version = TRUE; break; case 'l': opt_leaf = TRUE; { errno = 0; char* endptr = NULL; opt_leaf_val = strtoul(optarg, &endptr, 0); if (errno != 0) { fprintf(stderr, "%s: argument to -l/--leaf not understood: %s\n", program, argv[optind-1]); exit(1); } } break; case 's': opt_subleaf = TRUE; { errno = 0; char* endptr = NULL; opt_subleaf_val = strtoul(optarg, &endptr, 0); if (errno != 0) { fprintf(stderr, "%s: argument to -s/--subleaf not understood: %s\n", program, argv[optind-1]); exit(1); } } break; case 'S': opts.simple = TRUE; break; case '?': default: if (optopt == '\0') { fprintf(stderr, "%s: unrecognized option: %s\n", program, argv[optind-1]); } else { fprintf(stderr, "%s: unrecognized option letter: %c\n", program, optopt); } usage(); /*NOTREACHED*/ } } if (optind < argc) { fprintf(stderr, "%s: unrecognized argument: %s\n", program, argv[optind]); usage(); /*NOTREACHED*/ } #ifndef USE_CPUID_MODULE if (opt_kernel) { fprintf(stderr, "%s: unrecognized argument: -k\n", program); usage(); /*NOTREACHED*/ } #endif if (opt_inst && opt_kernel) { fprintf(stderr, "%s: -i/--inst and -k/--kernel are incompatible options\n", program); exit(1); } if (opt_filename != NULL && opt_leaf) { fprintf(stderr, "%s: -f/--file and -l/--leaf are incompatible options\n", program); exit(1); } if (opt_subleaf && !opt_leaf) { fprintf(stderr, "%s: -s/--subleaf requires that -l/--leaf also be specified\n", program); exit(1); } // Default to -i. So use inst unless -k is specified. boolean inst = !opt_kernel; if (opt_version) { printf("cpuid version %s\n", XSTR(VERSION)); } else { if (opt_filename != NULL) { do_file(opt_filename, &opts); } else if (opt_leaf) { do_real_one(opt_leaf_val, opt_subleaf_val, opt_one_cpu, inst, &opts); } else { do_real(opt_one_cpu, inst, &opts); } } exit(0); /*NOTREACHED*/ } cpuid-20250316/FAMILY.NOTES0000666001234300001440000006462414764564321013562 0ustar toddusersIntel Core architecture: Launch -------Mobile------- ----Desktop/UP Server---- CL Server DP Server MP Server -------------------------------------------------------------------------------------------------------------- 2006 1-core 65nm Merom-L Conroe-L 2-core 65nm Merom-2M Merom Allendale Conroe Conroe-CL Woodcrest Tigerton-DC 4-core 65nm Kentsfield Clovertown Tigerton -------------------------------------------------------------------------------------------------------------- 2007 1-core 45nm Penryn-L Wolfdale-CL 2-core 45nm Merom-3M Penryn Wolfdale-3M Wolfdale Wolfdale-CL Wolfdale-DP 4-core 45nm Penryn-QC Yorkfield-6M Yorkfield Yorkfield-CL Harpertown Dunnington-QC 6-core 34nm Dunnington -------------------------------------------------------------------------------------------------------------- Intel Nehalem architecture (sometimes called 1st generation) (LGA 1156/1366): Desktop/ Launch uArch Mobile UP Server DP Server MP Server ----------------------------------------------------------------------------------- 2008 Nehalem 8-core 45nm Beckton 4-core 45nm Bloomfield Gainestown 4-core 45nm Clarksfield Lynnfield Jasper Forest ----------------------------------------------------------------------------------- 2010 Westmere 12-core 32nm Westmere-EX 6-core 32nm Gulftown Westmere-EP 2-core 32nm Arrandale Clarkdale ----------------------------------------------------------------------------------- Intel *Bridge, *well, *Lake, *Cove: (Desktop) ========================Server (Xeon)======================== Launch Marketing uArch Relationships Core Socket Gen uArch Platform Socket --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- 2011 2000 Series Sandy Bridge new architecture LGA 1155 (same) LGA 2011: R 2012 3000 Series Ivy Bridge shrink of Sandy Bridge (22nm) LGA 1155 (same) LGA 2011: R --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- 2013 4000 Series Haswell new architecture LGA 1150 (same) Grantley LGA 2011-v3: R3 2014 5000 Series Broadwell shrink of Haswell (14nm) LGA 1150 (same) Grantley LGA 2011-v3: R3 --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- 2015 6000 Series Skylake new architecture LGA 1151/2066 1st (same) Purley LGA 3647-0: P 2019 Cascade Lake optim of Skylake, DL Boost, spectre/meltdown LGA 2066 2nd (same) Purley LGA 3647-0: P 2020 Cooper Lake optim of Cascade Lake, bfloat16, more cores 3rd (same) Whitley LGA 4189: P+ 2016 7000 Series Kaby Lake optim of Skylake, higher clock (14nm+) LGA 1151/2066 2016 Kaby Lake R refresh of Kaby Lake named 8000 Series LGA 1151 2017 8000 Series Coffee Lake optim of Kaby Lake, 1.5x CPUs/die (14nm++) LGA 1151 2018 Whiskey Lake *optim of Kaby Lake, mobile (U) (14nm++) 2018 Amber Lake *optim of Kaby Lake, extreme low power (Y) 2018 Palm Cove shrink of Kaby Lake (10nm), AVX-512 (Cannon Lake) 2017 9000 Series Coffee Lake refresh of Coffee Lake, spectre/meltdown LGA 1151 2019 10000 Series Comet Lake *optim of {Coffee, Whiskey} Lake (K,U) LGA 1200 --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- 2019 10000 Series Sunny Cove new architecture (Ice Lake) (10nm) 3rd (same) Whitley LGA 4189: P+ 2020 11000 Series Willow Cove optim of Sunny Cove (Tiger Lake) (10nm) 2021 Cypress Cove backport of Willow Cove (Rocket Lake) (14nm) LGA 1200 --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- 2021 12000 Series Golden Cove new architecture (Alder Lake) (Intel 7) LGA 1700 4th Sapphire Rapids Eagle Stream LGA 4677 2022 13000 Series Raptor Cove modified Golden Cove (Raptor Lake) (Intel 7) LGA 1700 5th Emerald Rapids (H2'23) Eagle Stream LGA 4677 2023 14000 Series Raptor Cove refreshed Raptor Cove (Intel 7) 2023 Core Ultra 100 Redwood Cove modified Raptor Cove (Meteor Lake) (Intel 4) <-?-> 6th Granite Rapids (2024) Birch Stream LGA 7529 --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- 2024 Core Ultra 200 Lion Cove new architecture (Arrow Lake (TSMC N3) desktop) LGA 1851 2024 " " " (Lunar Lake (TSMC N3B) AI/low power) BGA 2833 --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- ? Raptor Cove? (Bartlett Lake?) (Q1'25?) LGA 1700? ? Core Ultra 300? Lion Cove refresh of Lion Cove (Arrow Lake? (Intel 20A)) (2025) LGA 1851? ? Cougar Cove? (Panther Lake (Intel 18A?)) (mobile-only?) (2025) LGA 1851? ? - Panther Cove? <-?-> 7th Diamond Rapids (2025) Mountain Stream LGA 9324? ? Core Ultra 400? Coyote Cove? (Nova Lake? (Intel 18A?)) (2026) --------------------------------------------------------------------------------------------------------------------------------------------------------------------------- * = I'm not treating this as a distinct uarch, but just as a core within its parent uarch, Kaby Lake Alder Lake variants: -S desktop, -P = mobile, -M = low-power, -L = atom replacement, -N educational "Lines" (suffixes): K = unlocked (overclockable) (usually doesn't include cooler) Mobile = mobile F = does not include GPU G = includes GPU H = high performance GPU T = power-optimized U = ultra low power Y = extremely lower power (even lower than U) S = special edition (>= 9000) or performance-optimized (<= 4000) Sapphire Rapids-HBM (high bandwidth memory) is branded as "Xeon Max". Hybrids: Launch Combined P-cores E-cores --------------------------------------------------------------------- 2020 Lakefield 1x Sunny Cove + 4x Tremont (more of a prototype) --------------------------------------------------------------------- 2021 Alder Lake {2,6,8}x Golden Cove + {0,8}x Gracemont 2022 Raptor Lake 8x Raptor Cove + 16x Gracemont 2023 Meteor Lake {2,4,6}x Redwood Cove + {4,8}x Crestmont --------------------------------------------------------------------- 2024 Arrow Lake {6,8}x Lion Cove + {8,12,16}x Skymont (desktop) 2024 Lunar Lake 4x Lion Cove + 4x Skymont (AI/low power) --------------------------------------------------------------------- ? Panther Lake Cougar Cove? + Darkmont ? Nova Lake Coyote Cove? + Arctic Wolf? --------------------------------------------------------------------- Intel Atom architectures: Launch uArch Hybrid E-core Servers Network PCs Notebooks Embedded/Automotive Mobile phones ----------------------------------------------------------------------------------------------------------------------------------------- 2008 Bonnell Diamondville Silverthorne Bonnell 2 Pineview Tunnel Creek/Stellarton Lincroft 2011 Saltwell Centerton Cedarview Medfield " Clover Trail ----------------------------------------------------------------------------------------------------------------------------------------- 2013 Silvermont Avoton Rangeley Bay Trail Bay Trail Bay Trail Merrifield " Moorefield " SoFIA 2015 Airmont Braswell Cherry Trail Braswell ----------------------------------------------------------------------------------------------------------------------------------------- 2016 Goldmont Denverton Apollo Lake Willow Trail* Apollo Lake Apollo Lake 2017 Goldmont+ Gemini Lake ----------------------------------------------------------------------------------------------------------------------------------------- 2020 Tremont Lakefield Elkhart Lake Snow Ridge Skyhawk Lake/ Elkhart Lake Parker Ridge Jasper Lake ----------------------------------------------------------------------------------------------------------------------------------------- 2021 Gracemont Alder Lake Alder Lake-N/ Arizona Beach Twin Lake Raptor Lake ----------------------------------------------------------------------------------------------------------------------------------------- 2023 Crestmont Meteor Lake Sierra Forest Grand Ridge ----------------------------------------------------------------------------------------------------------------------------------------- 2024 Skymont Arrow Lake Lunar Lake ----------------------------------------------------------------------------------------------------------------------------------------- Darkmont Panther Lake? Clearwater Forest ? Arctic Wolf Nova Lake? ----------------------------------------------------------------------------------------------------------------------------------------- Server: uArch Core Platform SoC --------------------------------------------------------- Saltwell Centerton Bordenville Centerton Saltwell ? ? Briarwood ---------------------------------------------------------- Silvermont Avoton ? Avoton --------------------------------------------------------- Tremont Elkhart Lake Jacobsville --------------------------------------------------------- Crestmont Sierra Forest --------------------------------------------------------- Darkmont Clearwater Forest --------------------------------------------------------- Notebooks: uArch Core Platform SoC ----------------------------------------------------- Bonnell Diamondville Bonnell 2 Pineview Pine Trail-M Bonnell 2 Lincroft ! Oak Trail Saltwell Cedarview Cedar Trail ------------------------------------------------------ Silvermont Bay Trail-T Bay Trail Valleyview Airmont Cherry Trail Cherry Trail Cherryview ------------------------------------------------------ Goldmont Willow Trail* Willow Trail Broxton ----------------------------------------------------- Gracemont Alder Lake-N/ Twin Lake ----------------------------------------------------- Embedded: uArch Core/SoC Platform -------------------------------------- Bonnell 2 Tunnel Creek Queens Bay -------------------------------------- Silvermont Bay Trail -------------------------------------- Airmont Braswell -------------------------------------- Goldmont Apollo Lake -------------------------------------- Tremont Elkhart Lake -------------------------------------- Gracemont Arizona Beach -------------------------------------- Mobile phones: uArch Core Platform SoC ------------------------------------------------------ Stealey McCaslin Bonnell Silverthorne Menlow Bonnell 2 Lincroft Moorestown Saltwell Medfield Medfield Penwell Saltwell Medfield Medfield Lexington Saltwell Clover Trail Clover Trail+ Cloverview ------------------------------------------------------ Silvermont Merrifield Merrifield Tangier Silvermont Moorefield Moorefield Anniedale ------------------------------------------------------ Goldmont Apollo Lake Morganfield Broxton ------------------------------------------------------ * Canceled core ! Surprising use of wrong-market core Intel Phi (brand name) / MIC (architecture name): (research) : Larrabee (derived from P54C) Knights Ferry : 24 Aubrey Isle {K1OM}, derived from Larrabee cores Knights Corner : 50 (Aubrey Isle-derived) {K1OM} cores Knights Landing : 72 Airmont cores Knights Hill : (canceled; would've shrunk Knights Landing to 10nm) Knights Mill : 72 Airmont(?) cores Intel AI: Spring Hill : 2x Sunny Cove (derived) cores + 12 ICE (Vision P6 DSP) ====================================================================================================================================== AMD K8-based Platforms (includes K10 & its derivatives): Mobile Platform Athlon m-Athlon Sempron m-Sempron Turion -------------------------------------------------------------------------------------------- Initial (CG) NewCastle Clawhammer/Odessa Paris Dublin Initial (D0) Winchester Oakville Palermo Sonora Initial (E3) Venice Palermo Palermo Initial (E4) San Diego Initial (E5) Newark Lancaster/Richmond Initial (E6) Venice Palermo Albany/Roma Kite (F2) Orleans Manila Keene Taylor/Trinidad Kite R (G1) Brisbane Sparta Sherman Tyler Puma Lion Sable Lion Yukon Huron/Brisbane Huron Congo Tigris/Danube Sargas/Regor Sargas Caspian/Champlain Nile Geneva -------------------------------------------------------------------------------------------- AMD Bobcat - Puma (2014): Desktop Mobile Server Embedded --------------------------------------------------------------------------------------------------------------------------------------- Bobcat Ontario/Desna/Zacate Ontario/Zacate --------------------------------------------------------------------------------------------------------------------------------------- Bulldozer Zambezi Interlagos/Valencia/Zurich Piledriver Trinity Trinity Trinity (update) Richland Richland Steamroller Kaveri Kaveri Berlin (canceled) Bald Eagle (refresh) Godavari Excavator Carrizo Carrizo Toronto Brown Falcon/Merlin Falcon (+) Bristol Ridge/Stoney Ridge Bristol Ridge/Stoney Ridge Prairie Falcon --------------------------------------------------------------------------------------------------------------------------------------- Jaguar Kabini/(PS4)/(Xbox One) Kabini/Temash Kyoto Kabini Puma (2014) Beema/Mullins Steppe Eagle (SoC)/Crowned Eagle (CPU) --------------------------------------------------------------------------------------------------------------------------------------- A-Series = APU (Desktop/Mobile) E-Series = cheaper version of A-Series G-Series = Embedded AMD Zen and later: Desktop Desktop Enthusiast Mobile Server Embedded -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- Zen (14nm) 1000: Summit Ridge 1000: Whitehaven 2000: Raven Ridge 1st Gen: Naples/Snowy Owl V1000: Great Horned Owl/R1000: Banded Kestrel 1000: Dali 1000: Dali Zen+ (12nm) 2000: Pinnacle Ridge 2000: Colfax 3000: Picasso 3000: Picasso Zen 2 (7nm) 3000: Castle Peak 2nd Gen: Rome==Starship V2000: Grey Hawk (update) 3000: Matisse 4000: Renoir 5000: Lucienne 7000: Mendocino Cardinal (PS5) Van Gogh (Steam Deck) ProjectX (Xbox X) Mero (MagicLeap Demophon) Zen 3 (7nm) 5000: Vermeer 5000: Chagall==Genesis Peak 5000: Cezanne/Barcelo 3rd Gen: Milan 6000/7000: Rembrandt V3000: still Rembrandt? Trento (Frontier super) Badami (?) Zen 4 (5nm) 7000: Raphael 7000: Storm Peak 7000/8000: Phoenix 4th Gen: Genoa{==Stones?}(standard) 7000: Dragon Range (MI300 super) 8000: Hawk Point Zen 4c (N5) 4th Gen: 97x4: Bergamo{==Stones-dense?}(cloud) 4th Gen: 8xy4: Siena{==Stones-dense?}(edge) Zen 5 (N4P) 9000: Granite Ridge AI 300: Strix Point 5th Gen: 9xy5: Turin{==Breithorn} Zen 5c (N3) 5th Gen: 9xy5: Sorano{==Breithorn-dense}(edge?) -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- ? 9000: Shimada Peak? 9000: Fire Range ? 9000: Krackan Point(edge)? ? AI ???: Strix Halo==Sarlak? ? AI ???: Bald Eagle Point? ? Escher? ? Zen 6 10000: Medusa (2026)? 6th Gen: Venice==Weisshorn -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- Ryzen = Desktop/Mobile Ryzen Threadripper = Desktop Enthusiast (64-core) EPYC = Server Ryzen numbering, before circa 2022: single digit: 3 = mainstream (4-core) 5 = high performance (6-core) 7 = enthusiast (8-core) 9 = prosumer (16-core) 1st digit: generation 2nd digit (performance) (old): 1,2,3 = mainstream 4,5,6 = high performance 7,8 = enthusiast 9 = prosumer Suffixes: (none) = ordinary desktop G = includes GPU GE = lower power GPU E = lowest power GPU X = high performance (XFR) T = turbo clock speeds (often combined with X) HX = mobile: high performance > 45W (big laptops) H = mobile: high performance 45W (big laptops) HS = mobile: high performance 35W U = mobile: ultra low power (thin laptops) C = chromebook Ryzen numbering, after circa 2022: 1st digit: year 7 = 2023 8 = 2024 9 = 2025 2nd digit (performance) (new): 1 = Athlon Silver 2 = Athlon Gold 3,4 = Ryzen 3 5,6 = Ryzen 5 7 = Ryzen 7 8 = Ryzen 7/9 9 = Ryzen 9 3rd digit: architecture 1 = Zen/Zen+ 2 = Zen 2 3 = Zen 3 4 = Zen 4 5 = Zen 5 4th digit: segment 0 = lower 5 = higher Suffixes: HX = mobile: high performance >= 55W (big laptops) HS = mobile: high performance 35W U = mobile: ultra low power 15-28W (thin laptops) e = lowest power 9W C = chromebook ====================================================================================================================================== Zhaoxin (VIA + Shanghai Municipal Government), began ~2013: 2015 1st gen: ZhangJiang (incl. KaiXian (desktop), Kaisheng (server)) 2017 2nd gen: WuDaoKou 2019 3rd gen: LuJiaZui (e.g. KX-U6880) 2022 ------- Shijidadao (KX-7000) : rebadged Intel Alder Lake (e.g. Core i*-N300) or Raptor Lake? (selling rebadged Intel Xeon's after 2022 US BIS Entity List export restrictions?) ====================================================================================================================================== Hygon (AMD + THATIC (AMD + various Chinese companies)), began ~2016: 2018 Dhyana A1/A2 (C86 3185/3188) <=2022 Dhyana B1 (C86 3250) <=2024 Dhyana C1 (C86 3350) 2024 Dhyana ? (C86 7390/7490) (9,15),(0,4),1 maybe? (forked from AMD Zen 1 because of 2022 US BIS Entity List export restrictions) ====================================================================================================================================== Montage (Intel + Montage + Tsinghua University), began ~2016: 2020 Jintide 1st Gen (X____ series) : Intel Skylake Xeon + Tsinghua University RCP Jintide 2nd Gen (C_2__R series) : rabadged Intel Xeon 2nd Gen Scalable (Cascade Lake)? Jintide 3rd Gen (C_3__ series) : rabadged Intel Xeon 3rd Gen Scalable (Ice Lake)? Jintide 4th Gen (C_4__ series) : rabadged Intel Xeon 4th Gen Scalable (Sapphire Rapids)? Jintide 5th Gen (C_5__ series) : rabadged Intel Xeon 5th Gen Scalable (Emerald Rapids)? Jintide 6th Gen (C_7__E series) : rabadged Intel Xeon 6 (Sierra Forest)? (selling rebadged Intel Xeon's after 2022 US BIS Entity List export restrictions?) cpuid-20250316/Makefile0000666001234300001440000001520414765705212013412 0ustar toddusersCFLAGS+=-g CPPFLAGS?= LDFLAGS?= ifneq (,$(findstring arch=i386,$(CFLAGS))) CISA=-m32 endif CFL=$(CPPFLAGS) $(CFLAGS) $(CISA) -Wall -W -Wshadow -Wcast-align -Wredundant-decls -Wbad-function-cast -Wcast-qual -Wwrite-strings -Waggregate-return -Wstrict-prototypes -Wmissing-prototypes -Wimplicit-fallthrough -Wunused-parameter -Wundef -D_FILE_OFFSET_BITS=64 -DVERSION=$(VERSION) CFL_OPT=-O3 $(CFL) -Wformat-overflow=2 INSTALL_STRIP=-s PACKAGE=cpuid VERSION=20250316 RELEASE=1 PROG=$(PACKAGE) SRC_TAR=$(PACKAGE)-$(VERSION).src.tar.gz i386_TAR=$(PACKAGE)-$(VERSION).i386.tar.gz x86_64_TAR=$(PACKAGE)-$(VERSION).x86_64.tar.gz TARS=$(SRC_TAR) $(i386_TAR) $(x86_64_TAR) SRC_RPM=$(PACKAGE)-$(VERSION)-$(RELEASE).src.rpm i386_RPM=$(PACKAGE)-$(VERSION)-$(RELEASE).i386.rpm x86_64_RPM=$(PACKAGE)-$(VERSION)-$(RELEASE).x86_64.rpm RPMS=$(SRC_RPM) $(i386_RPM) $(x86_64_RPM) i386_DEBUG_RPM=$(PACKAGE)-debuginfo-$(VERSION)-$(RELEASE).i386.rpm x86_64_DEBUG_RPM=$(PACKAGE)-debuginfo-$(VERSION)-$(RELEASE).x86_64.rpm DEBUG_RPMS=$(i386_DEBUG_RPM) $(x86_64_DEBUG_RPM) i386_DEBUGSOURCE_RPM=$(PACKAGE)-debugsource-$(VERSION)-$(RELEASE).i386.rpm x86_64_DEBUGSOURCE_RPM=$(PACKAGE)-debugsource-$(VERSION)-$(RELEASE).x86_64.rpm DEBUGSOURCE_RPMS=$(i386_DEBUGSOURCE_RPM) $(x86_64_DEBUGSOURCE_RPM) SRCS=cpuid.c OTHER_SRCS=Makefile $(PROG).man cpuinfo2cpuid \ $(PACKAGE).proto.spec $(PACKAGE).spec \ ChangeLog FUTURE FAMILY.NOTES LICENSE OTHER_BINS=$(PROG).man cpuinfo2cpuid.man REL_DIR=../$(shell date +%Y-%m-%d) WEB_DIR=/toad2/apps.mine/www/www/$(PROG) BUILDROOT=$(DESTDIR) default: $(PROG) $(PROG).man.gz cpuinfo2cpuid cpuinfo2cpuid.man.gz $(PROG): cpuid.c Makefile $(CC) $(CFL) $(LDFLAGS) -o $@ cpuid.c $(PROG).opt: cpuid.c Makefile $(CC) $(CFL_OPT) $(LDFLAGS) -o $@ cpuid.c opt: $(PROG).opt $(PROG).man.gz: $(PROG).man gzip < $< > $@ cpuinfo2cpuid.man: cpuinfo2cpuid Makefile pod2man -r "$(VERSION)" -c "" $< > $@ cpuinfo2cpuid.man.gz: cpuinfo2cpuid.man gzip < $< > $@ install: $(PROG) $(PROG).man.gz cpuinfo2cpuid cpuinfo2cpuid.man.gz install -D $(INSTALL_STRIP) -m 755 $(PROG) $(BUILDROOT)/usr/bin/$(PROG) install -D -m 444 $(PROG).man.gz $(BUILDROOT)/usr/share/man/man1/$(PROG).1.gz install -D -m 755 cpuinfo2cpuid $(BUILDROOT)/usr/bin/cpuinfo2cpuid install -D -m 444 cpuinfo2cpuid.man.gz $(BUILDROOT)/usr/share/man/man1/cpuinfo2cpuid.1.gz clean: rm -f $(PROG) $(PROG).opt $(PROG).i386 $(PROG).x86_64 rm -f $(PROG).man.gz rm -f cpuinfo2cpuid.man cpuinfo2cpuid.man.gz rm -f $(PACKAGE).spec rm -f $(TARS) rm -f $(RPMS) rm -f $(DEBUG_RPMS) rm -f $(DEBUGSOURCE_RPMS) rm -f $(PACKAGE)-*.src.tar.gz $(PACKAGE)-*.i386.tar.gz $(PACKAGE)-*.x86_64.tar.gz rm -f $(PACKAGE)-*.src.rpm $(PACKAGE)-*.i386.rpm $(PACKAGE)-*.x86_64.rpm rm -f $(PACKAGE)-debuginfo-*.i386.rpm $(PACKAGE)-debuginfo-*.x86_64.rpm # Todd's Development rules $(PROG).i386: cpuid.c Makefile $(CC) -m32 -static -O3 $(CFL) $(LDFLAGS) -o $@ cpuid.c $(PROG).x86_64: cpuid.c Makefile $(CC) -static -O3 $(CFL) $(LDFLAGS) -o $@ cpuid.c todd: $(PROG).i386 $(PROG).x86_64 rm -f ~/.bin/execs/i586/$(PROG) rm -f ~/.bin/execs/x86_64/$(PROG) cp -p $(PROG).i386 ~/.bin/execs/i586/$(PROG) cp -p $(PROG).x86_64 ~/.bin/execs/x86_64/$(PROG) chmod 777 ~/.bin/execs/i586/$(PROG) chmod 777 ~/.bin/execs/x86_64/$(PROG) (cd ~/.bin/execs; prop i586/$(PROG) x86_64/$(PROG)) # Release rules $(PACKAGE).spec: $(PACKAGE).proto.spec @(echo "%define version $(VERSION)"; \ echo "%define release $(RELEASE)"; \ cat $<) > $@ $(SRC_TAR): $(SRCS) $(OTHER_SRCS) @echo "Tarring source" @rm -rf $(PACKAGE)-$(VERSION) @mkdir $(PACKAGE)-$(VERSION) @ls -1d $(SRCS) $(OTHER_SRCS) | cpio -pdmuv $(PACKAGE)-$(VERSION) @tar cvf - $(PACKAGE)-$(VERSION) | gzip -c >| $(SRC_TAR) @rm -rf $(PACKAGE)-$(VERSION) $(i386_TAR): $(PROG).i386 $(OTHER_BINS) @echo "Tarring i386 binary" @rm -rf $(PACKAGE)-$(VERSION) @mkdir $(PACKAGE)-$(VERSION) @ls -1d $(PROG).i386 $(OTHER_BINS) | cpio -pdmuv $(PACKAGE)-$(VERSION) @mv $(PACKAGE)-$(VERSION)/$(PROG).i386 $(PACKAGE)-$(VERSION)/$(PROG) @(cd $(PACKAGE)-$(VERSION); strip $(PROG)) @tar cvf - $(PACKAGE)-$(VERSION) | gzip -c >| $(i386_TAR) @rm -rf $(PACKAGE)-$(VERSION) $(x86_64_TAR): $(PROG).x86_64 $(OTHER_BINS) @echo "Tarring x86_64 binary" @rm -rf $(PACKAGE)-$(VERSION) @mkdir $(PACKAGE)-$(VERSION) @ls -1d $(PROG).x86_64 $(OTHER_BINS) | cpio -pdmuv $(PACKAGE)-$(VERSION) @mv $(PACKAGE)-$(VERSION)/$(PROG).x86_64 $(PACKAGE)-$(VERSION)/$(PROG) @(cd $(PACKAGE)-$(VERSION); strip $(PROG)) @tar cvf - $(PACKAGE)-$(VERSION) | gzip -c >| $(x86_64_TAR) @rm -rf $(PACKAGE)-$(VERSION) src_tar: $(SRC_TAR) tar tars: $(TARS) $(i386_RPM) $(i386_DEBUG_RPM) $(i386_DEBUGSOURCE_RPM) $(SRC_RPM): $(SRC_TAR) $(PACKAGE).spec @echo "Building i386 RPMs" @rm -rf build buildroot @mkdir buildroot @mkdir build @rpmbuild -v -ba --target i386 \ --buildroot "${PWD}/buildroot" \ --define "_builddir ${PWD}/build" \ --define "_rpmdir ${PWD}" \ --define "_srcrpmdir ${PWD}" \ --define "_sourcedir ${PWD}" \ --define "_specdir ${PWD}" \ --define "_rpmfilename %%{NAME}-%%{VERSION}-%%{RELEASE}.%%{ARCH}.rpm" \ $(PACKAGE).spec @rm -rf build buildroot $(x86_64_RPM) $(x86_64_DEBUG_RPM) $(x86_64_DEBUGSOURCE_RPM): $(SRC_TAR) $(PACKAGE).spec @echo "Building x86_64 RPMs" @rm -rf build buildroot @mkdir buildroot @mkdir build @rpmbuild -v -ba --target x86_64 \ --buildroot "${PWD}/buildroot" \ --define "_builddir ${PWD}/build" \ --define "_rpmdir ${PWD}" \ --define "_srcrpmdir ${PWD}" \ --define "_sourcedir ${PWD}" \ --define "_specdir ${PWD}" \ --define "_rpmfilename %%{NAME}-%%{VERSION}-%%{RELEASE}.%%{ARCH}.rpm" \ $(PACKAGE).spec @rm -rf build buildroot rpm rpms: $(RPMS) # Todd's release rules release: $(PROG) $(PROG).i386 $(PROG).x86_64 $(TARS) $(RPMS) if [ -d $(REL_DIR) ]; then \ echo "Makefile: $(REL_DIR) already exists" >&2; \ exit 1; \ fi mkdir $(REL_DIR) cp -p $(PROG) $(PROG).i386 $(PROG).x86_64 $(SRCS) $(OTHER_SRCS) $(REL_DIR) mv $(TARS) $(RPMS) $(REL_DIR) if [ -e $(i386_DEBUG_RPM) ]; then \ mv $(i386_DEBUG_RPM) $(REL_DIR); \ fi if [ -e $(x86_64_DEBUG_RPM) ]; then \ mv $(x86_64_DEBUG_RPM) $(REL_DIR); \ fi if [ -e $(i386_DEBUGSOURCE_RPM) ]; then \ mv $(i386_DEBUGSOURCE_RPM) $(REL_DIR); \ fi if [ -e $(x86_64_DEBUGSOURCE_RPM) ]; then \ mv $(x86_64_DEBUGSOURCE_RPM) $(REL_DIR); \ fi chmod -w $(REL_DIR)/* cp -f -p $(REL_DIR)/*.tar.gz $(REL_DIR)/*.rpm $(WEB_DIR) rm -f $(PACKAGE).spec rerelease: rm -rf $(REL_DIR) $(MAKE) -$(MAKEFLAGS) release cpuid-20250316/cpuid.proto.spec0000666001234300001440000000160113615561750015070 0ustar toddusersSummary: dumps CPUID information about the CPU(s) Name: cpuid Version: %{version} Release: %{release} License: GPL Group: System Environment/Base Source: cpuid-%{version}.src.tar.gz Packager: Todd Allen URL: http://www.etallen.com/cpuid.html BuildRoot: %{getenv:HOME}/rpmbuild/BUILDROOT/%{name}-%{version}-%{release}.%{_arch} %description cpuid dumps detailed information about the CPU(s) gathered from the CPUID instruction, and also determines the exact model of CPU(s). %prep %setup %build %{__make} %{?_smp_mflags} CFLAGS="$RPM_OPT_FLAGS" %install %{__make} install BUILDROOT=${RPM_BUILD_ROOT} INSTALL_STRIP= %clean %{__rm} -rf $RPM_BUILD_DIR/$RPM_PACKAGE_NAME-$RPM_PACKAGE_VERSION %files %defattr(-,root,root) %{_bindir}/cpuid %{_mandir}/man1/cpuid.1.gz %{_bindir}/cpuinfo2cpuid %{_mandir}/man1/cpuinfo2cpuid.1.gz %doc ChangeLog FUTURE FAMILY.NOTES %license LICENSE cpuid-20250316/FUTURE0000666001234300001440000000570113737062456012714 0ustar toddusersGigabyte: Try using the Gigabyte CPU Support List to verify stepping names. -------------------------------------------------------------------------------- Intel: Cascade Lake refresh Xeons: Xeon Scalable 3xxxR, 4xxxR & 6xxxR (to be released 2020-02-23): still (0,6),(5,5),7? Amber Lake refresh: What is the FMS for its i*-10000 parts? Cannon Lake [Palm Cove] (0,6),(6,6) spec update. Ice Lake [Sunny Cove] (0,6),(6,10) spec update. Ice Lake [Sunny Cove] (0,6),(6,12) spec update. Tiger Lake [Willow Cove] (0,6),(8,13) spec update. Spring Hill (aka Ice Lake NPP-I) (0,6),(9,13) spec update. Comet Lake [Kaby Lake] (0,6),(10,5) spec update. Comet Lake [Kaby Lake] (0,6),(10,6) spec update. Rocket Lake (~2020?) Willow Cove (~2020) Golden Cove (~2021). Sapphire Rapids (~2021). Atom XMM 7272 (SoFIA) (0,6),(6,5) spec update. Atom Elkhart Lake [Tremont] (0,6),(8,6) spec update. (wrong name?) Atom Elkhart Lake [Tremont] (0,6),(9,6) spec update. Atom Jasper Lake [Tremont] (0,6),(9,12) spec update. Atom P5900 (Snow Ridge?) [Tremont]: f/m/s unknown. Atom [Gracemont] (~2021). Atom Puma 7 (0,6),(6,14) spec update. Lakefield (Sunny Cove + 4x Tremont?): Sunny Cove & Tremont FMS? Alder Lake (Golden Cove + Gracemont) [~2021] AMD: Add EPYC series numbers (e.g. EPYC 7000 = Rome) Zen 3 models (Vermeer: desktop, Milan: server, Genesis Peak: Threadripper) -------------------------------------------------------------------------------- These are not really future, but I have very little data on them: Intel: Xeon Phi (Knights Ferry) (0,11),(0,0). Intel: Xeon Phi (Knights Corner) (0,11),(0,1) with 0x20000001 leaf. Intel: Xeon Phi (Knights Mill) (0,6),(8,5). Intel: Atom Z3400 (Merrifield) [Silvermont] (0,6),(4,10). Intel: Atom (Apollo Lake) [Goldmont] (0,6),(5,12),2. Intel: Atom x3-C3000 (SoFIA) [Silvermont] (0,6),(5,13). Intel: Spreadtrum SC9853I-IA [Airmont] (0,6),(7,5). Intel: Atom S12x9 (Briarwood) is based on Cedar Trail, but the Intel docs provide no CPUID identification values. And I can find no examples online. Does anyone know the CPUID family/model/steppings? AMD: Cato (7,15),(2,6) (real or only engr samples?) AMD: Geneva (the Athlon II Neo counterpart of the Athlon II mobile Champlain, or the V-Series Champlain?) [not seen in any revision guides yet, though] VIA: 0xc0000003 leaf (I have no info) VIA: 0xc0000004 leaf (I have no info) Zhaoxin: ZhangJiang (more models/steppings than (0,6),(0,15),14? Zhaoxin: WuDaoKou (more models than (0,7),(1,11)?) Zhaoxin: LuJiaZui (more models than (0,7),(3,11)?) -------------------------------------------------------------------------------- Stashes of cpuid information: http://instlatx64.atw.hu (aka https://github.com/InstLatx64/InstLatx64) http://www.cpu-world.com (hard to navigate) http://valid.x86.fr/records.html (limited info) cpuid-20250316/cpuid.spec0000666001234300001440000000165414765705435013745 0ustar toddusers%define version 20250316 %define release 1 Summary: dumps CPUID information about the CPU(s) Name: cpuid Version: %{version} Release: %{release} License: GPL Group: System Environment/Base Source: cpuid-%{version}.src.tar.gz Packager: Todd Allen URL: http://www.etallen.com/cpuid.html BuildRoot: %{getenv:HOME}/rpmbuild/BUILDROOT/%{name}-%{version}-%{release}.%{_arch} %description cpuid dumps detailed information about the CPU(s) gathered from the CPUID instruction, and also determines the exact model of CPU(s). %prep %setup %build %{__make} %{?_smp_mflags} CFLAGS="$RPM_OPT_FLAGS" %install %{__make} install BUILDROOT=${RPM_BUILD_ROOT} INSTALL_STRIP= %clean %{__rm} -rf $RPM_BUILD_DIR/$RPM_PACKAGE_NAME-$RPM_PACKAGE_VERSION %files %defattr(-,root,root) %{_bindir}/cpuid %{_mandir}/man1/cpuid.1.gz %{_bindir}/cpuinfo2cpuid %{_mandir}/man1/cpuinfo2cpuid.1.gz %doc ChangeLog FUTURE FAMILY.NOTES %license LICENSE